- A documentation of the design flow using Alliance tools.
- Each tools are shortly described, strength and weakness are brieflly commented, - An example for each Alliance file format is given.
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<html>
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<head>
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<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
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<title>Digital design flow</title>
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<!-- Author: Ludovic Jacomme May 2004 -->
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</head>
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<body bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#000080" alink="#FF0000">
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<img src="logo.gif">
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<br>
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<h1>The main steps of the digital design flow</h1>
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<ul>
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<li>Behavioral specification</li>
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<li>RTL synthesis</li>
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<li>Place and Route</li>
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</ul>
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<br>
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<h1>Overview of the behavioral specification step</h1>
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<ul>
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<li>During this step the designer can cut the chip in several functional
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blocks interconnected together
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<br><br><img src=beh-spec-split.gif>
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</li>
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<br>
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<li>Then he has to describe, using a hardware description langage (HDL),
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the behavior of each functional block.<br> Each functional block can be:
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</li>
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<ul>
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<li>a Finite State Machine
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<br><img src=beh-spec-fsm.gif>
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</li>
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<li>a set of registers and transfert functions
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<br><img src=beh-spec-rtl.gif>
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</li>
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<li>a set of interconnected other functional blocks
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<br><img src=beh-spec-struct.gif>
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</li>
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</ul>
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<br>
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<li>The behavioral description has to be validate. The designer can use
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different methods such as:
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<ul>
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<li>digital simulation using a set of stimuli.
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(each stimuli describes the value of inputs pins
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and the expected values of outputs pins)</li>
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<li>model checking using a set of CTL formulae. (each CTL
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formulae describe a property that the functional block has
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to verified)</li>
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</ul>
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</ul>
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<h1>The behavioral specification using the Alliance CAD system</h1>
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<ul>
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<li>Digital simulation using a set of stimuli:
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<a id="asimut" name="asimut"></a>
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<a id="xpat" name="xpat"></a>
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<a id="genpat" name="genpat"></a>
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<br><img src=beh-spec-asimut.gif><br>
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<ul>
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<li><a href="tools.html#genpat">GENPAT</a> is used to write
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digital stimuli. It provides a C
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interface of a set of functions usefull to create stimuli. It
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loads a C file describing patterns and run the C compiler.
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Finally it generates a stimuli file
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(<a href="tools.html#pat">PAT</a> file format).
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Note that patterns file can also
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be written using a simple text editor.
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<br></li>
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<li><a href="tools.html#asimut">ASIMUT</a> is a VHDL simulator.
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It loads behavioral or structural
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descriptions written according to the Alliance VHDL subsets.
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<a href="tools.html#asimut">ASIMUT</a> may also be linked with C
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descriptions of behavioral
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components.
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It loads a stimuli file (<a href="tools.html#pat">PAT</a> file format) and then
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run the simulation. The result is dumped in a new pattern file
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and it can be displayed using <a href="tools.html#xpat">XPAT</a>.
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<br></li>
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<li><a href="tools.html#xpat">XPAT</a> is a graphical pattern
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viewer. It loads a pattern file
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(<a href="tools.html#pat">PAT</a> file format)
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and displays waveforms on a graphical window.
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<br></li>
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</ul>
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</li>
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<br><li>Digital simulation of FSM descriptions:
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<a id="syf" name="syf"></a>
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<br><br><img src=beh-spec-syf.gif><br><br>
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<ul>
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<li><a href="tools.html#syf">SYF</a> loads the graph of a Finite
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State Machine. This FSM is
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described in VHDL using predefined templates. It encodes each
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states of the FSM and tries to minimize the resulting
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combinatorial logic.
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Finally it drives a new description using the Alliance VHDL
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dataflow subset (<a href="tools.html#vbe">VBE</a> file format).
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<br></li>
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</ul>
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</li>
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<br><li>Digital simulation of VHDL descriptions using Synospys VHDL subset:
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<a id="vasy" name="vasy"></a>
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<br><br><img src=beh-spec-vasy.gif><br><br>
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<ul>
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<li><a href="tools.html#vasy">VASY</a> can be seen as a VHDL
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translator. It loads VHDL
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behavioral or structural descriptions (written according to the
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Synopsys <a href="tools.html#vhd">VHDL</a> subset).
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It then drives one or more VHDL descriptions using the Alliance
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VHDL dataflow or structural
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subsets. <br> Those Alliance VHDL subsets are small and very
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particular.
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They are called <a href="tools.html#vbe">VBE</a> (VHDL
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BEhavioral) and <a href="tools.html#vst">VST</a> (VHDL
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STructural) file format.
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<br></li>
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</ul>
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</li>
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<br><li>Model checking of behavioral descriptions:
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<a id="mocha" name="mocha"></a>
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<br><br><img src=beh-spec-mocha.gif><br><br>
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<ul>
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<li><a href="tools.html#mocha">MOCHA</a> loads the graph of a
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Finite State Machine
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description. This FSM is described in VHDL using predefined
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templates. Then it loads a list of CTL formulae (described in
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CTL file format) and check formally if the given FSM verify CTL
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properties. <a href="tools.html#mocha">MOCHA</a> can also be
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used on a behavioral description
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using the Alliance VHDL dataflow subset (<a href="tools.html#vbe">VBE</a>).
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<br></li>
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</ul>
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</li>
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<br><li><b>Summary of digital behavioral specification step</b></li>
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<br><br><img src=beh-spec-alliance.gif>
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</ul>
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<!--
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-->
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<h1>Overview of the RTL synthesis step</h1>
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<ul>
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<li>This step consist on a transformation of a behavioral description
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to an optimized netlist of gates (standard cells, macros-cells, datapaths etc ...).
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</li>
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<br>
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<li>The designer can give optimization parameters and constraints to
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be satisfied such as:
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</li>
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<ul>
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<li>delay, arrival/required time
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</li>
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<li>surface
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</li>
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<li>power consumption
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</li>
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<li>etc ...
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</li>
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</ul>
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<br>
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<li>The RTL synthesis step has to be validate. The designer can use
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different methods such as:
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<ul>
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<li>Post synthesis digital simulation
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</li>
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<li>Formal proof
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</li>
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</ul>
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</ul>
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<!--
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-->
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<h1>The RTL synthesis step using the Alliance CAD system</h1>
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<ul>
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<li>Logic synthesis and standard cell mapping
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<a id="boom" name="boom"></a>
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<a id="boog" name="boog"></a>
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<a id="loon" name="loon"></a>
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<a id="proof" name="proof"></a>
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<br><br><img src=rtl-synth-logic.gif><br><br>
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<ul>
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<li><a href="tools.html#boom">BOOM</a> is used for the first
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step of the synthesis process.
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It loads a behavioural description
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(<a href="tools.html#vbe">VBE</a>), if possible a parameter
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file, and it builds an equivalent boolean network.
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From one hand it minimizes the boolean expression
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of each nodes of the network, and on the other hand it factorizes
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equivalent nodes. The result is an equivalent boolean network where
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the maximum depth is smaller and where boolean nodes have been factorized.
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<br></li>
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<li><a href="tools.html#asimut">ASIMUT</a> is the Alliance's VHDL simulator.
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<br></li>
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<li><a href="tools.html#proof">PROOF</a> is an equivalence
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checker. It loads two behavioural descriptions
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(<a href="tools.html#vbe">VBE</a>) and check their equivalence using formal technics.
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<br></li>
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<li><a href="tools.html#boog">BOOG</a> is used for the second
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step of the synthesis process.
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It loads a behavioural description
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(<a href="tools.html#vbe">VBE</a>) beforehand optimized
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with <a href="tools.html#boom">BOOM</a>
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and builds an equivalent boolean network. It loads also a library of standard
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cells and in option a parameter file.
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For each boolean function of each node of the network,
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it tries to find in the given library, a cell or a set of cells that produce
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the same boolean function. This step is often called standard cell mapping.
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The result is a netlist of cells with an equivalent behavior.
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<br></li>
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<li><a href="tools.html#loon">LOON</a> is used for the last
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step of the synthesis process.
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It loads a netlist of gates described in VHDL (<a href="tools.html#vst">VST</a>).
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It loads also a library of standard cells and in option a parameter file.
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<a href="tools.html#loon">LOON</a> computes the critical path
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and performs a gate repowering to
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decrease its delay and global capacitance.
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The result is an optimized netlist described in VHDL
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(<a href="tools.html#vst">VST</a>).
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<br></li>
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</ul>
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</li>
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<br>
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<li>Handmake synthesis
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<a id="genlib" name="genlib"></a>
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<a id="xsch" name="xsch"></a>
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<br><br><img src=rtl-synth-genlib.gif><br><br>
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<ul>
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<li><a href="tools.html#genlib">GENLIB</a> provides a C
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interface of a set of functions usefull to create
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a netlist of cells or a physical layout. For example given a cell library,
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a simple C function call is enough to create an instance of a cell.
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The result is a netlist (or a physical layout) built during the sequential
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execution of the C source code.
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<br></li>
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<li><a href="tools.html#xsch">XSCH</a> is the graphical
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schematic viewer of Alliance. It loads a netlist
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(<a href="tools.html#vst">VST</a> file
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format) and displays it on a graphical window.
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<br></li>
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<li><a href="tools.html#asimut">ASIMUT</a> is the Alliance's VHDL simulator.
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<br></li>
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</ul>
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</li>
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<br>
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<li>Data-path synthesis
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<br><br><img src=rtl-synth-dp.gif><br><br>
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<ul>
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<li><a href="tools.html#genlib">GENLIB</a> provides also a C
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interface for several macro-cells generators such
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as rom generator/register file generator etc ...
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The layout and the netlist of a complex data-path can be easily
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generated with only simple calls to predefined C functions.
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<br></li>
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<li><a href="tools.html#asimut">ASIMUT</a> is the Alliance's VHDL simulator.
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<br></li>
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</ul>
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</li>
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<br>
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<li>FSM synthesis and state graph minimisation:
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<a id="fmi" name="fmi"></a>
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<a id="fsp" name="fsp"></a>
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<br><br><img src=rtl-synth-fmi.gif><br><br>
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<ul>
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<li><a href="tools.html#fmi">FMI</a> loads the graph of a Finite
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State Machine (<a href="tools.html#fsm">FSM</a> file format).
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In the given FSM, <a href="tools.html#fmi">FMI</a> finds all
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equivalent states and merges them all
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together. The result is a new FSM, that still equivalent, but with a
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reduced number of states.
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Finally it drives this new description using <a href="tools.html#fsm">FSM</a>
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file format.
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<br></li>
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<li><a href="tools.html#fsp">FSP</a> is an FSM equivalence
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checker. It loads the graph of two FSMs and checks formally
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(using a FSM product based algorithm) if they have exactly the
|
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same behavior.
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<br></li>
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<li><a href="tools.html#syf">SYF</a> is a Finite State Machine synthesizer.
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<br></li>
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<li><a href="tools.html#b2f">B2F</a> is a Finite State Machine
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abstractor.
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It loads a RTL VHDL description (<a href="tools.html#vbe">VBE</a> file format).
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It then build the graph of an equivalent Finite State Machine, using a symbolic
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simulation algorithm. This tool does the inverse operation of the FSM synthesizer
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<a href="tools.html#syf">SYF</a>
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<br></li>
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</ul>
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</li>
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</ul>
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<!--
|
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-->
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<h1>Overview of the Place & Route step</h1>
|
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<ul>
|
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|
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<li>This step consist on a transformation of a netlist description
|
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to a physical layout.
|
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</li>
|
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<br>
|
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|
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<li>The designer can give some parameters and constraints to
|
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be satisfied such as:
|
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</li>
|
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<ul>
|
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<li>an initial placement of the cells
|
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</li>
|
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<li>a position for each physical connectors
|
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</li>
|
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<li>a form factor
|
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</li>
|
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<li>number of metal layers to be used
|
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</li>
|
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<li>etc ...
|
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</li>
|
||||
</ul>
|
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<br>
|
||||
|
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<li>The place and route step has to be validated. The designer has to use
|
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different methods such as:
|
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<ul>
|
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<li>Netlist exctration and netlist comparison
|
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</li>
|
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<li>Design rule checking
|
||||
</li>
|
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<li>Functionnal abstraction
|
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</li>
|
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</ul>
|
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</ul>
|
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|
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<!--
|
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-->
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<h1>The place and route step using the Alliance CAD system</h1>
|
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|
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<ul>
|
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<li>Overcell place and route
|
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|
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<a id="ocp" name="ocp"></a>
|
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<a id="nero" name="nero"></a>
|
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|
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<br><br><img src=place-route-ocpr.gif><br><br>
|
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|
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<ul>
|
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<li><a href="tools.html#ocp">OCP</a> is a placement tool. It
|
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loads a netlist of standard cells.
|
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The designer can specifies eventually connectors placement by given
|
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a parameter file (IOC file format).
|
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If there are non standard cell blocks in the netlist, the designer
|
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has to give a placement for those blocks.
|
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<a href="tools.html#ocp">OCP</a> then uses a simulated
|
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annealing algorithm to find a placement
|
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of all the netlist's cells, that minimized the length of nets.
|
||||
The result is a physical symbolic layout file with physical connectors
|
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and placed cells (<a href="tools.html#ap">AP</a> file format).
|
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<br></li>
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|
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<li><a href="tools.html#nero">NERO</a>(previously OCR) is the overcell
|
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router of Alliance. It loads a netlist and a
|
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physical placement file. The designer can give other parameters such
|
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as the number of metal layer he would like to use.
|
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The result is a physical symbolic layout view where each net
|
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of the netlist has been routed (<a href="tools.html#ap">AP</a> file format).
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<br></li>
|
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|
||||
</ul>
|
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</li>
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<br>
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|
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|
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<li>Pad ring place and route
|
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<a id="ring" name="ring"></a>
|
||||
|
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<br><br><img src=place-route-ring.gif><br><br>
|
||||
|
||||
<ul>
|
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<li><a href="tools.html#ring">RING</a> loads a netlist of pads
|
||||
interconnected with a "core" block.
|
||||
The designer can give a relative placement for those pads (RIN file format).
|
||||
After loading the physical view of the pads and the core, <a
|
||||
href="tools.html#ring">RING</a>
|
||||
place and route them all together, with a special treatment for
|
||||
the power supply nets.
|
||||
The result is a physical symbolic layout
|
||||
(<a href="tools.html#ap">AP</a> file format).
|
||||
<br></li>
|
||||
</ul>
|
||||
</li>
|
||||
<br>
|
||||
|
||||
<li>Place and route validation
|
||||
|
||||
<a id="lynx" name="lynx"></a>
|
||||
<a id="cougar" name="cougar"></a>
|
||||
<a id="lvx" name="lvx"></a>
|
||||
<a id="druc" name="druc"></a>
|
||||
<a id="graal" name="graal"></a>
|
||||
|
||||
<br><br><img src=place-route-valid.gif><br><br>
|
||||
|
||||
<ul>
|
||||
<li><a href="tools.html#cougar">LYNX</a> (called now COUGAR) is a
|
||||
hierarchical netlist extractor.
|
||||
It loads a symbolic or real physical view and given a technological
|
||||
file (RDS file format) it extracts a netlist
|
||||
(<a href="tools.html#al">AL</a> file format).
|
||||
<br></li>
|
||||
|
||||
<li><a href="tools.html#lvx">LVX</a> is simple a netlist comparator.
|
||||
<br></li>
|
||||
|
||||
<li><a href="tools.html#druc">DRUC</a> is a hierarchical design rule checker.
|
||||
It loads a symbolic physical view and given a technological
|
||||
file (RDS file format) it verifies design rules.
|
||||
<br></li>
|
||||
|
||||
<li><a href="tools.html#asimut">ASIMUT</a> is the Alliance's VHDL simulator.
|
||||
<br></li>
|
||||
|
||||
<li><a href="tools.html#graal">GRAAL</a> is a hierarchical symbolic layout editor.
|
||||
<br></li>
|
||||
|
||||
</ul>
|
||||
</li>
|
||||
<br>
|
||||
|
||||
<li>Symbolic layout to real layout
|
||||
|
||||
<a id="s2r" name="s2r"></a>
|
||||
<a id="dreal" name="dreal"></a>
|
||||
|
||||
<br><br><img src=place-route-s2r.gif><br><br>
|
||||
|
||||
<ul>
|
||||
<li>Given a technological file, <a href="tools.html#s2r">S2R</a> transforms
|
||||
a symbolic layout (lambda) to a real equivalent layout (micron).
|
||||
<br></li>
|
||||
|
||||
<li><a href="tools.html#dreal">DREAL</a> is the real layout editor of Alliance.
|
||||
<br></li>
|
||||
|
||||
<li><a href="tools.html#cougar">LYNX</a> is the netlist extractor of Alliance.
|
||||
<br></li>
|
||||
</ul>
|
||||
</li>
|
||||
<br>
|
||||
</ul>
|
||||
|
||||
|
||||
</body>
|
||||
|
|
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|
|||
<html>
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
|
||||
<title>Futur works in Alliance</title>
|
||||
</head>
|
||||
|
||||
<body bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#000080" alink="#FF0000">
|
||||
|
||||
<img src="logo.gif">
|
||||
|
||||
|
||||
<br>
|
||||
<br>
|
||||
<br>
|
||||
<h1>TO BE DONE</h1>
|
||||
<ul>
|
||||
<li>To be done
|
||||
</li>
|
||||
|
||||
<li>To be done
|
||||
</li>
|
||||
</ul>
|
||||
<br>
|
||||
|
||||
|
||||
</body>
|
||||
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|
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|
|
@ -0,0 +1,18 @@
|
|||
<html>
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
|
||||
<title>Alliance</title>
|
||||
<!-- Author: Ludovic Jacomme May 2004 -->
|
||||
</head>
|
||||
|
||||
<body bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#000080" alink="#FF0000">
|
||||
|
||||
<img src="logo.gif">
|
||||
|
||||
<ul>
|
||||
<li><a href="intro.html">What is Alliance ?</a></li>
|
||||
<li><a href="flow.html">Digital design flow</a></li>
|
||||
<li><a href="tools.html">Tools overview</a></li>
|
||||
</ul>
|
||||
|
||||
</body>
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
<html>
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
|
||||
<title>What is Alliance ?</title>
|
||||
</head>
|
||||
|
||||
<body bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#000080" alink="#FF0000">
|
||||
|
||||
<img src="logo.gif">
|
||||
|
||||
|
||||
<br>
|
||||
<br>
|
||||
<br>
|
||||
<h1>Alliance provides a software environement for the development of CAD tools:</h1>
|
||||
<ul>
|
||||
<li>More than 60 librairies written in C langage.
|
||||
Those libraries contain the definition of several data structures and methods
|
||||
allowing to describe circuits from the RTL view up to the physical view.
|
||||
Thoses data structures covered all the design flow and can be used
|
||||
by developpers to implement CAD applications.
|
||||
Those libraries contain also parsers and drivers for several standard file
|
||||
format.</li>
|
||||
|
||||
<li>More than 650 man pages describing the programming interface of
|
||||
those librairies</li>
|
||||
</ul>
|
||||
<br>
|
||||
|
||||
<h1>Alliance provides CAD tools covering most of all the digital design flow:</h1>
|
||||
<ul>
|
||||
<li>VHDL Compilation and Simulation</li>
|
||||
<li>Model checking and formal proof</li>
|
||||
<li>RTL and Logic synthesis</li>
|
||||
<li>Data-Path compilation</li>
|
||||
<li>Macro-cells generation</li>
|
||||
<li>Place and route</li>
|
||||
<li>Layout edition</li>
|
||||
<li>Netlist extraction and verification</li>
|
||||
<li>Design rules checking</li>
|
||||
<li>etc ...</li>
|
||||
</ul>
|
||||
<br>
|
||||
|
||||
<center><a href="mips.html"><img src=mips-small.jpg></a>
|
||||
<br>
|
||||
This is a MIPS-R3000 of 52000 transistors, that has been completely designed
|
||||
using Alliance CAD tools
|
||||
</center>
|
||||
<br>
|
||||
|
||||
<h1>Alliance provides also a complete set of portable CMOS libraries:</h1>
|
||||
<ul>
|
||||
<li>standard cells</li>
|
||||
<li>specific cells used by the generators (RAM/ROM/etc ...)</li>
|
||||
<li>symbolic pad cells</li>
|
||||
</ul>
|
||||
|
||||
<br>
|
||||
<br>
|
||||
|
||||
|
||||
<center>
|
||||
<em>The Alliance CAD system is used in more than 80 Universities all arround the world
|
||||
for teaching and research purposes.
|
||||
</em>
|
||||
<br>
|
||||
<em>Alliance is the result of a twelve year effort spent at ASIM department of LIP6
|
||||
laboratory of the Pierre et Marie Curie University
|
||||
</em>
|
||||
</center>
|
||||
|
||||
</body>
|
||||
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|
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|
|
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|
|||
<html>
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
|
||||
<title>What is Alliance ?</title>
|
||||
</head>
|
||||
|
||||
<body bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#000080" alink="#FF0000">
|
||||
|
||||
<img src="logo.gif">
|
||||
<br>
|
||||
<br>
|
||||
|
||||
<center><a href="intro.html"><img src=mips.jpg></a>
|
||||
|
||||
|
||||
</body>
|
||||
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Reference in New Issue