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modif sur TRISTATE input -> TRISTATE output

This commit is contained in:
Francois Donnet 2000-11-06 12:08:43 +00:00
parent 56dfb00de1
commit d1f845b89f
2 changed files with 5 additions and 5 deletions
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6
alliance/share/man/man3/GENLIB_BUS.3
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@ -1,4 +1,4 @@
.\" $Id: GENLIB_BUS.3,v 1.2 2000/09/28 15:25:48 fred Exp $
.\" $Id: GENLIB_BUS.3,v 1.3 2000/11/06 12:08:42 francois Exp $
.\" @(#)GENLIB_BUS.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
.if t \{\
.so man1/alc_contents.mac
@ -33,7 +33,7 @@ Starting index of the set of signal, \fIfrom\fP included
\fIto\fP
Ending index of the set of signal, \fIto\fP included
.SH DESCRIPTION
\fIBUS\fP Creates a set of names, based upon a common name, valid for the
\fIGENLIB_BUS\fP Creates a set of names, based upon a common name, valid for the
genlib netlist
functions that manipulate the signal, and/or connector, concept.
They are:
@ -63,7 +63,7 @@ int e = 12;
/\(** Create a figure to work on \(**/
GENLIB_DEF_LOFIG("mycell");
/\(** define interface \(**/
GENLIB_LOCON(GENLIB_BUS("i", b, e), INPUT, BUS("sig", b, e);
GENLIB_LOCON(GENLIB_BUS("i", b, e), INPUT, GENLIB_BUS("sig", b, e);
GENLIB_LOCON("o[2:0]", OUTPUT, "sigout[4:6]");
/\(** Place an instance \(**/
GENLIB_LOINS("model","instance", GENLIB_BUS("sig", e/2), "sigout[6]", EOL);

4
alliance/share/man/man3/GENLIB_LOCON.3
View File

@ -1,4 +1,4 @@
.\" $Id: GENLIB_LOCON.3,v 1.2 2000/09/28 15:25:51 fred Exp $
.\" $Id: GENLIB_LOCON.3,v 1.3 2000/11/06 12:08:43 francois Exp $
.\" @(#)GENLIB_LOCON.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
.if t \{\
.so man1/alc_contents.mac
@ -50,7 +50,7 @@ as input/output, like supplies or clock for example.
if one doesn't know what it is.
.TP
\fBTRISTATE\fP
as high impedance input.
as high impedance output.
.TP
\fBTRANSV\fP
as transciever. That means \fBTRISTATE\fP input plus output.