mises a jour
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Franck Wajsburt
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.\" $Id: sxlib.5,v 1.4 1999/09/27 17:06:10 franck Exp $
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.\" $Id: sxlib.5,v 1.5 1999/09/28 07:21:23 franck Exp $
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.\" @(#)Labo.l 0.0 92/09/24 UPMC; Author: Franck Wajsburt
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.pl -.4
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.TH SXLIB 5 "September 16, 1999" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
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.SH NAME
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.B sxlib - a portable CMOS Standard Cell Library
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@ -10,15 +9,28 @@
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\fBsxlib\fP library contains standard cells that have been developed at
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UPMC-ASIM/LIP6. This manual gives the list of available cells, with their
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behavior, width, maximum delay and input fan-in.
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behavior, width, maximum delay and input fan-in. This manual gives also
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few thumb rules to help the user to well use the cells. The given delais
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are the maximum (that means worst case for a generic .35 micron process).
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More precise delais can be found in ALLIANCE VHDL behavior files (.vbe file).
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Cell-name is built that way <behavior>_<output drive>
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(see explanations below).
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.nf
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Three files are attached to each cell:-
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- Layout cell-name.ap
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- Transistor net-list cell-name.al
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- VHDL behavior cell-name.vbe
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Four files are attached to each cell:-
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- ALLIANCE Layout ............... cell-name.ap
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- ALLIANCE Transistor net-list .. cell-name.al
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- ALLIANCE VHDL behavior ........ cell-name.vbe
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- Compiled HILO behavior ........ 0000000xx.dat
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And few files more:-
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- CATAL ......................... ALLIANCE catalog file
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- sxlib.cct ..................... Cell definition for HILO CAD tools
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- CIRCUIT.idx ................... HILO catalog file
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- sxlib.lib ..................... Cell definition for Synopsys CAD tools
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- sxlib.db ...................... Compiled cell definition for Synopsys
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- sxlib.sdb ..................... Icon definition for Synopys
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Cell-name is built that way <behavior>_<output drive>.
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.fi
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.SH PHYSICAL OUTLINE
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@ -29,6 +41,7 @@ mapping to a specific process CIF or GDS2 layout must be performed by the
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\fBs2r\fP tool (symbolic to real), which uses a value for the lambda
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(e.g. 1 lambda=0.3um).
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.nf
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_________________
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50 | VDD |
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45 |_________________| x : place of virtual connector.
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@ -124,6 +137,9 @@ the VHDL interface component is always the alphabetic order.
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[\fBn\fP][\fBsd\fP]\fBff\fP<i> : [\fBn\fPot] [\fBs\fPtatic|\fBd\fPynamic] \fBf\fPlip-\fBf\fPlop <i> inputs
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[\fBn\fP]\fBoa\fP... : [\fBn\fPot] \fBa\fPnd/\fBo\fPr function (see below)
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\fBand_or cell (lex grammar):-\fP
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NAME : \fBn\fP OA_CELL -> not OA_CELL
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@ -161,18 +177,21 @@ The delay is in nano-seconds. Remember this delay corresponds to the slower
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input+0.6ns. The behavior gives logic function. / means not, + means or, .
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means and, ^ means xor. Each input is followed by fan-in capacitance in fF,
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(e.g. i0<11> means i0 pin capacitance is 11fF).
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.nf
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\fB=================================================================\fP
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\fBWIDTH NAME DELAY BEHAVIOR\fP
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\fB---------------------------------------------------------- BUFFER\fP
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\fB-------------------------------------------------------- INVERSOR\fP
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3 inv_x1 .7 nq <= /i<8>
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3 inv_x2 .7 nq <= /i<12>
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4 inv_x4 .7 nq <= /i<26>
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7 inv_x8 .7 nq <= /i<54>
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\fB---------------------------------------------------------- BUFFER\fP
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4 buf_x2 1.0 q <= i<6>
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5 buf_x4 1.0 q <= i<9>
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8 buf_x8 1.0 q <= i<15>
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\fB------------------------------------------------------ THREE STATE\fP
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6 nts_x1 .8 IF (cmd<14>) nq <= /i<14>
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8 nts_x2 .9 IF (cmd<18>) nq <= /i<28>
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@ -204,11 +223,6 @@ means and, ^ means xor. Each input is followed by fan-in capacitance in fF,
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10 o3_x4 1.2 q <= (i0<10>+i1<10>+i2<9>)
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7 o4_x2 1.2 q <= (i0<10>+i1<10>+i2<10>+i3<9>)
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8 o4_x4 1.3 q <= (i0<12>+i1<12>+i2<12>+i3<12>)
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\fB-------------------------------------------------------------- XOR\fP
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9 nxr2_x1 1.1 nq <= /(i0<21>^i1<22>)
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11 nxr2_x4 1.2 nq <= /(i0<20>^i1<21>)
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9 xr2_x1 1.0 q <= (i0<21>^i1<22>)
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12 xr2_x4 1.2 q <= (i0<20>^i1<21>)
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\fB--------------------------------------------------------- AND/OR 3\fP
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6 nao22_x1 .9 nq <= /((i0<14>+i1<14>).i2<14>)
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10 nao22_x4 1.3 nq <= /((i0<8>+i1<8>).i2<9>)
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@ -227,11 +241,19 @@ means and, ^ means xor. Each input is followed by fan-in capacitance in fF,
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10 ao2o22_x4 1.3 nq <= ((i0<8>+i1<8>).(i2<8>+i3<8>))
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9 oa2a22_x1 1.2 nq <= ((i0<8>.i1<8>)+(i2<8>.i3<8>))
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10 oa2a22_x4 1.4 nq <= ((i0<8>.i1<8>)+(i2<8>.i3<8>))
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\fB------------------------------------------------------ MULTIPLEXER\fP
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7 nmx2_x1 1.0 nq <= /((i0<14>./cmd<21>)+(i1<14>.cmd))
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12 nmx2_x4 1.3 nq <= /((i0<8>./cmd<14>)+(i1<9>.cmd))
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9 mx2_x2 1.1 q <= (i0<8>./cmd<17>)+(i1<9>.cmd)
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10 mx2_x4 1.3 q <= (i0<8>./cmd<17>)+(i1<9>.cmd)
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\fB-------------------------------------------------------------- XOR\fP
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9 nxr2_x1 1.1 nq <= /(i0<21>^i1<22>)
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11 nxr2_x4 1.2 nq <= /(i0<20>^i1<21>)
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9 xr2_x1 1.0 q <= (i0<21>^i1<22>)
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12 xr2_x4 1.2 q <= (i0<20>^i1<21>)
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\fB-------------------------------------------------------- FLIP-FLOP\fP
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."25 nsdff2_x4 1.0 IF RISE(ck<23>) nq <=/((i0<11>./cmd<13>)+(i1<7>.cmd))
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18 sff1_x4 1.7 IF RISE(ck<8>) q <= i<8>
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@ -244,11 +266,6 @@ means and, ^ means xor. Each input is followed by fan-in capacitance in fF,
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\fB==================================================================\fP
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.fi
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.SH SEE ALSO
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\fB MBK_CATA_LIB (1), catal(1), scr(1), lynx(1), bop(1), glop(1), scmap(1),
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c4map(1), tas(1), yagle(1), genlib(1), ap(1), al(1), vbe(1)\fP
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.SH NEW CELLS
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It is possible to add new cells in the library just by providing the 3
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@ -294,4 +311,10 @@ PORT (
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vss : in BIT
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);
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.fi
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.SH SEE ALSO
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\fBMBK_CATA_LIB (1), catal(1), scr(1), lynx(1), bop(1), glop(1), scmap(1),
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c4map(1), tas(1), yagle(1), genlib(1), ap(1), al(1), vbe(1)\fP
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.so man1/alc_bug_report.1
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