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Franck Wajsburt 1999-09-27 17:06:10 +00:00
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@ -1,4 +1,4 @@
.\" $Id: sxlib.5,v 1.3 1999/09/27 14:16:40 franck Exp $
.\" $Id: sxlib.5,v 1.4 1999/09/27 17:06:10 franck Exp $
.\" @(#)Labo.l 0.0 92/09/24 UPMC; Author: Franck Wajsburt
.pl -.4
.TH SXLIB 5 "September 16, 1999" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
@ -101,7 +101,8 @@ not very good to under-load a cell because this leads to a signal overshoot.
With the 0.35um process, a \fB1\fP lambda interconnect wire is about
\fB0.15fF\fP, an average cell fan-in is 10fF. Then, if it needs about 50
lambdas to connect 2 cells, an \fBx1\fP cell is able to drive about 7
cells. With 100 lambdas, 5 cells, with 750 lambdas only 2 cells.
cells (125/(10+50*.15)=7). With 100 lambdas, 5 cells, with 750 lambdas
only 2 cells.
All this are indications. Only a timing analysis on the extracted
transistor net-list from layout can tell if a cell is well used or not