Les cellules pour HILO et synopsys

alliance/share/cells/sxlib/CIRCUIT.IDX

@@ -0,0 +1,68 @@
+SystemHILO
+xTSWTF040HMODA2ZV
+66
+3 A2_X2 2
+3 A2_X4 3
+3 A3_X2 4
+3 A3_X4 5
+3 A4_X2 6
+3 A4_X4 7
+3 AO22_X2 8
+3 AO22_X4 9
+3 AO2O22_X2 10
+3 AO2O22_X4 11
+3 BUF_X2 12
+3 BUF_X4 13
+3 BUF_X8 14
+3 INV_X1 15
+3 INV_X2 16
+3 INV_X4 17
+3 INV_X8 18
+3 MX2_X2 19
+3 MX2_X4 20
+3 NA2_X1 21
+3 NA2_X4 22
+3 NA3_X1 23
+3 NA3_X4 24
+3 NA4_X1 25
+3 NA4_X4 26
+3 NAO22_X1 27
+3 NAO22_X4 28
+3 NAO2O22_X1 29
+3 NAO2O22_X4 30
+3 NMX2_X1 31
+3 NMX2_X4 32
+3 NO2_X1 33
+3 NO2_X4 34
+3 NO3_X1 35
+3 NO3_X4 36
+3 NO4_X1 37
+3 NO4_X4 38
+3 NOA22_X1 39
+3 NOA22_X4 40
+3 NOA2A22_X1 41
+3 NOA2A22_X4 42
+3 NTS_X1 43
+3 NTS_X2 44
+3 NXR2_X1 45
+3 NXR2_X4 46
+3 O2_X2 47
+3 O2_X4 48
+3 O3_X2 49
+3 O3_X4 50
+3 O4_X2 51
+3 O4_X4 52
+3 OA22_X2 53
+3 OA22_X4 54
+3 OA2A22_X2 55
+3 OA2A22_X4 56
+3 ONE_X0 57
+3 ROWEND_X0 58
+3 SFF1_X4 59
+3 SFF2_X4 60
+3 TIE_X0 61
+3 TS_X4 62
+3 TS_X8 63
+3 XR2_X1 64
+3 XR2_X4 65
+3 ZERO_X0 66

alliance/share/cells/sxlib/sxlib.cct

@@ -0,0 +1,638 @@
+Circuit a2_x2 (
+ Input    i0 ,
+ Input    i1 ,
+ Output   q ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE q := (i0 and i1) ;
+EndCircuit
+Circuit a2_x4 (
+ Input    i0 ,
+ Input    i1 ,
+ Output   q ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE q := (i0 and i1) ;
+EndCircuit
+Circuit a3_x2 (
+ Input    i0 ,
+ Input    i1 ,
+ Input    i2 ,
+ Output   q ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE q := ((i0 and i1) and i2) ;
+EndCircuit
+Circuit a3_x4 (
+ Input    i0 ,
+ Input    i1 ,
+ Input    i2 ,
+ Output   q ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE q := ((i0 and i1) and i2) ;
+EndCircuit
+Circuit a4_x2 (
+ Input    i0 ,
+ Input    i1 ,
+ Input    i2 ,
+ Input    i3 ,
+ Output   q ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE q := (((i0 and i1) and i2) and i3) ;
+EndCircuit
+Circuit a4_x4 (
+ Input    i0 ,
+ Input    i1 ,
+ Input    i2 ,
+ Input    i3 ,
+ Output   q ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE q := (((i0 and i1) and i2) and i3) ;
+EndCircuit
+Circuit ao22_x2 (
+ Input    i0 ,
+ Input    i1 ,
+ Input    i2 ,
+ Output   q ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE q := ((i0 or i1) and i2) ;
+EndCircuit
+Circuit ao22_x4 (
+ Input    i0 ,
+ Input    i1 ,
+ Input    i2 ,
+ Output   q ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE q := ((i0 or i1) and i2) ;
+EndCircuit
+Circuit ao2o22_x2 (
+ Input    i0 ,
+ Input    i1 ,
+ Input    i2 ,
+ Input    i3 ,
+ Output   q ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE q := ((i0 or i1) and (i2 or i3)) ;
+EndCircuit
+Circuit ao2o22_x4 (
+ Input    i0 ,
+ Input    i1 ,
+ Input    i2 ,
+ Input    i3 ,
+ Output   q ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE q := ((i0 or i1) and (i2 or i3)) ;
+EndCircuit
+Circuit buf_x2 (
+ Input    i ,
+ Output   q ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE q := i ;
+EndCircuit
+Circuit buf_x4 (
+ Input    i ,
+ Output   q ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE q := i ;
+EndCircuit
+Circuit buf_x8 (
+ Input    i ,
+ Output   q ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE q := i ;
+EndCircuit
+Circuit inv_x1 (
+ Input    i ,
+ Output   nq ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE nq := not i ;
+EndCircuit
+Circuit inv_x2 (
+ Input    i ,
+ Output   nq ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE nq := not i ;
+EndCircuit
+Circuit inv_x4 (
+ Input    i ,
+ Output   nq ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE nq := not i ;
+EndCircuit
+Circuit inv_x8 (
+ Input    i ,
+ Output   nq ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE nq := not i ;
+EndCircuit
+Circuit mx2_x2 (
+ Input    cmd ,
+ Input    i0 ,
+ Input    i1 ,
+ Output   q ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE q := ((i1 and cmd) or (not cmd and i0)) ;
+EndCircuit
+Circuit mx2_x4 (
+ Input    cmd ,
+ Input    i0 ,
+ Input    i1 ,
+ Output   q ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE q := ((i1 and cmd) or (not cmd and i0)) ;
+EndCircuit
+Circuit na2_x1 (
+ Input    i0 ,
+ Input    i1 ,
+ Output   nq ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE nq := not (i0 and i1) ;
+EndCircuit
+Circuit na2_x4 (
+ Input    i0 ,
+ Input    i1 ,
+ Output   nq ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE nq := not (i0 and i1) ;
+EndCircuit
+Circuit na3_x1 (
+ Input    i0 ,
+ Input    i1 ,
+ Input    i2 ,
+ Output   nq ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE nq := not ((i0 and i1) and i2) ;
+EndCircuit
+Circuit na3_x4 (
+ Input    i0 ,
+ Input    i1 ,
+ Input    i2 ,
+ Output   nq ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE nq := not ((i0 and i1) and i2) ;
+EndCircuit
+Circuit na4_x1 (
+ Input    i0 ,
+ Input    i1 ,
+ Input    i2 ,
+ Input    i3 ,
+ Output   nq ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE nq := not (((i0 and i1) and i2) and i3) ;
+EndCircuit
+Circuit na4_x4 (
+ Input    i0 ,
+ Input    i1 ,
+ Input    i2 ,
+ Input    i3 ,
+ Output   nq ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE nq := not (((i0 and i1) and i2) and i3) ;
+EndCircuit
+Circuit nao22_x1 (
+ Input    i0 ,
+ Input    i1 ,
+ Input    i2 ,
+ Output   nq ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE nq := not ((i0 or i1) and i2) ;
+EndCircuit
+Circuit nao22_x4 (
+ Input    i0 ,
+ Input    i1 ,
+ Input    i2 ,
+ Output   nq ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE nq := not ((i0 or i1) and i2) ;
+EndCircuit
+Circuit nao2o22_x1 (
+ Input    i0 ,
+ Input    i1 ,
+ Input    i2 ,
+ Input    i3 ,
+ Output   nq ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE nq := not ((i0 or i1) and (i2 or i3)) ;
+EndCircuit
+Circuit nao2o22_x4 (
+ Input    i0 ,
+ Input    i1 ,
+ Input    i2 ,
+ Input    i3 ,
+ Output   nq ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE nq := not ((i0 or i1) and (i2 or i3)) ;
+EndCircuit
+Circuit nmx2_x1 (
+ Input    cmd ,
+ Input    i0 ,
+ Input    i1 ,
+ Output   nq ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE nq := not ((i0 and not cmd) or (i1 and cmd)) ;
+EndCircuit
+Circuit nmx2_x4 (
+ Input    cmd ,
+ Input    i0 ,
+ Input    i1 ,
+ Output   nq ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE nq := not ((i0 and not cmd) or (i1 and cmd)) ;
+EndCircuit
+Circuit no2_x1 (
+ Input    i0 ,
+ Input    i1 ,
+ Output   nq ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE nq := not (i0 or i1) ;
+EndCircuit
+Circuit no2_x4 (
+ Input    i0 ,
+ Input    i1 ,
+ Output   nq ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE nq := not (i0 or i1) ;
+EndCircuit
+Circuit no3_x1 (
+ Input    i0 ,
+ Input    i1 ,
+ Input    i2 ,
+ Output   nq ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE nq := not ((i0 or i1) or i2) ;
+EndCircuit
+Circuit no3_x4 (
+ Input    i0 ,
+ Input    i1 ,
+ Input    i2 ,
+ Output   nq ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE nq := not ((i0 or i1) or i2) ;
+EndCircuit
+Circuit no4_x1 (
+ Input    i0 ,
+ Input    i1 ,
+ Input    i2 ,
+ Input    i3 ,
+ Output   nq ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE nq := not (((i0 or i1) or i2) or i3) ;
+EndCircuit
+Circuit no4_x4 (
+ Input    i0 ,
+ Input    i1 ,
+ Input    i2 ,
+ Input    i3 ,
+ Output   nq ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE nq := not (((i0 or i1) or i2) or i3) ;
+EndCircuit
+Circuit noa22_x1 (
+ Input    i0 ,
+ Input    i1 ,
+ Input    i2 ,
+ Output   nq ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE nq := not ((i0 and i1) or i2) ;
+EndCircuit
+Circuit noa22_x4 (
+ Input    i0 ,
+ Input    i1 ,
+ Input    i2 ,
+ Output   nq ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE nq := not ((i0 and i1) or i2) ;
+EndCircuit
+Circuit noa2a22_x1 (
+ Input    i0 ,
+ Input    i1 ,
+ Input    i2 ,
+ Input    i3 ,
+ Output   nq ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE nq := not ((i0 and i1) or (i2 and i3)) ;
+EndCircuit
+Circuit noa2a22_x4 (
+ Input    i0 ,
+ Input    i1 ,
+ Input    i2 ,
+ Input    i3 ,
+ Output   nq ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE nq := not ((i0 and i1) or (i2 and i3)) ;
+EndCircuit
+Circuit nts_x1 (
+ Input    cmd ,
+ Input    i ,
+ Output   nq ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE commande_0_nq := cmd ;
+WIRE data_0_nq := not i ;
+TRI1 nq ;
+	BUFIF1 tri_0_nq (nq,data_0_nq,commande_0_nq) ;
+EndCircuit
+Circuit nts_x2 (
+ Input    cmd ,
+ Input    i ,
+ Output   nq ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE commande_0_nq := cmd ;
+WIRE data_0_nq := not i ;
+TRI1 nq ;
+	BUFIF1 tri_0_nq (nq,data_0_nq,commande_0_nq) ;
+EndCircuit
+Circuit nxr2_x1 (
+ Input    i0 ,
+ Input    i1 ,
+ Output   nq ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE nq := not (i0 xor i1) ;
+EndCircuit
+Circuit nxr2_x4 (
+ Input    i0 ,
+ Input    i1 ,
+ Output   nq ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE nq := not (i0 xor i1) ;
+EndCircuit
+Circuit o2_x2 (
+ Input    i0 ,
+ Input    i1 ,
+ Output   q ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE q := (i0 or i1) ;
+EndCircuit
+Circuit o2_x4 (
+ Input    i0 ,
+ Input    i1 ,
+ Output   q ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE q := (i0 or i1) ;
+EndCircuit
+Circuit o3_x2 (
+ Input    i0 ,
+ Input    i1 ,
+ Input    i2 ,
+ Output   q ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE q := ((i0 or i1) or i2) ;
+EndCircuit
+Circuit o3_x4 (
+ Input    i0 ,
+ Input    i1 ,
+ Input    i2 ,
+ Output   q ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE q := ((i0 or i1) or i2) ;
+EndCircuit
+Circuit o4_x2 (
+ Input    i0 ,
+ Input    i1 ,
+ Input    i2 ,
+ Input    i3 ,
+ Output   q ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE q := (((i0 or i1) or i2) or i3) ;
+EndCircuit
+Circuit o4_x4 (
+ Input    i0 ,
+ Input    i1 ,
+ Input    i2 ,
+ Input    i3 ,
+ Output   q ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE q := (((i0 or i1) or i2) or i3) ;
+EndCircuit
+Circuit oa22_x2 (
+ Input    i0 ,
+ Input    i1 ,
+ Input    i2 ,
+ Output   q ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE q := ((i0 and i1) or i2) ;
+EndCircuit
+Circuit oa22_x4 (
+ Input    i0 ,
+ Input    i1 ,
+ Input    i2 ,
+ Output   q ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE q := ((i0 and i1) or i2) ;
+EndCircuit
+Circuit oa2a22_x2 (
+ Input    i0 ,
+ Input    i1 ,
+ Input    i2 ,
+ Input    i3 ,
+ Output   q ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE q := ((i0 and i1) or (i2 and i3)) ;
+EndCircuit
+Circuit oa2a22_x4 (
+ Input    i0 ,
+ Input    i1 ,
+ Input    i2 ,
+ Input    i3 ,
+ Output   q ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE q := ((i0 and i1) or (i2 and i3)) ;
+EndCircuit
+Circuit one_x0 (
+ Output   q ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE q := 1 ;
+EndCircuit
+Circuit rowend_x0 (
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+EndCircuit
+Circuit sff1_x4 (
+ Input    ck ,
+ Input    i ,
+ Output   q ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE sff_m_bcond_0 := ck ;
+REGISTER (1,1) sff_m ; 
+WHEN sff_m_bcond_0 (0 TO 1) DO sff_m := i ;
+WIRE q := sff_m ;
+EndCircuit
+Circuit sff2_x4 (
+ Input    ck ,
+ Input    cmd ,
+ Input    i0 ,
+ Input    i1 ,
+ Output   q ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE sff_m_bcond_0 := ck ;
+REGISTER (1,1) sff_m ; 
+WHEN sff_m_bcond_0 (0 TO 1) DO sff_m := ((i1 and cmd) or (i0 and not cmd)) ;
+WIRE q := sff_m ;
+EndCircuit
+Circuit tie_x0 (
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+EndCircuit
+Circuit ts_x4 (
+ Input    cmd ,
+ Input    i ,
+ Output   q ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE commande_0_q := cmd ;
+WIRE data_0_q := i ;
+TRI1 q ;
+	BUFIF1 tri_0_q (q,data_0_q,commande_0_q) ;
+EndCircuit
+Circuit ts_x8 (
+ Input    cmd ,
+ Input    i ,
+ Output   q ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE commande_0_q := cmd ;
+WIRE data_0_q := i ;
+TRI1 q ;
+	BUFIF1 tri_0_q (q,data_0_q,commande_0_q) ;
+EndCircuit
+Circuit xr2_x1 (
+ Input    i0 ,
+ Input    i1 ,
+ Output   q ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE q := (i0 xor i1) ;
+EndCircuit
+Circuit xr2_x4 (
+ Input    i0 ,
+ Input    i1 ,
+ Output   q ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE q := (i0 xor i1) ;
+EndCircuit
+Circuit zero_x0 (
+ Output   nq ,
+ Supply1  vdd ,
+ Supply0  vss 
+ );
+WIRE nq := 0 ;
+EndCircuit