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Francois Donnet 2000-08-25 10:37:37 +00:00
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alliance/share/man/man1/boog.1
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@ -59,6 +59,7 @@ The logic level behavioural description (.vbe file) uses the same VHDL subset as
Some constraints due to hardware mapping exist. These attributes are only supported by technology mapping onto a standard cell library as \f4sxlib\fP. Some constraints due to hardware mapping exist. These attributes are only supported by technology mapping onto a standard cell library as \f4sxlib\fP.
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For the register signal description, only one condition statement must appear. STABLE must be strictely used as a negativ motion and joined to clock setup value. Setup can be on high or low value, but it would be worthy to choose it accordingly with hardware register cell. For the register signal description, only one condition statement must appear. STABLE must be strictely used as a negativ motion and joined to clock setup value. Setup can be on high or low value, but it would be worthy to choose it accordingly with hardware register cell.
.br
\fI# Example\fP \fI# Example\fP
label: BLOCK (NOT ck 'STABLE and ck='1') label: BLOCK (NOT ck 'STABLE and ck='1')
BEGIN BEGIN