en caractere gras
This commit is contained in:
Francois Donnet
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@ -47,16 +47,16 @@ BooG \- Binding and Optimizing On Gates.
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.SH DESCRIPTION
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.br
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\fBBoog\fP is a mapper of a behavioural description onto a predefined standard cell library as SXLIB.
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\f4boog\fP is a mapper of a behavioural description onto a predefined standard cell library as SXLIB.
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It is the second step of the logic synthesis: it builds a gate network using a standard cell library.
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.br
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.br
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\fB Input file description\fP
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\f4 Input file description\fP
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.br
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The logic level behavioural description (.vbe file) uses the same VHDL subset as the logic simulator \fBasimut\fP, the FSM synthesizer \fBsyf\fP, the functional abstractor \fByagle\fP and the formal prover \fBproof\fP (for further information about the subset of VHDL, see the "vbe" manual).
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The logic level behavioural description (.vbe file) uses the same VHDL subset as the logic simulator \f4asimut\fP, the FSM synthesizer \f4syf\fP, the functional abstractor \f4yagle\fP and the formal prover \f4proof\fP (for further information about the subset of VHDL, see the "vbe" manual).
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.br
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Some constraints due to hardware mapping exist. These attributes are only supported by technology mapping onto a standard cell library as \fBsxlib\fP.
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Some constraints due to hardware mapping exist. These attributes are only supported by technology mapping onto a standard cell library as \f4sxlib\fP.
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.br
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For the register signal description, only one condition statement must appear. STABLE must be strictely used as a negativ motion and joined to clock setup value. Setup can be on high or low value, but it would be worthy to choose it accordingly with hardware register cell.
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\fI# Example\fP
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@ -74,26 +74,26 @@ You can also put a write enable condition to your register:
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.ti 7
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A special feature has been introduced in the VHDL subset in order to allow the don't care description for external outputs and internal registers : A bit signal can take the 'd' value.
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This value is interpreted as a '0' by the logic simulator \fBasimut\fP.
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Don't Cares are automatically generated by \fBsyf\fP in the resulting '.vbe' file.
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This value is interpreted as a '0' by the logic simulator \f4asimut\fP.
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Don't Cares are automatically generated by \f4syf\fP in the resulting '.vbe' file.
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.br
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\fB Output file description\fP
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\f4 Output file description\fP
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.br
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A pure standard cell netlist is produced by \fBboog\fP. This file is destinated for /fBloon/fP alliance utility to improve RC delays.
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A pure standard cell netlist is produced by \f4boog\fP. This file is destinated for /fBloon/fP alliance utility to improve RC delays.
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Any equipotential keeps its name from connector to connector. In trouble case, buffers are inserted to respect this VHDL constraint.
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.br
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\fB lax Parameter file description\fP
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\f4 lax Parameter file description\fP
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.br
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The lax file is common with other logic synthesis tools and is used
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for driving the synthesis process.
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See \fBlax\fP(5) manual for more detail.
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See \f4lax\fP(5) manual for more detail.
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.br
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\fBlax\fP uses a lot of parameters to guide every step of the synthesis process.
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Some parameters are globally used (for example, \fIoptimization level\fP whereas others are specifically used (\fBload capacitance\fP for the netlist optimization only).
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\f4lax\fP uses a lot of parameters to guide every step of the synthesis process.
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Some parameters are globally used (for example, \fIoptimization level\fP whereas others are specifically used (\f4load capacitance\fP for the netlist optimization only).
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Here is the default lax file (see the user's manual for further information about the syntax of the '.lax' file):
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.br
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@ -109,36 +109,36 @@ Here is the default lax file (see the user's manual for further information abou
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.br
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\fB Mapping with a standard cell library\fP
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\f4 Mapping with a standard cell library\fP
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.br
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Every cell appearing in the directory defined by the environment variable MBK_TARGET_LIB may be used by \fBboog\fP since they are described as a '.vbe' file. There are some restrictions about the type of the cell used. Every cell has to have only one output.
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The cell must be characterized. The timing and area informations required by \fBboog\fP are specified in the "generic" clause of the ".vbe" file.
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Every cell appearing in the directory defined by the environment variable MBK_TARGET_LIB may be used by \f4boog\fP since they are described as a '.vbe' file. There are some restrictions about the type of the cell used. Every cell has to have only one output.
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The cell must be characterized. The timing and area informations required by \f4boog\fP are specified in the "generic" clause of the ".vbe" file.
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.br
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.SH OPTION
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.TP 10
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\f4\-h\fP
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Help mode. Displays possible uses of \fBboog\fP.
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Help mode. Displays possible uses of \f4boog\fP.
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.TP 10
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\f4\-m optim_mode\fP
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Optimization mode. Can be defined in lax file, it's only a shortcut to define it on command line. This mode number has an array defined between \fI0\fP and \fI4\fP. It indicates the way of optimization the user wants. If \fI0\fP is chosen, the circuit area will be improved. On the other hand, \fI4\fP will improve circuit delays. \fI2\fP is a medium value for optimization.
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.TP 10
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\f4\-x xsch_mode\fP
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Generate a '.xsc' file. It is a color map for each signals contained in \fIoutput_file\fP network. This file is used by \fBxsch\fP to view the netlist. By choosing level 0 or 1 for xsch_mode, you can color respectively the critical path or all signals with delay graduation.
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Generate a '.xsc' file. It is a color map for each signals contained in \fIoutput_file\fP network. This file is used by \f4xsch\fP to view the netlist. By choosing level 0 or 1 for xsch_mode, you can color respectively the critical path or all signals with delay graduation.
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.TP 10
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\f4\-o output_file\fP
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Just another way to show explicitely the \fBVST\fP output file name.
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Just another way to show explicitely the \f4VST\fP output file name.
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.TP 10
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\f4\-l lax_file\fP
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Just another way to show explicitely the \fBLAX\fP parameter file name.
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Just another way to show explicitely the \f4LAX\fP parameter file name.
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.TP 10
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\f4\-d debug_file\fP
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Generates a \fBVBE\f debug file. It comes from internal result algorithm. Users aren't concerned.
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Generates a \f4VBE\f debug file. It comes from internal result algorithm. Users aren't concerned.
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.br
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.SH ENVIRONMENT VARIABLES
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.br
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The following environment variables have to be set before using \fBboog\fP :
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The following environment variables have to be set before using \f4boog\fP :
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.HP
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.ti 7
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\fIMBK_CATA_LIB\fP gives the auxiliary paths of the directories of input files (behavioural description).
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@ -152,7 +152,7 @@ The following environment variables have to be set before using \fBboog\fP :
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.SH EXAMPLE
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.br
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You can call \fBboog\fP as follows :
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You can call \f4boog\fP as follows :
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.br
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.br
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boog alu alu
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