une version avec un contenu
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Francois Donnet
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.\" with the GNU C Library; see the file COPYING. If not, write to the Free
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.\" Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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.\"
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.\"
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.\" Tool : Man pages
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.\" Date : 1991,92,2000
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@ -43,56 +42,50 @@ BooG \- Binding and Optimizing On Gates.
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.SH SYNOPSIS
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.TP
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\f4boog\fP \fIinput_file\fP \fIoutput_file\fP [\fIlax_file\fP]
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\f4boog\fP \-h
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\f4boog\fP [\-v] [\-m \fImode\fP] \fIinput_file\fP [\-o \fIoutput_file\fP] [\-l \fIlax_file\fP]
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\f4boog\fP [\-m \fImode\fP] \fIinput_file\fP \-d \fIdebug_file\fP\n\
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\f4boog\fP [-hmxold] \fIinput_file\fP \fIoutput_file\fP [\fIlax_file\fP]
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.br
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.SH DESCRIPTION
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.br
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Boog is a mapper of a behavioural description onto a standard cell library.
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.br
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\fB Input description\fP
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\fBBoog\fP is a mapper of a behavioural description onto a predefined standard cell library as SXLIB.
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It is the second step of the logic synthesis: it builds a gate network using a standard cell library.
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.br
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.br
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\fB Input file description\fP
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.br
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The logic level behavioural description (.vbe file) uses the same VHDL subset as the logic simulator \fBasimut\fP, the FSM synthesizer \fBsyf\fP, the functional abstractor \fByagle\fP and the formal prover \fBproof\fP (for further information about the subset of VHDL, see the "vbe" manual).
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.br
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A special feature has been introduced in the VHDL subset in order to allow the don't care description for external outputs and internal registers : A bit signal can take the 'd' value.
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This value is interpreted as a '0' by the logic simulator \fBasimut\fP.
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Don't Cares are automatically generated by \fBsyf\fP in the resulting '.vbe' file.
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Some constraints due to hardware mapping exist. These attributes are only supported by technology mapping onto a standard cell library as \fBsxlib\fP.
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.br
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For the register signal, only one signal can appear in a guarded expression since the STABLE attribute is used. This attribute is only supported by technology mapping onto a standard cell library as \fBsxlib\fP. Indeed you can associate a write enable signal in condition register. To resume only 2 descriptions are accepted as followed:
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\fIlabel: BLOCK (NOT ck 'STABLE and ck='1')
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.nf
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# Example
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BEGIN
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reg <= expr;
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END BLOCK;\fP
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or
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\fIlabel: BLOCK (NOT ck 'STABLE and ck='1' and wen='1')
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BEGIN
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reg <= expr;
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END BLOCK;\fP
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For the register signal description, only one condition statement must appear. STABLE must be strictely used as a negativ motion and joined to clock setup value. Setup can be on high or low value, but it would be worthy to choose it accordingly with hardware register cell.
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\fI# Example\fP
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label: BLOCK (NOT ck 'STABLE and ck='1')
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BEGIN
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reg <= GUARDED expr;
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END BLOCK;
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You can also put a write enable condition to your register:
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label: BLOCK (NOT ck 'STABLE and ck='1' and wen='1')
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BEGIN
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reg <= GUARDED expr;
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END BLOCK;
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.fi
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.ti 7
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\fBboog\fP is the second step of the logic synthesis : it builds a gate network using
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a predefined standard cell library as SXLIB.
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.br
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A special feature has been introduced in the VHDL subset in order to allow the don't care description for external outputs and internal registers : A bit signal can take the 'd' value.
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This value is interpreted as a '0' by the logic simulator \fBasimut\fP.
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Don't Cares are automatically generated by \fBsyf\fP in the resulting '.vbe' file.
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.br
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\fB Mapping with a standard cell library\fP
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\fB Output file description\fP
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.br
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A pure standard cell netlist is produced by \fBboog\fP. This file is destinated for /fBloon/fP alliance utility to improve RC delays.
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Any equipotential keeps its name from connector to connector. In trouble case, buffers are inserted to respect this VHDL constraint.
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.br
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Every cell appearing in the directory defined by the environment variable MBK_TARGET_LIB may be used by \fBboog\fP since they are described as a '.vbe' file. There are some restrictions about the type of the cell used. Every cell has to have only one output.
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The cell must be characterized. The timing and area informations required by \fBboog\fP are specified in the "generic" clause of the ".vbe" file.
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.br
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.br
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\fB Parameter file '.lax'\fP
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\fB lax Parameter file description\fP
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.br
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The lax file is common with other logic synthesis tools and is used
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for driving the synthesis process.
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@ -115,18 +108,24 @@ Here is the default lax file (see the user's manual for further information abou
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.br
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.br
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\fB Mapping with a standard cell library\fP
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.br
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Every cell appearing in the directory defined by the environment variable MBK_TARGET_LIB may be used by \fBboog\fP since they are described as a '.vbe' file. There are some restrictions about the type of the cell used. Every cell has to have only one output.
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The cell must be characterized. The timing and area informations required by \fBboog\fP are specified in the "generic" clause of the ".vbe" file.
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.br
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.SH OPTION
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.TP 10
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\f4\-h\fP
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Help mode. Displays possible uses of \fBboog\fP.
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.TP 10
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\f4\-v\fP
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Verbose mode. Displays timing and area informations.
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.TP 10
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\f4\-m mode\fP
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\f4\-m optim_mode\fP
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Optimization mode. Can be defined in lax file, it's only a shortcut to define it on command line. This mode number has an array defined between \fI0\fP and \fI4\fP. It indicates the way of optimization the user wants. If \fI0\fP is chosen, the circuit area will be improved. On the other hand, \fI4\fP will improve circuit delays. \fI2\fP is a medium value for optimization.
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.TP 10
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\f4\-x xsch_mode\fP
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Generate a '.xsc' file. It is a color map for each signals contained in \fIoutput_file\fP network. This file is used by \fBxsch\fP to view the netlist. By choosing level 0 or 1 for xsch_mode, you can color respectively the critical path or all signals with delay graduation.
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.TP 10
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\f4\-o output_file\fP
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Just another way to show explicitely the \fBVST\fP output file name.
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.TP 10
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@ -148,9 +147,6 @@ The following environment variables have to be set before using \fBboog\fP :
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\fIMBK_TARGET_LIB\fP gives the path (single) of the directory of the selected standard cell library.
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.HP
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.ti 7
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\fIMBK_IN_LO\fP gives the format of models instantiated in the structural description.
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.HP
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.ti 7
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\fIMBK_OUT_LO\fP gives the output format of the structural description.
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@ -165,15 +161,8 @@ You can call \fBboog\fP as follows :
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.SH SEE ALSO
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.br
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boog(1), scmap(1), c4map(1), xlmap(1), proof(1), yagle(1), asimut(1), vhdl(5), scr(1), sclib(1), sxlib(1).
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boog(1), boom(1), loon(1), lax(1), vbe(1), scmap(1), bop(1), glop(1), c4map(1), xlmap(1), proof(1), yagle(1), asimut(1), vhdl(5), scr(1), sclib(1), sxlib(1).
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.br
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.SH DIAGNOSTICS
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.br
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"VHDL : Error - bad usage of the 'stable' attribut"
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.br
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The stable attribut must be used with only one signal in a guarded expression
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.br
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.so man1/alc_bug_rprt.1
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.so man1/alc_bug_report.1
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