riscv
/
alliance
mirror of https://gitlab.lip6.fr/vlsi-eda/alliance.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

tralala

This commit is contained in:
Francois Donnet 2000-08-25 10:37:37 +00:00
parent 7156c6781e
commit be59697358
1 changed files with 1 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
alliance/share/man/man1/boog.1
View File

@ -59,6 +59,7 @@ The logic level behavioural description (.vbe file) uses the same VHDL subset as
Some constraints due to hardware mapping exist. These attributes are only supported by technology mapping onto a standard cell library as \f4sxlib\fP.
.br
For the register signal description, only one condition statement must appear. STABLE must be strictely used as a negativ motion and joined to clock setup value. Setup can be on high or low value, but it would be worthy to choose it accordingly with hardware register cell.
.br
\fI# Example\fP
label: BLOCK (NOT ck 'STABLE and ck='1')
BEGIN