cellules de transparences avec et sans boody tie
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@ -51,3 +51,7 @@ xr2_x4 C
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zero_x0 C
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one_x0.ap F
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zero_x0.ap F
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rowend_x0 C
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tie_x0 C
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rowend_x0 F
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tie_x0 F
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@ -0,0 +1,14 @@
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ENTITY rowend_x0 IS
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PORT (
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vdd : in BIT;
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vss : in BIT
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);
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END rowend_x0;
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ARCHITECTURE behaviour_data_flow OF rowend_x0 IS
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BEGIN
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ASSERT ((vdd and not (vss)) = '1')
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REPORT "power supply is missing on rowend_x0"
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SEVERITY WARNING;
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END;
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@ -0,0 +1,14 @@
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ENTITY tie_x0 IS
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PORT (
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vdd : in BIT;
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vss : in BIT
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);
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END tie_x0;
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ARCHITECTURE behaviour_data_flow OF tie_x0 IS
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BEGIN
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ASSERT ((vdd and not (vss)) = '1')
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REPORT "power supply is missing on tie_x0"
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SEVERITY WARNING;
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END;
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