From b6a59f9dcb19b0096ee397807fb395046b70a98f Mon Sep 17 00:00:00 2001
From: Franck Wajsburt <alliance-cvs@asim.lip6.fr>
Date: Wed, 15 Sep 1999 16:50:38 +0000
Subject: [PATCH] cellules de transparences avec et sans boody tie

---
 alliance/share/cells/sxlib/CATAL         |  4 ++++
 alliance/share/cells/sxlib/rowend_x0.vbe | 14 ++++++++++++++
 alliance/share/cells/sxlib/tie_x0.vbe    | 14 ++++++++++++++
 3 files changed, 32 insertions(+)
 create mode 100644 alliance/share/cells/sxlib/rowend_x0.vbe
 create mode 100644 alliance/share/cells/sxlib/tie_x0.vbe

diff --git a/alliance/share/cells/sxlib/CATAL b/alliance/share/cells/sxlib/CATAL
index 1e22c053..a0949daa 100644
--- a/alliance/share/cells/sxlib/CATAL
+++ b/alliance/share/cells/sxlib/CATAL
@@ -51,3 +51,7 @@ xr2_x4 C
 zero_x0 C
 one_x0.ap F
 zero_x0.ap F
+rowend_x0 C
+tie_x0 C
+rowend_x0 F
+tie_x0 F
diff --git a/alliance/share/cells/sxlib/rowend_x0.vbe b/alliance/share/cells/sxlib/rowend_x0.vbe
new file mode 100644
index 00000000..22b204c5
--- /dev/null
+++ b/alliance/share/cells/sxlib/rowend_x0.vbe
@@ -0,0 +1,14 @@
+ENTITY rowend_x0 IS
+PORT (
+  vdd	 : in  BIT;
+  vss	 : in  BIT
+);
+END rowend_x0;
+
+ARCHITECTURE behaviour_data_flow OF rowend_x0 IS
+
+BEGIN
+  ASSERT ((vdd and not (vss)) = '1')
+  REPORT "power supply is missing on rowend_x0"
+  SEVERITY WARNING;
+END;
diff --git a/alliance/share/cells/sxlib/tie_x0.vbe b/alliance/share/cells/sxlib/tie_x0.vbe
new file mode 100644
index 00000000..1cb9788c
--- /dev/null
+++ b/alliance/share/cells/sxlib/tie_x0.vbe
@@ -0,0 +1,14 @@
+ENTITY tie_x0 IS
+PORT (
+  vdd	 : in  BIT;
+  vss	 : in  BIT
+);
+END tie_x0;
+
+ARCHITECTURE behaviour_data_flow OF tie_x0 IS
+
+BEGIN
+  ASSERT ((vdd and not (vss)) = '1')
+  REPORT "power supply is missing on tie_x0"
+  SEVERITY WARNING;
+END;