Nouveau "tutorial" pour VASY

alliance/share/tutorials/vasy/hadamard/1

@@ -0,0 +1,2 @@
+rm CATAL Makefile calcul.vhdl compteur.vhdl ex0.stim ex1.stim ex2.stim ex3.stim hadamard hadamard.stim hadamard.vhdl hadamard_1.pat hadamard_2.pat hadamard_3.pat hadamard_tb.vhdl ram.vhdl rom.vhdl sequenceur.vhdl
+cvs remove CATAL Makefile calcul.vhdl compteur.vhdl ex0.stim ex1.stim ex2.stim ex3.stim hadamard hadamard.stim hadamard.vhdl hadamard_1.pat hadamard_2.pat hadamard_3.pat hadamard_tb.vhdl ram.vhdl rom.vhdl sequenceur.vhdl

alliance/share/tutorials/vasy/hadamard/Makefile

@@ -51,7 +51,8 @@ include $(ALLIANCE_TOP)/etc/libraries.mk
 # |                                                             |
 # \------------------------------------------------------------*/
 
-VASY   = $(ALLIANCE_TOP)/bin/vasy
+# VASY   = $(ALLIANCE_TOP)/bin/vasy
+VASY = $(HOME)/dev/bin/SunOS/vasy
 ASIMUT = $(ALLIANCE_TOP)/bin/asimut
 
 # /*------------------------------------------------------------\
@@ -90,7 +91,7 @@ result_3.pat : hadamard.vst
 # \------------------------------------------------------------*/
 
 hadamard.vst : hadamard.vhdl
-	$(ENV_VASY); $(VASY) -a -I vhdl -H hadamard
+	$(ENV_VASY); $(VASY) -a -o -I vhdl -H hadamard
 
 
 # /*------------------------------------------------------------\

alliance/share/tutorials/vasy/multi8/CATAL

@@ -0,0 +1,5 @@
+addaccu		C
+multi8_model	C
+srb		C
+controller	C
+sra		C

alliance/share/tutorials/vasy/multi8/Makefile

@@ -0,0 +1,257 @@
+# /*------------------------------------------------------------\
+# |                                                             |
+# | This file is part of the Alliance CAD System Copyright      |
+# | (C) Laboratoire LIP6 - Département ASIM Universite P&M Curie|
+# |                                                             |
+# | Home page      : http://www-asim.lip6.fr/alliance/          |
+# | E-mail support : mailto:alliance-support@asim.lip6.fr       |
+# |                                                             |
+# | This progam is  free software; you can redistribute it      |
+# | and/or modify it under the  terms of the GNU General Public |
+# | License as  published by the Free Software Foundation;      |
+# | either version 2 of the License, or (at your option) any    |
+# | later version.                                              |
+# |                                                             |
+# | Alliance VLSI  CAD System  is distributed  in the hope that |
+# | it  will be useful, but WITHOUT  ANY WARRANTY;              |
+# | without even the  implied warranty of MERCHANTABILITY or    |
+# | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General       |
+# | Public License for more details.                            |
+# |                                                             |
+# | You should have received a copy  of the GNU General Public  |
+# | License along with the GNU C Library; see the file COPYING. |
+# | If not, write to the Free Software Foundation, Inc.,        |
+# | 675 Mass Ave, Cambridge, MA 02139, USA.                     |
+# |                                                             |
+# \------------------------------------------------------------*/
+
+# /*------------------------------------------------------------\
+# |                                                             |
+# | Tool   :                      VASY                          |
+# |                                                             |
+# | File   :                    Makefile                        |
+# |                                                             |
+# | Author :                 Jacomme Ludovic                    |
+# |                                                             |
+# | Date    :                   30_05_2000                      |
+# |                                                             |
+# \------------------------------------------------------------*/
+
+include $(ALLIANCE_TOP)/etc/$(ALLIANCE_OS).mk
+include $(ALLIANCE_TOP)/etc/libraries.mk
+
+# /*------------------------------------------------------------\
+# |                                                             |
+# |                              Cells                          |
+# |                                                             |
+# \------------------------------------------------------------*/
+# /*------------------------------------------------------------\
+# |                                                             |
+# |                             Binary                          |
+# |                                                             |
+# \------------------------------------------------------------*/
+
+TOUCH  = touch
+VASY   = $(ALLIANCE_TOP)/bin/vasy
+ASIMUT = $(ALLIANCE_TOP)/bin/asimut
+BOP    = $(ALLIANCE_TOP)/bin/bop
+SCMAP  = $(ALLIANCE_TOP)/bin/scmap
+PROOF  = $(ALLIANCE_TOP)/bin/proof
+SCR    = $(ALLIANCE_TOP)/bin/scr
+LYNX   = $(ALLIANCE_TOP)/bin/lynx
+LVX    = $(ALLIANCE_TOP)/bin/lvx
+DRUC   = $(ALLIANCE_TOP)/bin/druc
+
+# /*------------------------------------------------------------\
+# |                                                             |
+# |                            Environement                     |
+# |                                                             |
+# \------------------------------------------------------------*/
+
+ENV_VASY = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
+           MBK_CATAL_NAME=NO_CATAL; export MBK_CATAL_NAME
+
+ENV_ASIMUT = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
+             MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME;\
+             MBK_IN_LO=vst; export MBK_IN_LO;\
+	     MBK_OUT_LO=vst; export MBK_OUT_LO
+
+ENV_SIMU_VBE = MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib; export MBK_CATA_LIB;\
+               MBK_WORK_LIB=.; export MBK_WORK_LIB;\
+               MBK_CATAL_NAME=CATAL_VBE; export MBK_CATAL_NAME;\
+               MBK_IN_LO=vst; export MBK_IN_LO;\
+	       MBK_OUT_LO=vst; export MBK_OUT_LO
+
+ENV_SIMU_VST = MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib; export MBK_CATA_LIB;\
+               MBK_WORK_LIB=.; export MBK_WORK_LIB;\
+               MBK_CATAL_NAME=NO_CATAL; export MBK_CATAL_NAME;\
+               MBK_IN_LO=vst; export MBK_IN_LO;\
+	       MBK_OUT_LO=vst; export MBK_OUT_LO
+
+ENV_SYNTH = MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib; export MBK_CATA_LIB;\
+            MBK_TARGET_LIB=$(ALLIANCE_TOP)/cells/sxlib; export MBK_TARGET_LIB;\
+            MBK_WORK_LIB=.; export MBK_WORK_LIB;\
+            MBK_CATAL_NAME=CATAL_VBE; export MBK_CATAL_NAME;\
+            MBK_IN_LO=vst; export MBK_IN_LO;\
+	    MBK_OUT_LO=vst; export MBK_OUT_LO
+
+ENV_ROUTE = MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib; export MBK_CATA_LIB;\
+            MBK_WORK_LIB=.; export MBK_WORK_LIB;\
+            MBK_CATAL_NAME=NO_CATAL; export MBK_CATAL_NAME;\
+            MBK_IN_PH=ap; export MBK_IN_PH;\
+	    MBK_OUT_PH=ap; export MBK_OUT_PH;\
+            MBK_IN_LO=vst; export MBK_IN_LO;\
+	    MBK_OUT_LO=al; export MBK_OUT_LO
+
+ENV_PHYS = MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib; export MBK_CATA_LIB;\
+           MBK_WORK_LIB=.; export MBK_WORK_LIB;\
+           MBK_CATAL_NAME=NO_CATAL; export MBK_CATAL_NAME;\
+	   RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/cmos_11.rds; \
+	   export RDS_TECHNO_NAME;\
+	   RDS_IN=cif; export RDS_IN;\
+	   RDS_OUT=cif; export RDS_OUT;\
+           MBK_IN_PH=ap; export MBK_IN_PH;\
+	   MBK_OUT_PH=ap; export MBK_OUT_PH;\
+           MBK_IN_LO=al; export MBK_IN_LO;\
+	   MBK_OUT_LO=al; export MBK_OUT_LO
+
+all : multi8_drc
+
+# /*------------------------------------------------------------\
+# |                                                             |
+# |                             Vasy                            |
+# |                                                             |
+# \------------------------------------------------------------*/
+
+multi8.vst : addaccu.vhdl controller.vhdl multi8.vhdl sra.vhdl srb.vhdl
+	$(ENV_VASY); $(VASY) -a -o -I vhdl -HLpV multi8
+
+# /*------------------------------------------------------------\
+# |                                                             |
+# |                      Behavioral Simulation                  |
+# |                                                             |
+# \------------------------------------------------------------*/
+
+result_beh_pat : multi8.vst
+	$(ENV_ASIMUT); $(ASIMUT) multi8 multi8 result_beh
+	$(TOUCH) result_beh_pat
+
+# /*------------------------------------------------------------\
+# |                                                             |
+# |                         Boolean Optimization                |
+# |                                                             |
+# \------------------------------------------------------------*/
+
+srao_vbe : result_beh_pat
+	$(ENV_SYNTH); $(BOP) -o sra srao
+	$(ENV_SYNTH); $(PROOF) sra srao
+	$(TOUCH) srao_vbe
+
+srbo_vbe : result_beh_pat
+	$(ENV_SYNTH); $(BOP) -o srb srbo
+	$(ENV_SYNTH); $(PROOF) srb srbo
+	$(TOUCH) srbo_vbe
+
+addaccuo_vbe : result_beh_pat
+	$(ENV_SYNTH); $(BOP) -o addaccu addaccuo addaccu
+	$(ENV_SYNTH); $(PROOF) addaccu addaccuo
+	$(TOUCH) addaccuo_vbe
+
+controllero_vbe : result_beh_pat
+	$(ENV_SYNTH); $(BOP) -o controller controllero
+	$(ENV_SYNTH); $(PROOF) controller controllero
+	$(TOUCH) controllero_vbe
+
+multi8_modelo_vbe : result_beh_pat
+	$(ENV_SYNTH); $(BOP) -o multi8_model multi8_modelo
+	$(ENV_SYNTH); $(PROOF) multi8_model multi8_modelo
+	$(TOUCH) multi8_modelo_vbe
+
+# /*------------------------------------------------------------\
+# |                                                             |
+# |                           Mapping                           |
+# |                                                             |
+# \------------------------------------------------------------*/
+
+sra.vst : srao_vbe
+	$(ENV_SYNTH); $(SCMAP) srao sra
+
+srb.vst : srbo_vbe
+	$(ENV_SYNTH); $(SCMAP) srbo srb
+
+addaccu.vst : addaccuo_vbe
+# $(ENV_SYNTH); $(SCMAP) addaccuo addaccu
+	echo Bug with SCMAP just make a copy 
+	cp addaccu.vst.patched addaccu.vst
+	$(TOUCH) addaccu.vst
+
+controller.vst : controllero_vbe
+	$(ENV_SYNTH); $(SCMAP) controllero controller
+
+multi8_model.vst : multi8_modelo_vbe
+	$(ENV_SYNTH); $(SCMAP) multi8_modelo multi8_model
+
+# /*------------------------------------------------------------\
+# |                                                             |
+# |                      Structural Simulation                  |
+# |                                                             |
+# \------------------------------------------------------------*/
+
+result_vst_pat : addaccu.vst controller.vst multi8.vst multi8_model.vst \
+                 sra.vst srb.vst
+	$(ENV_SIMU_VST); $(ASIMUT) -zd multi8 multi8 result_vst 
+	$(TOUCH) result_vst_pat
+
+# /*------------------------------------------------------------\
+# |                                                             |
+# |                        Place And Route                      |
+# |                                                             |
+# \------------------------------------------------------------*/
+
+multi8.ap : result_vst_pat
+	$(ENV_ROUTE); $(SCR) -p -r -i 1000 multi8 multi8
+
+# /*------------------------------------------------------------\
+# |                                                             |
+# |                           Extract                           |
+# |                                                             |
+# \------------------------------------------------------------*/
+
+multi8.al : multi8.ap
+	$(ENV_PHYS); $(LYNX) -v multi8 multi8
+
+# /*------------------------------------------------------------\
+# |                                                             |
+# |                           NetList Comparison                |
+# |                                                             |
+# \------------------------------------------------------------*/
+
+multi8_lvx : multi8.al
+	$(ENV_PHYS); $(LVX) vst al multi8 multi8 -f
+	$(TOUCH) multi8_lvx
+
+# /*------------------------------------------------------------\
+# |                                                             |
+# |                           Design Rules Check                |
+# |                                                             |
+# \------------------------------------------------------------*/
+
+multi8_drc : multi8_lvx
+	$(ENV_PHYS); $(DRUC) multi8
+	$(TOUCH) multi8_drc
+
+
+
+# /*------------------------------------------------------------\
+# |                                                             |
+# |                              Clean                          |
+# |                                                             |
+# \------------------------------------------------------------*/
+
+realclean : clean
+
+clean     :
+	$(RM) -f *vst *vbe result_vst.pat  result_beh.pat
+	$(RM) -f result_vst_pat  result_beh_pat multi8_drc multi8_lvx
+	$(RM) -f *.al *.ap *.lax *.drc *.cif
+	

alliance/share/tutorials/vasy/multi8/addaccu.vhdl

@@ -0,0 +1,34 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_arith.ALL;
+use IEEE.STD_LOGIC_unsigned.ALL;
+
+
+entity AddAccu is
+
+    port ( CLR : in Std_Logic;
+           LD : in Std_Logic;
+           OUTS : in Std_Logic_Vector(15 downto 0) ;
+           CLK : in Std_Logic;
+
+           RESULT : out Std_Logic_Vector(15 downto 0) );
+
+end AddAccu;
+
+
+----------------------------------------------------------------------
+
+architecture DataFlow OF AddAccu is
+signal resultint : Std_Logic_Vector(15 downto 0) ;
+begin
+process (CLK)
+begin
+   if CLK'event and CLK='0' then
+      if CLR = '1' then resultint  <= ( others => '0' );
+      elsif LD = '1' then resultint <= resultint + OUTS;
+      end if;
+ end if;
+end process;
+RESULT <= resultint;
+end DataFlow;
+----------------------------------------------------------------------

alliance/share/tutorials/vasy/multi8/controller.vhdl

@@ -0,0 +1,59 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity Controller is
+  port (STB, CLK, LSB, Done, RST:	in	STD_LOGIC;
+	Init, Shift, Add:	out	STD_LOGIC);
+end Controller;
+
+---------------------------------------------------
+
+architecture FSM of Controller is
+
+  type States is (EndS,InitS, CheckS, AddS, ShiftS);
+  signal State: States ;
+begin
+
+  -- Drive control outputs based upon State
+
+  Init  <= '1' when State = InitS  else '0';
+  Add   <= '1' when State = AddS   else '0';
+  Shift <= '1' when State = ShiftS else '0';
+
+  -- Determine Next State from control inputs
+
+  StateMachine:
+
+    process (CLK)
+    begin
+	--compass stateMachine adj State
+      if CLK'Event and CLK = '0' then
+	if RST = '1' then State <= EndS;
+	else
+	case State is
+	  when InitS =>
+	    State <= CheckS;
+	  when CheckS =>
+	    if LSB = '1' then
+	      State <= AddS;
+	    elsif Done = '0' then
+	      State <= ShiftS;
+	    else
+	      State <= EndS;
+	    end if;
+	  when AddS =>
+	    State <= ShiftS;
+	  when ShiftS =>
+	    State <= CheckS;
+	  when EndS =>
+	    if STB = '1' then
+	      State <= InitS;
+	    end if;
+	end case;
+	end if;
+      end if;
+    end process;
+
+end FSM;
+
+---------------------------------------------------

alliance/share/tutorials/vasy/multi8/multi8.do

@@ -0,0 +1,16 @@
+wave CLK
+wave RST
+wave STB
+wave DONE
+wave -dec A
+wave -dec B
+wave -dec RESULT
+
+force clk 1 50 , 0 100 -repeat 100
+force RST 1
+run
+force RST 0
+force STB 1
+force A   10#123
+force B   10#12
+run

alliance/share/tutorials/vasy/multi8/multi8.inc

@@ -0,0 +1,91 @@
+trace /MULTI8/U3/STATE
+
+cd MULTI8
+trace A
+trace B
+trace CLK
+trace RST
+trace STB
+trace RESULT
+trace DONE
+
+assign ("00000111") A
+assign ("00000011") B
+assign ('1') RST
+
+assign ('0') CLK
+run 50
+assign ('1') CLK
+run 50
+assign ('0') CLK
+run 50
+
+assign ('0') RST
+assign ('1') STB
+
+run 50
+assign ('1') CLK
+run 50
+assign ('0') CLK
+run 50
+
+run 50
+assign ('1') CLK
+run 50
+assign ('0') CLK
+run 50
+
+assign ('1') CLK
+run 50
+assign ('0') CLK
+run 50
+
+assign ('1') CLK
+run 50
+assign ('0') CLK
+run 50
+
+assign ('1') CLK
+run 50
+assign ('0') CLK
+run 50
+
+assign ('1') CLK
+run 50
+assign ('0') CLK
+run 50
+
+assign ('1') CLK
+run 50
+assign ('0') CLK
+run 50
+
+assign ('1') CLK
+run 50
+assign ('0') CLK
+run 50
+
+assign ('1') CLK
+run 50
+assign ('0') CLK
+run 50
+
+assign ('1') CLK
+run 50
+assign ('0') CLK
+run 50
+
+assign ('1') CLK
+run 50
+assign ('0') CLK
+run 50
+
+assign ('1') CLK
+run 50
+assign ('0') CLK
+run 50
+
+assign ('1') CLK
+run 50
+assign ('0') CLK
+run 50

alliance/share/tutorials/vasy/multi8/multi8.pat

@@ -0,0 +1,51 @@
+-- input / output list :
+
+in       clk B;;
+in       rst B;;
+in       stb B;;
+in       a (7 downto 0) X;;
+in       b (7 downto 0) X;;
+out      result (15 downto 0) X;;
+out      done B;
+
+begin
+
+-- Pattern description :
+
+--    C R S A  B   R     D 
+--    L S T        E     O 
+--    K T B        S     N 
+--                 U     E 
+--                 L       
+--                 T       
+
+    : 0 1 0 00 00 ?**** ?u;
+    : 1 1 0 00 00 ?**** ?u;
+    : 0 1 0 00 00 ?**** ?u;
+    : 0 0 0 00 00 ?**** ?u;
+    : 0 0 1 00 00 ?**** ?u;
+    : 1 0 1 00 00 ?**** ?u;
+    : 0 0 1 00 00 ?**** ?u;
+    : 0 0 0 02 03 ?**** ?u;
+    : 1 0 0 02 03 ?**** ?u;
+    : 0 0 0 02 03 ?0000 ?0;
+    : 0 0 0 00 00 ?0000 ?0;
+    : 1 0 0 00 00 ?0000 ?0;
+    : 0 0 0 00 00 ?0000 ?0;
+    : 0 0 0 00 00 ?0000 ?0;
+    : 1 0 0 00 00 ?0000 ?0;
+    : 0 0 0 00 00 ?0000 ?0;
+    : 0 0 0 00 00 ?0000 ?0;
+    : 1 0 0 00 00 ?0000 ?0;
+    : 0 0 0 00 00 ?0000 ?0;
+    : 0 0 0 00 00 ?0000 ?0;
+    : 1 0 0 00 00 ?0000 ?0;
+    : 0 0 0 00 00 ?0006 ?0;
+    : 0 0 0 00 00 ?0006 ?0;
+    : 1 0 0 00 00 ?0006 ?0;
+    : 0 0 0 00 00 ?0006 ?1;
+    : 0 0 0 00 00 ?0006 ?1;
+    : 1 0 0 00 00 ?0006 ?1;
+    : 0 0 0 00 00 ?0006 ?1;
+
+end;

alliance/share/tutorials/vasy/multi8/multi8.vhdl

@@ -0,0 +1,121 @@
+-- Date of netlist generation:  Dec-6-95
+----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity Multi8 is
+
+
+    port ( A : in Std_Logic_Vector(7 downto 0) ;
+           B : in Std_Logic_Vector(7 downto 0) ;
+           CLK : in Std_Logic ;
+           RST : in Std_Logic ;
+           STB : in Std_Logic ;
+
+           RESULT : out Std_Logic_Vector(15 downto 0) ;
+           DONE : out Std_Logic );
+
+end Multi8;
+
+----------------------------------------------------------------------
+
+architecture Structural OF Multi8 is
+
+    component Controller
+        port ( STB : in Std_Logic;
+               CLK : in Std_Logic;
+               LSB : in Std_Logic;
+               DONE : in Std_Logic;
+               RST : in Std_Logic;
+
+               INIT : out Std_Logic;
+               SHIFT : out Std_Logic;
+               ADD : out Std_Logic );
+    end component;
+
+    component Srb
+        port ( SHIFT : in Std_Logic;
+               LD : in Std_Logic;
+               CLK : in Std_Logic;
+               B : in Std_Logic_Vector(7 downto 0) ;
+
+               OUTS : out Std_Logic_Vector(15 downto 0)  );
+    end component;
+
+    component AddAccu
+        port ( CLR : in Std_Logic;
+               LD : in Std_Logic;
+               OUTS : in Std_Logic_Vector(15 downto 0) ;
+               CLK : in Std_Logic;
+
+               RESULT : out Std_Logic_Vector(15 downto 0)  );
+    end component;
+
+    component Sra
+        port ( SHIFT : in Std_Logic;
+               LD : in Std_Logic;
+               CLK : in Std_Logic;
+               RST : in Std_Logic;
+               A : in Std_Logic_Vector(7 downto 0) ;
+
+               DONE : out Std_Logic;
+               LSB : out Std_Logic );
+    end component;
+
+
+    signal DONE_local: Std_Logic;
+    signal U1_LSB : Std_Logic;
+    signal U3_INIT : Std_Logic;
+    signal U3_SHIFT : Std_Logic;
+    signal U3_ADD : Std_Logic;
+    signal OUT_INT : Std_Logic_vector(15 downto 0);
+
+begin
+
+
+    U3: Controller
+        port map ( STB => STB,
+                   CLK => CLK,
+                   LSB => U1_LSB,
+                   DONE => DONE_local,
+                   RST => RST,
+                   INIT => U3_INIT,
+                   SHIFT => U3_SHIFT,
+                   ADD => U3_ADD );
+
+    U2: Srb
+        port map ( SHIFT => U3_SHIFT,
+                   LD => U3_INIT,
+                   CLK => CLK,
+                   B => B,
+                   OUTS => OUT_INT );
+
+    U5: AddAccu
+        port map ( CLR => U3_INIT,
+                   LD => U3_ADD,
+                   OUTS => OUT_INT,
+                   CLK => CLK,
+                   RESULT => RESULT );
+
+    U1: Sra
+        port map ( SHIFT => U3_SHIFT,
+                   LD => U3_INIT,
+                   RST => RST,
+                   CLK => CLK,
+                   A => A,
+                   DONE => DONE_local,
+                   LSB => U1_LSB );
+
+    DONE <= DONE_local;
+
+end Structural;
+
+configuration CFG_Multi8 of Multi8 is
+   for Structural
+
+   end for;
+end CFG_Multi8;
+
+
+----------------------------------------------------------------------

alliance/share/tutorials/vasy/multi8/multi8_debug.pat

@@ -0,0 +1,67 @@
+
+in       clk B;;
+in       rst B;;
+in       stb B;;
+in       A (7 downto 0) X;;
+in       B (7 downto 0) X;;
+out      result (15 downto 0) X;;
+out      done B;
+
+register u3.state(0 to 2) X;;
+register u1.outsint(7 downto 0) X;;
+
+begin
+
+-- PATTERN DESCRIPTION :
+
+ : 0 1 0 00 00 ?**** ?* ?* ?**;
+ : 1 1 0 00 00 ?**** ?* ?* ?**;
+ : 0 1 0 00 00 ?**** ?* ?* ?**;
+ : 0 0 0 00 00 ?**** ?* ?* ?**;
+ : 0 0 1 00 00 ?**** ?* ?* ?**;
+ : 1 0 1 00 00 ?**** ?* ?* ?**;
+ : 0 0 1 00 00 ?**** ?* ?* ?**;
+ : 0 0 0 02 03 ?**** ?* ?* ?**;
+ : 1 0 0 02 03 ?**** ?* ?* ?**;
+ : 0 0 0 02 03 ?**** ?* ?* ?**;
+ : 0 0 0 00 00 ?**** ?* ?* ?**;
+ : 1 0 0 00 00 ?**** ?* ?* ?**;
+ : 0 0 0 00 00 ?**** ?* ?* ?**;
+ : 0 0 0 00 00 ?**** ?* ?* ?**;
+ : 1 0 0 00 00 ?**** ?* ?* ?**;
+ : 0 0 0 00 00 ?**** ?* ?* ?**;
+ : 0 0 0 00 00 ?**** ?* ?* ?**;
+ : 1 0 0 00 00 ?**** ?* ?* ?**;
+ : 0 0 0 00 00 ?**** ?* ?* ?**;
+ : 0 0 0 00 00 ?**** ?* ?* ?**;
+ : 1 0 0 00 00 ?**** ?* ?* ?**;
+ : 0 0 0 00 00 ?**** ?* ?* ?**;
+ : 0 0 0 00 00 ?**** ?* ?* ?**;
+ : 1 0 0 00 00 ?**** ?* ?* ?**;
+ : 0 0 0 00 00 ?**** ?* ?* ?**;
+ : 0 0 0 00 00 ?**** ?* ?* ?**;
+ : 1 0 0 00 00 ?**** ?* ?* ?**;
+ : 0 0 0 00 00 ?**** ?* ?* ?**;
+ : 0 0 0 00 00 ?**** ?* ?* ?**;
+ : 1 0 0 00 00 ?**** ?* ?* ?**;
+ : 0 0 0 00 00 ?**** ?* ?* ?**;
+ : 0 0 0 00 00 ?**** ?* ?* ?**;
+ : 1 0 0 00 00 ?**** ?* ?* ?**;
+ : 0 0 0 00 00 ?**** ?* ?* ?**;
+ : 0 0 0 00 00 ?**** ?* ?* ?**;
+ : 1 0 0 00 00 ?**** ?* ?* ?**;
+ : 0 0 0 00 00 ?**** ?* ?* ?**;
+ : 0 0 0 00 00 ?**** ?* ?* ?**;
+ : 1 0 0 00 00 ?**** ?* ?* ?**;
+ : 0 0 0 00 00 ?**** ?* ?* ?**;
+ : 0 0 0 00 00 ?**** ?* ?* ?**;
+ : 1 0 0 00 00 ?**** ?* ?* ?**;
+ : 0 0 0 00 00 ?**** ?* ?* ?**;
+ : 0 0 0 00 00 ?**** ?* ?* ?**;
+ : 1 0 0 00 00 ?**** ?* ?* ?**;
+ : 0 0 0 00 00 ?**** ?* ?* ?**;
+ : 0 0 0 00 00 ?**** ?* ?* ?**;
+ : 1 0 0 00 00 ?**** ?* ?* ?**;
+ : 0 0 0 00 00 ?**** ?* ?* ?**;
+
+end;

alliance/share/tutorials/vasy/multi8/sra.vhdl

@@ -0,0 +1,55 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_arith.ALL;
+use IEEE.STD_LOGIC_unsigned.ALL;
+
+entity Sra is
+
+    port ( Shift : in Std_Logic ;
+           LD : in Std_Logic ;
+	   RST : in Std_Logic;
+           CLK : in Std_Logic ;
+           A : in Std_Logic_Vector(7 downto 0);
+
+           Done : out Std_Logic ;
+           LSB : out Std_Logic  );
+
+end Sra;
+
+
+----------------------------------------------------------------------
+
+architecture DataFlow OF Sra is
+
+signal outsint : Std_Logic_Vector(7 downto 0);
+begin
+process (CLK)
+begin
+     if CLK'event and CLK='0' then
+         if RST ='1' then outsint <= (others => '0');
+	 elsif LD = '1' then outsint <= A ;
+         elsif Shift= '1' then
+            outsint(7 downto 0) <= '0' & outsint(7 downto 1);
+	else outsint <= outsint;
+         end if;
+     end if;
+end process;
+
+process( outsint )
+  variable RESULT : Std_Logic;
+begin
+   RESULT := '0';
+   for j in outsint'range loop
+       RESULT := outsint(j) or RESULT;
+       exit when RESULT = '1';
+   end loop;
+   RESULT := not(RESULT);
+
+   Done <= RESULT;
+end process;
+LSB <= outsint(0);
+
+end DataFlow;
+
+
+----------------------------------------------------------------------

alliance/share/tutorials/vasy/multi8/srb.vhdl

@@ -0,0 +1,41 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_arith.ALL;
+use IEEE.STD_LOGIC_unsigned.ALL;
+
+entity Srb is
+
+    port ( Shift : in Std_Logic ;
+           LD : in Std_Logic ;
+           CLK : in Std_Logic ;
+           B : in Std_Logic_Vector(7 downto 0);
+
+           OUTS : out Std_Logic_Vector(15 downto 0));
+
+end Srb;
+
+
+----------------------------------------------------------------------
+
+architecture DataFlow OF Srb is
+signal outsint : Std_Logic_Vector(15 downto 0);
+
+begin
+process (CLK)
+begin
+     if CLK'event and CLK='0' then
+         if LD = '1' then outsint <= 
+	    B(7)&B(7)&B(7)&B(7)&B(7)&B(7)&B(7)&B(7)&B ;
+         elsif Shift= '1' then  
+              outsint(15 downto 0) <= outsint(14 downto 0) & '0';
+	 else outsint <= outsint;
+         end if;
+     end if;
+end process;
+
+OUTS <= outsint;
+
+end DataFlow;
+
+
+----------------------------------------------------------------------