alliance/alliance/share/tutorials/vasy/multi8/addaccu.vst.patched

-- VHDL structural description generated from `addaccu`
--		date : Tue May 30 19:36:46 2000


-- Entity Declaration

ENTITY addaccu IS
  PORT (
  clr : in BIT;	-- clr
  ld : in BIT;	-- ld
  outs : in BIT_VECTOR (15 DOWNTO 0);	-- outs
  clk : in BIT;	-- clk
  result : inout BIT_VECTOR (15 DOWNTO 0);	-- result
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END addaccu;

-- Architecture Declaration

ARCHITECTURE VST OF addaccu IS
  COMPONENT nao22_x1
    port (
    i0 : in BIT;	-- i0
    i1 : in BIT;	-- i1
    i2 : in BIT;	-- i2
    nq : out BIT;	-- nq
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT o4_x2
    port (
    i0 : in BIT;	-- i0
    i1 : in BIT;	-- i1
    i2 : in BIT;	-- i2
    i3 : in BIT;	-- i3
    q : out BIT;	-- q
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT ao2o22_x2
    port (
    i0 : in BIT;	-- i0
    i1 : in BIT;	-- i1
    i2 : in BIT;	-- i2
    i3 : in BIT;	-- i3
    q : out BIT;	-- q
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT a3_x2
    port (
    i0 : in BIT;	-- i0
    i1 : in BIT;	-- i1
    i2 : in BIT;	-- i2
    q : out BIT;	-- q
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT o3_x2
    port (
    i0 : in BIT;	-- i0
    i1 : in BIT;	-- i1
    i2 : in BIT;	-- i2
    q : out BIT;	-- q
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT noa22_x1
    port (
    i0 : in BIT;	-- i0
    i1 : in BIT;	-- i1
    i2 : in BIT;	-- i2
    nq : out BIT;	-- nq
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT na2_x1
    port (
    i0 : in BIT;	-- i0
    i1 : in BIT;	-- i1
    nq : out BIT;	-- nq
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT xr2_x1
    port (
    i0 : in BIT;	-- i0
    i1 : in BIT;	-- i1
    q : out BIT;	-- q
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT no2_x1
    port (
    i0 : in BIT;	-- i0
    i1 : in BIT;	-- i1
    nq : out BIT;	-- nq
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT nxr2_x1
    port (
    i0 : in BIT;	-- i0
    i1 : in BIT;	-- i1
    nq : out BIT;	-- nq
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT ao22_x2
    port (
    i0 : in BIT;	-- i0
    i1 : in BIT;	-- i1
    i2 : in BIT;	-- i2
    q : out BIT;	-- q
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT oa2a22_x2
    port (
    i0 : in BIT;	-- i0
    i1 : in BIT;	-- i1
    i2 : in BIT;	-- i2
    i3 : in BIT;	-- i3
    q : out BIT;	-- q
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT on12_x1
    port (
    i0 : in BIT;	-- i0
    i1 : in BIT;	-- i1
    q : out BIT;	-- q
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT an12_x1
    port (
    i0 : in BIT;	-- i0
    i1 : in BIT;	-- i1
    q : out BIT;	-- q
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT buf_x2
    port (
  i	 : in  BIT;
  q	 : out BIT;
  vdd	 : in  BIT;
  vss	 : in  BIT
    );
  END COMPONENT;

  COMPONENT inv_x1
    port (
    i : in BIT;	-- i
    nq : out BIT;	-- nq
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT o2_x2
    port (
    i0 : in BIT;	-- i0
    i1 : in BIT;	-- i1
    q : out BIT;	-- q
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT a2_x2
    port (
    i0 : in BIT;	-- i0
    i1 : in BIT;	-- i1
    q : out BIT;	-- q
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT oa22_x2
    port (
    i0 : in BIT;	-- i0
    i1 : in BIT;	-- i1
    i2 : in BIT;	-- i2
    q : out BIT;	-- q
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT sff1_x4
    port (
    ck : in BIT;	-- ck
    i : in BIT;	-- i
    q : out BIT;	-- q
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  SIGNAL int_result : BIT_VECTOR(15 downto 0);
  SIGNAL rtlcarry_0_14 : BIT;	-- rtlcarry_0_14
  SIGNAL rtlcarry_0_13 : BIT;	-- rtlcarry_0_13
  SIGNAL rtlcarry_0_12 : BIT;	-- rtlcarry_0_12
  SIGNAL rtlcarry_0_11 : BIT;	-- rtlcarry_0_11
  SIGNAL rtlcarry_0_10 : BIT;	-- rtlcarry_0_10
  SIGNAL rtlcarry_0_9 : BIT;	-- rtlcarry_0_9
  SIGNAL rtlcarry_0_8 : BIT;	-- rtlcarry_0_8
  SIGNAL rtlcarry_0_7 : BIT;	-- rtlcarry_0_7
  SIGNAL rtlcarry_0_6 : BIT;	-- rtlcarry_0_6
  SIGNAL rtlcarry_0_5 : BIT;	-- rtlcarry_0_5
  SIGNAL rtlcarry_0_4 : BIT;	-- rtlcarry_0_4
  SIGNAL rtlcarry_0_3 : BIT;	-- rtlcarry_0_3
  SIGNAL rtlcarry_0_2 : BIT;	-- rtlcarry_0_2
  SIGNAL auxsc27 : BIT;	-- auxsc27
  SIGNAL auxsc24 : BIT;	-- auxsc24
  SIGNAL auxsc16 : BIT;	-- auxsc16
  SIGNAL auxsc28 : BIT;	-- auxsc28
  SIGNAL auxsc34 : BIT;	-- auxsc34
  SIGNAL auxsc35 : BIT;	-- auxsc35
  SIGNAL auxsc36 : BIT;	-- auxsc36
  SIGNAL auxsc45 : BIT;	-- auxsc45
  SIGNAL auxsc46 : BIT;	-- auxsc46
  SIGNAL auxsc52 : BIT;	-- auxsc52
  SIGNAL auxsc53 : BIT;	-- auxsc53
  SIGNAL auxsc54 : BIT;	-- auxsc54
  SIGNAL auxsc55 : BIT;	-- auxsc55
  SIGNAL auxsc64 : BIT;	-- auxsc64
  SIGNAL auxsc65 : BIT;	-- auxsc65
  SIGNAL auxsc71 : BIT;	-- auxsc71
  SIGNAL auxsc72 : BIT;	-- auxsc72
  SIGNAL auxsc73 : BIT;	-- auxsc73
  SIGNAL auxsc74 : BIT;	-- auxsc74
  SIGNAL auxsc83 : BIT;	-- auxsc83
  SIGNAL auxsc84 : BIT;	-- auxsc84
  SIGNAL auxsc90 : BIT;	-- auxsc90
  SIGNAL auxsc91 : BIT;	-- auxsc91
  SIGNAL auxsc92 : BIT;	-- auxsc92
  SIGNAL auxsc93 : BIT;	-- auxsc93
  SIGNAL auxsc102 : BIT;	-- auxsc102
  SIGNAL auxsc103 : BIT;	-- auxsc103
  SIGNAL auxsc109 : BIT;	-- auxsc109
  SIGNAL auxsc110 : BIT;	-- auxsc110
  SIGNAL auxsc111 : BIT;	-- auxsc111
  SIGNAL auxsc112 : BIT;	-- auxsc112
  SIGNAL auxsc121 : BIT;	-- auxsc121
  SIGNAL auxsc122 : BIT;	-- auxsc122
  SIGNAL auxsc128 : BIT;	-- auxsc128
  SIGNAL auxsc129 : BIT;	-- auxsc129
  SIGNAL auxsc130 : BIT;	-- auxsc130
  SIGNAL auxsc131 : BIT;	-- auxsc131
  SIGNAL auxsc140 : BIT;	-- auxsc140
  SIGNAL auxsc141 : BIT;	-- auxsc141
  SIGNAL auxsc147 : BIT;	-- auxsc147
  SIGNAL auxsc148 : BIT;	-- auxsc148
  SIGNAL auxsc149 : BIT;	-- auxsc149
  SIGNAL auxsc150 : BIT;	-- auxsc150
  SIGNAL auxsc159 : BIT;	-- auxsc159
  SIGNAL auxsc160 : BIT;	-- auxsc160
  SIGNAL auxsc166 : BIT;	-- auxsc166
  SIGNAL auxsc167 : BIT;	-- auxsc167
  SIGNAL auxsc168 : BIT;	-- auxsc168
  SIGNAL auxsc169 : BIT;	-- auxsc169
  SIGNAL auxsc178 : BIT;	-- auxsc178
  SIGNAL auxsc179 : BIT;	-- auxsc179
  SIGNAL auxsc185 : BIT;	-- auxsc185
  SIGNAL auxsc186 : BIT;	-- auxsc186
  SIGNAL auxsc187 : BIT;	-- auxsc187
  SIGNAL auxsc188 : BIT;	-- auxsc188
  SIGNAL auxsc197 : BIT;	-- auxsc197
  SIGNAL auxsc198 : BIT;	-- auxsc198
  SIGNAL auxsc204 : BIT;	-- auxsc204
  SIGNAL auxsc205 : BIT;	-- auxsc205
  SIGNAL auxsc206 : BIT;	-- auxsc206
  SIGNAL auxsc207 : BIT;	-- auxsc207
  SIGNAL auxsc216 : BIT;	-- auxsc216
  SIGNAL auxsc217 : BIT;	-- auxsc217
  SIGNAL auxsc223 : BIT;	-- auxsc223
  SIGNAL auxsc224 : BIT;	-- auxsc224
  SIGNAL auxsc225 : BIT;	-- auxsc225
  SIGNAL auxsc226 : BIT;	-- auxsc226
  SIGNAL auxsc235 : BIT;	-- auxsc235
  SIGNAL auxsc236 : BIT;	-- auxsc236
  SIGNAL auxsc242 : BIT;	-- auxsc242
  SIGNAL auxsc243 : BIT;	-- auxsc243
  SIGNAL auxsc244 : BIT;	-- auxsc244
  SIGNAL auxsc245 : BIT;	-- auxsc245
  SIGNAL auxsc254 : BIT;	-- auxsc254
  SIGNAL auxsc255 : BIT;	-- auxsc255
  SIGNAL auxsc5 : BIT;	-- auxsc5
  SIGNAL auxsc2 : BIT;	-- auxsc2
  SIGNAL auxsc6 : BIT;	-- auxsc6
  SIGNAL auxsc7 : BIT;	-- auxsc7
  SIGNAL auxsc18 : BIT;	-- auxsc18
  SIGNAL auxsc14 : BIT;	-- auxsc14
  SIGNAL auxsc15 : BIT;	-- auxsc15
  SIGNAL auxsc19 : BIT;	-- auxsc19
  SIGNAL auxsc20 : BIT;	-- auxsc20
  SIGNAL auxsc21 : BIT;	-- auxsc21
  SIGNAL auxsc22 : BIT;	-- auxsc22
  SIGNAL auxsc38 : BIT;	-- auxsc38
  SIGNAL auxsc39 : BIT;	-- auxsc39
  SIGNAL auxsc40 : BIT;	-- auxsc40
  SIGNAL auxsc41 : BIT;	-- auxsc41
  SIGNAL auxsc57 : BIT;	-- auxsc57
  SIGNAL auxsc58 : BIT;	-- auxsc58
  SIGNAL auxsc59 : BIT;	-- auxsc59
  SIGNAL auxsc60 : BIT;	-- auxsc60
  SIGNAL auxsc76 : BIT;	-- auxsc76
  SIGNAL auxsc77 : BIT;	-- auxsc77
  SIGNAL auxsc78 : BIT;	-- auxsc78
  SIGNAL auxsc79 : BIT;	-- auxsc79
  SIGNAL auxsc95 : BIT;	-- auxsc95
  SIGNAL auxsc96 : BIT;	-- auxsc96
  SIGNAL auxsc97 : BIT;	-- auxsc97
  SIGNAL auxsc98 : BIT;	-- auxsc98
  SIGNAL auxsc114 : BIT;	-- auxsc114
  SIGNAL auxsc115 : BIT;	-- auxsc115
  SIGNAL auxsc116 : BIT;	-- auxsc116
  SIGNAL auxsc117 : BIT;	-- auxsc117
  SIGNAL auxsc133 : BIT;	-- auxsc133
  SIGNAL auxsc134 : BIT;	-- auxsc134
  SIGNAL auxsc135 : BIT;	-- auxsc135
  SIGNAL auxsc136 : BIT;	-- auxsc136
  SIGNAL auxsc152 : BIT;	-- auxsc152
  SIGNAL auxsc153 : BIT;	-- auxsc153
  SIGNAL auxsc154 : BIT;	-- auxsc154
  SIGNAL auxsc155 : BIT;	-- auxsc155
  SIGNAL auxsc171 : BIT;	-- auxsc171
  SIGNAL auxsc172 : BIT;	-- auxsc172
  SIGNAL auxsc173 : BIT;	-- auxsc173
  SIGNAL auxsc174 : BIT;	-- auxsc174
  SIGNAL auxsc190 : BIT;	-- auxsc190
  SIGNAL auxsc191 : BIT;	-- auxsc191
  SIGNAL auxsc192 : BIT;	-- auxsc192
  SIGNAL auxsc193 : BIT;	-- auxsc193
  SIGNAL auxsc209 : BIT;	-- auxsc209
  SIGNAL auxsc210 : BIT;	-- auxsc210
  SIGNAL auxsc211 : BIT;	-- auxsc211
  SIGNAL auxsc212 : BIT;	-- auxsc212
  SIGNAL auxsc228 : BIT;	-- auxsc228
  SIGNAL auxsc229 : BIT;	-- auxsc229
  SIGNAL auxsc230 : BIT;	-- auxsc230
  SIGNAL auxsc231 : BIT;	-- auxsc231
  SIGNAL auxsc247 : BIT;	-- auxsc247
  SIGNAL auxsc248 : BIT;	-- auxsc248
  SIGNAL auxsc249 : BIT;	-- auxsc249
  SIGNAL auxsc250 : BIT;	-- auxsc250
  SIGNAL auxsc292 : BIT;	-- auxsc292
  SIGNAL auxsc273 : BIT;	-- auxsc273
  SIGNAL auxsc287 : BIT;	-- auxsc287
  SIGNAL auxsc270 : BIT;	-- auxsc270
  SIGNAL auxsc283 : BIT;	-- auxsc283
  SIGNAL auxsc288 : BIT;	-- auxsc288
  SIGNAL auxsc279 : BIT;	-- auxsc279
  SIGNAL auxsc278 : BIT;	-- auxsc278
  SIGNAL auxsc281 : BIT;	-- auxsc281
  SIGNAL auxsc289 : BIT;	-- auxsc289
  SIGNAL auxsc291 : BIT;	-- auxsc291
  SIGNAL auxsc293 : BIT;	-- auxsc293
  SIGNAL auxsc294 : BIT;	-- auxsc294
  SIGNAL auxsc285 : BIT;	-- auxsc285
  SIGNAL auxsc286 : BIT;	-- auxsc286
  SIGNAL auxsc295 : BIT;	-- auxsc295
  SIGNAL auxsc297 : BIT;	-- auxsc297
  SIGNAL auxsc298 : BIT;	-- auxsc298
  SIGNAL auxsc339 : BIT;	-- auxsc339
  SIGNAL auxsc318 : BIT;	-- auxsc318
  SIGNAL auxsc302 : BIT;	-- auxsc302
  SIGNAL auxsc303 : BIT;	-- auxsc303
  SIGNAL auxsc331 : BIT;	-- auxsc331
  SIGNAL auxsc335 : BIT;	-- auxsc335
  SIGNAL auxsc327 : BIT;	-- auxsc327
  SIGNAL auxsc326 : BIT;	-- auxsc326
  SIGNAL auxsc329 : BIT;	-- auxsc329
  SIGNAL auxsc336 : BIT;	-- auxsc336
  SIGNAL auxsc338 : BIT;	-- auxsc338
  SIGNAL auxsc340 : BIT;	-- auxsc340
  SIGNAL auxsc341 : BIT;	-- auxsc341
  SIGNAL auxsc333 : BIT;	-- auxsc333
  SIGNAL auxsc334 : BIT;	-- auxsc334
  SIGNAL auxsc342 : BIT;	-- auxsc342
  SIGNAL auxsc344 : BIT;	-- auxsc344
  SIGNAL auxsc345 : BIT;	-- auxsc345

BEGIN

  auxsc345 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc345,
    i2 => auxsc344,
    i1 => auxsc338,
    i0 => auxsc339);
  auxsc344 : o4_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc344,
    i3 => auxsc342,
    i2 => auxsc341,
    i1 => auxsc340,
    i0 => auxsc18);
  auxsc342 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc342,
    i1 => auxsc334,
    i0 => auxsc333);
  auxsc334 : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc334,
    i1 => auxsc327,
    i0 => auxsc326);
  auxsc333 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc333,
    i1 => auxsc318,
    i0 => clr);
  auxsc341 : ao2o22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc341,
    i3 => auxsc326,
    i2 => auxsc327,
    i1 => clr,
    i0 => outs(15));
  auxsc340 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc340,
    i => auxsc339);
  auxsc338 : a3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc338,
    i2 => auxsc336,
    i1 => auxsc335,
    i0 => auxsc287);
  auxsc336 : o3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc336,
    i2 => auxsc329,
    i1 => clr,
    i0 => outs(15));
  auxsc329 : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc329,
    i1 => auxsc326,
    i0 => auxsc327);
  auxsc326 : ao22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc326,
    i2 => rtlcarry_0_14,
    i1 => int_result(14),
    i0 => outs(14));
  auxsc327 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc327,
    i1 => int_result(14),
    i0 => outs(14));
  auxsc335 : o3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc335,
    i2 => auxsc331,
    i1 => auxsc318,
    i0 => clr);
  auxsc331 : noa22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc331,
    i2 => auxsc303,
    i1 => auxsc302,
    i0 => auxsc286);
  auxsc303 : an12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc303,
    i1 => int_result(14),
    i0 => auxsc270);
  auxsc302 : on12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc302,
    i1 => int_result(14),
    i0 => auxsc270);
  auxsc318 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc318,
    i => outs(15));
  auxsc339 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc339,
    i => int_result(15));
  auxsc298 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc298,
    i2 => auxsc297,
    i1 => auxsc291,
    i0 => auxsc292);
  auxsc297 : o4_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc297,
    i3 => auxsc295,
    i2 => auxsc294,
    i1 => auxsc293,
    i0 => auxsc18);
  auxsc295 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc295,
    i1 => auxsc286,
    i0 => auxsc285);
  auxsc286 : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc286,
    i1 => auxsc279,
    i0 => auxsc278);
  auxsc285 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc285,
    i1 => auxsc270,
    i0 => clr);
  auxsc294 : ao2o22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc294,
    i3 => auxsc278,
    i2 => auxsc279,
    i1 => clr,
    i0 => outs(14));
  auxsc293 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc293,
    i => auxsc292);
  auxsc291 : a3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc291,
    i2 => auxsc289,
    i1 => auxsc288,
    i0 => auxsc287);
  auxsc289 : o3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc289,
    i2 => auxsc281,
    i1 => clr,
    i0 => outs(14));
  auxsc281 : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc281,
    i1 => auxsc278,
    i0 => auxsc279);
  auxsc278 : ao22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc278,
    i2 => rtlcarry_0_13,
    i1 => int_result(13),
    i0 => outs(13));
  auxsc279 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc279,
    i1 => int_result(13),
    i0 => outs(13));
  auxsc288 : o3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc288,
    i2 => auxsc283,
    i1 => auxsc270,
    i0 => clr);
  auxsc283 : noa22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc283,
    i2 => auxsc255,
    i1 => auxsc254,
    i0 => auxsc244);
  auxsc270 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc270,
    i => outs(14));
  auxsc287 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc287,
    i1 => auxsc273,
    i0 => auxsc18);
  auxsc273 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc273,
    i => clr);
  auxsc292 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc292,
    i => int_result(14));
  auxsc250 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc250,
    i1 => auxsc249,
    i0 => clr);
  auxsc249 : nxr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc249,
    i1 => auxsc248,
    i0 => int_result(13));
  auxsc248 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc248,
    i1 => auxsc247,
    i0 => auxsc18);
  auxsc247 : xr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc247,
    i1 => auxsc244,
    i0 => auxsc245);
  auxsc231 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc231,
    i1 => auxsc230,
    i0 => clr);
  auxsc230 : nxr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc230,
    i1 => auxsc229,
    i0 => int_result(12));
  auxsc229 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc229,
    i1 => auxsc228,
    i0 => auxsc18);
  auxsc228 : xr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc228,
    i1 => auxsc225,
    i0 => auxsc226);
  auxsc212 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc212,
    i1 => auxsc211,
    i0 => clr);
  auxsc211 : nxr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc211,
    i1 => auxsc210,
    i0 => int_result(11));
  auxsc210 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc210,
    i1 => auxsc209,
    i0 => auxsc18);
  auxsc209 : xr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc209,
    i1 => auxsc206,
    i0 => auxsc207);
  auxsc193 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc193,
    i1 => auxsc192,
    i0 => clr);
  auxsc192 : nxr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc192,
    i1 => auxsc191,
    i0 => int_result(10));
  auxsc191 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc191,
    i1 => auxsc190,
    i0 => auxsc18);
  auxsc190 : xr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc190,
    i1 => auxsc187,
    i0 => auxsc188);
  auxsc174 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc174,
    i1 => auxsc173,
    i0 => clr);
  auxsc173 : nxr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc173,
    i1 => auxsc172,
    i0 => int_result(9));
  auxsc172 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc172,
    i1 => auxsc171,
    i0 => auxsc18);
  auxsc171 : xr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc171,
    i1 => auxsc168,
    i0 => auxsc169);
  auxsc155 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc155,
    i1 => auxsc154,
    i0 => clr);
  auxsc154 : nxr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc154,
    i1 => auxsc153,
    i0 => int_result(8));
  auxsc153 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc153,
    i1 => auxsc152,
    i0 => auxsc18);
  auxsc152 : xr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc152,
    i1 => auxsc149,
    i0 => auxsc150);
  auxsc136 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc136,
    i1 => auxsc135,
    i0 => clr);
  auxsc135 : nxr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc135,
    i1 => auxsc134,
    i0 => int_result(7));
  auxsc134 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc134,
    i1 => auxsc133,
    i0 => auxsc18);
  auxsc133 : xr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc133,
    i1 => auxsc130,
    i0 => auxsc131);
  auxsc117 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc117,
    i1 => auxsc116,
    i0 => clr);
  auxsc116 : nxr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc116,
    i1 => auxsc115,
    i0 => int_result(6));
  auxsc115 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc115,
    i1 => auxsc114,
    i0 => auxsc18);
  auxsc114 : xr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc114,
    i1 => auxsc111,
    i0 => auxsc112);
  auxsc98 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc98,
    i1 => auxsc97,
    i0 => clr);
  auxsc97 : nxr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc97,
    i1 => auxsc96,
    i0 => int_result(5));
  auxsc96 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc96,
    i1 => auxsc95,
    i0 => auxsc18);
  auxsc95 : xr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc95,
    i1 => auxsc92,
    i0 => auxsc93);
  auxsc79 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc79,
    i1 => auxsc78,
    i0 => clr);
  auxsc78 : nxr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc78,
    i1 => auxsc77,
    i0 => int_result(4));
  auxsc77 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc77,
    i1 => auxsc76,
    i0 => auxsc18);
  auxsc76 : xr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc76,
    i1 => auxsc73,
    i0 => auxsc74);
  auxsc60 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc60,
    i1 => auxsc59,
    i0 => clr);
  auxsc59 : nxr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc59,
    i1 => auxsc58,
    i0 => int_result(3));
  auxsc58 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc58,
    i1 => auxsc57,
    i0 => auxsc18);
  auxsc57 : xr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc57,
    i1 => auxsc54,
    i0 => auxsc55);
  auxsc41 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc41,
    i1 => auxsc40,
    i0 => clr);
  auxsc40 : nxr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc40,
    i1 => auxsc39,
    i0 => int_result(2));
  auxsc39 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc39,
    i1 => auxsc38,
    i0 => auxsc18);
  auxsc38 : xr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc38,
    i1 => auxsc35,
    i0 => auxsc36);
  auxsc22 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc22,
    i1 => auxsc21,
    i0 => clr);
  auxsc21 : nxr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc21,
    i1 => auxsc20,
    i0 => int_result(1));
  auxsc20 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc20,
    i1 => auxsc19,
    i0 => auxsc18);
  auxsc19 : xr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc19,
    i1 => auxsc15,
    i0 => auxsc16);
  auxsc15 : an12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc15,
    i1 => int_result(0),
    i0 => auxsc14);
  auxsc14 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc14,
    i => outs(0));
  auxsc18 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc18,
    i => ld);
  auxsc7 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc7,
    i1 => auxsc6,
    i0 => clr);
  auxsc6 : nxr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc6,
    i1 => auxsc2,
    i0 => int_result(0));
  auxsc2 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc2,
    i1 => ld,
    i0 => outs(0));
  auxsc5 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc5,
    i => clk);
  auxsc255 : an12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc255,
    i1 => int_result(13),
    i0 => auxsc245);
  auxsc254 : on12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc254,
    i1 => int_result(13),
    i0 => auxsc245);
  auxsc245 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc245,
    i => outs(13));
  auxsc244 : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc244,
    i1 => auxsc243,
    i0 => auxsc242);
  auxsc243 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc243,
    i1 => int_result(12),
    i0 => outs(12));
  auxsc242 : ao22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc242,
    i2 => rtlcarry_0_12,
    i1 => int_result(12),
    i0 => outs(12));
  auxsc236 : an12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc236,
    i1 => int_result(12),
    i0 => auxsc226);
  auxsc235 : on12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc235,
    i1 => int_result(12),
    i0 => auxsc226);
  auxsc226 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc226,
    i => outs(12));
  auxsc225 : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc225,
    i1 => auxsc224,
    i0 => auxsc223);
  auxsc224 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc224,
    i1 => int_result(11),
    i0 => outs(11));
  auxsc223 : ao22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc223,
    i2 => rtlcarry_0_11,
    i1 => int_result(11),
    i0 => outs(11));
  auxsc217 : an12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc217,
    i1 => int_result(11),
    i0 => auxsc207);
  auxsc216 : on12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc216,
    i1 => int_result(11),
    i0 => auxsc207);
  auxsc207 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc207,
    i => outs(11));
  auxsc206 : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc206,
    i1 => auxsc205,
    i0 => auxsc204);
  auxsc205 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc205,
    i1 => int_result(10),
    i0 => outs(10));
  auxsc204 : ao22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc204,
    i2 => rtlcarry_0_10,
    i1 => int_result(10),
    i0 => outs(10));
  auxsc198 : an12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc198,
    i1 => int_result(10),
    i0 => auxsc188);
  auxsc197 : on12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc197,
    i1 => int_result(10),
    i0 => auxsc188);
  auxsc188 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc188,
    i => outs(10));
  auxsc187 : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc187,
    i1 => auxsc186,
    i0 => auxsc185);
  auxsc186 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc186,
    i1 => int_result(9),
    i0 => outs(9));
  auxsc185 : ao22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc185,
    i2 => rtlcarry_0_9,
    i1 => int_result(9),
    i0 => outs(9));
  auxsc179 : an12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc179,
    i1 => int_result(9),
    i0 => auxsc169);
  auxsc178 : on12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc178,
    i1 => int_result(9),
    i0 => auxsc169);
  auxsc169 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc169,
    i => outs(9));
  auxsc168 : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc168,
    i1 => auxsc167,
    i0 => auxsc166);
  auxsc167 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc167,
    i1 => int_result(8),
    i0 => outs(8));
  auxsc166 : ao22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc166,
    i2 => rtlcarry_0_8,
    i1 => int_result(8),
    i0 => outs(8));
  auxsc160 : an12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc160,
    i1 => int_result(8),
    i0 => auxsc150);
  auxsc159 : on12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc159,
    i1 => int_result(8),
    i0 => auxsc150);
  auxsc150 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc150,
    i => outs(8));
  auxsc149 : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc149,
    i1 => auxsc148,
    i0 => auxsc147);
  auxsc148 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc148,
    i1 => int_result(7),
    i0 => outs(7));
  auxsc147 : ao22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc147,
    i2 => rtlcarry_0_7,
    i1 => int_result(7),
    i0 => outs(7));
  auxsc141 : an12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc141,
    i1 => int_result(7),
    i0 => auxsc131);
  auxsc140 : on12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc140,
    i1 => int_result(7),
    i0 => auxsc131);
  auxsc131 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc131,
    i => outs(7));
  auxsc130 : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc130,
    i1 => auxsc129,
    i0 => auxsc128);
  auxsc129 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc129,
    i1 => int_result(6),
    i0 => outs(6));
  auxsc128 : ao22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc128,
    i2 => rtlcarry_0_6,
    i1 => int_result(6),
    i0 => outs(6));
  auxsc122 : an12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc122,
    i1 => int_result(6),
    i0 => auxsc112);
  auxsc121 : on12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc121,
    i1 => int_result(6),
    i0 => auxsc112);
  auxsc112 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc112,
    i => outs(6));
  auxsc111 : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc111,
    i1 => auxsc110,
    i0 => auxsc109);
  auxsc110 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc110,
    i1 => int_result(5),
    i0 => outs(5));
  auxsc109 : ao22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc109,
    i2 => rtlcarry_0_5,
    i1 => int_result(5),
    i0 => outs(5));
  auxsc103 : an12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc103,
    i1 => int_result(5),
    i0 => auxsc93);
  auxsc102 : on12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc102,
    i1 => int_result(5),
    i0 => auxsc93);
  auxsc93 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc93,
    i => outs(5));
  auxsc92 : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc92,
    i1 => auxsc91,
    i0 => auxsc90);
  auxsc91 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc91,
    i1 => int_result(4),
    i0 => outs(4));
  auxsc90 : ao22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc90,
    i2 => rtlcarry_0_4,
    i1 => int_result(4),
    i0 => outs(4));
  auxsc84 : an12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc84,
    i1 => int_result(4),
    i0 => auxsc74);
  auxsc83 : on12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc83,
    i1 => int_result(4),
    i0 => auxsc74);
  auxsc74 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc74,
    i => outs(4));
  auxsc73 : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc73,
    i1 => auxsc72,
    i0 => auxsc71);
  auxsc72 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc72,
    i1 => int_result(3),
    i0 => outs(3));
  auxsc71 : ao22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc71,
    i2 => rtlcarry_0_3,
    i1 => int_result(3),
    i0 => outs(3));
  auxsc65 : an12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc65,
    i1 => int_result(3),
    i0 => auxsc55);
  auxsc64 : on12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc64,
    i1 => int_result(3),
    i0 => auxsc55);
  auxsc55 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc55,
    i => outs(3));
  auxsc54 : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc54,
    i1 => auxsc53,
    i0 => auxsc52);
  auxsc53 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc53,
    i1 => int_result(2),
    i0 => outs(2));
  auxsc52 : ao22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc52,
    i2 => rtlcarry_0_2,
    i1 => int_result(2),
    i0 => outs(2));
  auxsc46 : an12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc46,
    i1 => int_result(2),
    i0 => auxsc36);
  auxsc45 : on12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc45,
    i1 => int_result(2),
    i0 => auxsc36);
  auxsc36 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc36,
    i => outs(2));
  auxsc35 : oa2a22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc35,
    i3 => auxsc34,
    i2 => auxsc27,
    i1 => int_result(1),
    i0 => outs(1));
  auxsc34 : on12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc34,
    i1 => int_result(1),
    i0 => auxsc16);
  auxsc28 : an12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc28,
    i1 => int_result(1),
    i0 => auxsc16);
  auxsc16 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc16,
    i => outs(1));
  auxsc24 : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc24,
    i1 => int_result(1),
    i0 => outs(1));
  auxsc27 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc27,
    i1 => int_result(0),
    i0 => outs(0));
  rtlcarry_0_2 : oa22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => rtlcarry_0_2,
    i2 => auxsc28,
    i1 => auxsc24,
    i0 => auxsc27);
  rtlcarry_0_3 : oa22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => rtlcarry_0_3,
    i2 => auxsc46,
    i1 => auxsc45,
    i0 => auxsc35);
  rtlcarry_0_4 : oa22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => rtlcarry_0_4,
    i2 => auxsc65,
    i1 => auxsc64,
    i0 => auxsc54);
  rtlcarry_0_5 : oa22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => rtlcarry_0_5,
    i2 => auxsc84,
    i1 => auxsc83,
    i0 => auxsc73);
  rtlcarry_0_6 : oa22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => rtlcarry_0_6,
    i2 => auxsc103,
    i1 => auxsc102,
    i0 => auxsc92);
  rtlcarry_0_7 : oa22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => rtlcarry_0_7,
    i2 => auxsc122,
    i1 => auxsc121,
    i0 => auxsc111);
  rtlcarry_0_8 : oa22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => rtlcarry_0_8,
    i2 => auxsc141,
    i1 => auxsc140,
    i0 => auxsc130);
  rtlcarry_0_9 : oa22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => rtlcarry_0_9,
    i2 => auxsc160,
    i1 => auxsc159,
    i0 => auxsc149);
  rtlcarry_0_10 : oa22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => rtlcarry_0_10,
    i2 => auxsc179,
    i1 => auxsc178,
    i0 => auxsc168);
  rtlcarry_0_11 : oa22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => rtlcarry_0_11,
    i2 => auxsc198,
    i1 => auxsc197,
    i0 => auxsc187);
  rtlcarry_0_12 : oa22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => rtlcarry_0_12,
    i2 => auxsc217,
    i1 => auxsc216,
    i0 => auxsc206);
  rtlcarry_0_13 : oa22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => rtlcarry_0_13,
    i2 => auxsc236,
    i1 => auxsc235,
    i0 => auxsc225);
  rtlcarry_0_14 : oa22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => rtlcarry_0_14,
    i2 => auxsc255,
    i1 => auxsc254,
    i0 => auxsc244);
  int_resultint_0 : sff1_x4
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => int_result(0),
    i => auxsc7,
    ck => auxsc5);
  int_resultint_1 : sff1_x4
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => int_result(1),
    i => auxsc22,
    ck => auxsc5);
  int_resultint_2 : sff1_x4
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => int_result(2),
    i => auxsc41,
    ck => auxsc5);
  int_resultint_3 : sff1_x4
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => int_result(3),
    i => auxsc60,
    ck => auxsc5);
  int_resultint_4 : sff1_x4
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => int_result(4),
    i => auxsc79,
    ck => auxsc5);
  int_resultint_5 : sff1_x4
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => int_result(5),
    i => auxsc98,
    ck => auxsc5);
  int_resultint_6 : sff1_x4
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => int_result(6),
    i => auxsc117,
    ck => auxsc5);
  int_resultint_7 : sff1_x4
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => int_result(7),
    i => auxsc136,
    ck => auxsc5);
  int_resultint_8 : sff1_x4
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => int_result(8),
    i => auxsc155,
    ck => auxsc5);
  int_resultint_9 : sff1_x4
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => int_result(9),
    i => auxsc174,
    ck => auxsc5);
  int_resultint_10 : sff1_x4
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => int_result(10),
    i => auxsc193,
    ck => auxsc5);
  int_resultint_11 : sff1_x4
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => int_result(11),
    i => auxsc212,
    ck => auxsc5);
  int_resultint_12 : sff1_x4
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => int_result(12),
    i => auxsc231,
    ck => auxsc5);
  int_resultint_13 : sff1_x4
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => int_result(13),
    i => auxsc250,
    ck => auxsc5);
  int_resultint_14 : sff1_x4
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => int_result(14),
    i => auxsc298,
    ck => auxsc5);
  int_resultint_15 : sff1_x4
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => int_result(15),
    i => auxsc345,
    ck => auxsc5);
  patch_0 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => result(0),
    i => int_result(0));
  patch_1 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => result(1),
    i => int_result(1));
  patch_2 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => result(2),
    i => int_result(2));
  patch_3 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => result(3),
    i => int_result(3));
  patch_4 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => result(4),
    i => int_result(4));
  patch_5 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => result(5),
    i => int_result(5));
  patch_6 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => result(6),
    i => int_result(6));
  patch_7 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => result(7),
    i => int_result(7));
  patch_8 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => result(8),
    i => int_result(8));
  patch_9 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => result(9),
    i => int_result(9));
  patch_10 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => result(10),
    i => int_result(10));
  patch_11 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => result(11),
    i => int_result(11));
  patch_12 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => result(12),
    i => int_result(12));
  patch_13 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => result(13),
    i => int_result(13));
  patch_14 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => result(14),
    i => int_result(14));
  patch_15 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => result(15),
    i => int_result(15));

end VST;