Nouveau "tutorial" pour VASY
This commit is contained in:
The Syf Tool
parent
2c763fd077
commit
9c9b09b1f4
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@ -0,0 +1,2 @@
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rm CATAL Makefile calcul.vhdl compteur.vhdl ex0.stim ex1.stim ex2.stim ex3.stim hadamard hadamard.stim hadamard.vhdl hadamard_1.pat hadamard_2.pat hadamard_3.pat hadamard_tb.vhdl ram.vhdl rom.vhdl sequenceur.vhdl
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cvs remove CATAL Makefile calcul.vhdl compteur.vhdl ex0.stim ex1.stim ex2.stim ex3.stim hadamard hadamard.stim hadamard.vhdl hadamard_1.pat hadamard_2.pat hadamard_3.pat hadamard_tb.vhdl ram.vhdl rom.vhdl sequenceur.vhdl
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@ -51,7 +51,8 @@ include $(ALLIANCE_TOP)/etc/libraries.mk
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# | |
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# \------------------------------------------------------------*/
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VASY = $(ALLIANCE_TOP)/bin/vasy
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# VASY = $(ALLIANCE_TOP)/bin/vasy
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VASY = $(HOME)/dev/bin/SunOS/vasy
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ASIMUT = $(ALLIANCE_TOP)/bin/asimut
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# /*------------------------------------------------------------\
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@ -90,7 +91,7 @@ result_3.pat : hadamard.vst
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# \------------------------------------------------------------*/
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hadamard.vst : hadamard.vhdl
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$(ENV_VASY); $(VASY) -a -I vhdl -H hadamard
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$(ENV_VASY); $(VASY) -a -o -I vhdl -H hadamard
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# /*------------------------------------------------------------\
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@ -0,0 +1,5 @@
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addaccu C
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multi8_model C
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srb C
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controller C
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sra C
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@ -0,0 +1,257 @@
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# /*------------------------------------------------------------\
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# | |
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# | This file is part of the Alliance CAD System Copyright |
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# | (C) Laboratoire LIP6 - Département ASIM Universite P&M Curie|
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# | |
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# | Home page : http://www-asim.lip6.fr/alliance/ |
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# | E-mail support : mailto:alliance-support@asim.lip6.fr |
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# | |
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# | This progam is free software; you can redistribute it |
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# | and/or modify it under the terms of the GNU General Public |
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# | License as published by the Free Software Foundation; |
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# | either version 2 of the License, or (at your option) any |
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# | later version. |
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# | |
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# | Alliance VLSI CAD System is distributed in the hope that |
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# | it will be useful, but WITHOUT ANY WARRANTY; |
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# | without even the implied warranty of MERCHANTABILITY or |
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# | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General |
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# | Public License for more details. |
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# | |
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# | You should have received a copy of the GNU General Public |
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# | License along with the GNU C Library; see the file COPYING. |
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# | If not, write to the Free Software Foundation, Inc., |
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# | 675 Mass Ave, Cambridge, MA 02139, USA. |
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# | |
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# \------------------------------------------------------------*/
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# /*------------------------------------------------------------\
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# | |
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# | Tool : VASY |
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# | |
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# | File : Makefile |
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# | |
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# | Author : Jacomme Ludovic |
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# | |
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# | Date : 30_05_2000 |
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# | |
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# \------------------------------------------------------------*/
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include $(ALLIANCE_TOP)/etc/$(ALLIANCE_OS).mk
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include $(ALLIANCE_TOP)/etc/libraries.mk
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# /*------------------------------------------------------------\
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# | |
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# | Cells |
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# | |
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# \------------------------------------------------------------*/
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# /*------------------------------------------------------------\
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# | |
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# | Binary |
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# | |
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# \------------------------------------------------------------*/
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TOUCH = touch
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VASY = $(ALLIANCE_TOP)/bin/vasy
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ASIMUT = $(ALLIANCE_TOP)/bin/asimut
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BOP = $(ALLIANCE_TOP)/bin/bop
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SCMAP = $(ALLIANCE_TOP)/bin/scmap
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PROOF = $(ALLIANCE_TOP)/bin/proof
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SCR = $(ALLIANCE_TOP)/bin/scr
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LYNX = $(ALLIANCE_TOP)/bin/lynx
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LVX = $(ALLIANCE_TOP)/bin/lvx
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DRUC = $(ALLIANCE_TOP)/bin/druc
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# /*------------------------------------------------------------\
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# | |
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# | Environement |
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# | |
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# \------------------------------------------------------------*/
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ENV_VASY = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
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MBK_CATAL_NAME=NO_CATAL; export MBK_CATAL_NAME
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ENV_ASIMUT = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME;\
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MBK_IN_LO=vst; export MBK_IN_LO;\
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MBK_OUT_LO=vst; export MBK_OUT_LO
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ENV_SIMU_VBE = MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib; export MBK_CATA_LIB;\
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MBK_WORK_LIB=.; export MBK_WORK_LIB;\
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MBK_CATAL_NAME=CATAL_VBE; export MBK_CATAL_NAME;\
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MBK_IN_LO=vst; export MBK_IN_LO;\
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MBK_OUT_LO=vst; export MBK_OUT_LO
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ENV_SIMU_VST = MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib; export MBK_CATA_LIB;\
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MBK_WORK_LIB=.; export MBK_WORK_LIB;\
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MBK_CATAL_NAME=NO_CATAL; export MBK_CATAL_NAME;\
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MBK_IN_LO=vst; export MBK_IN_LO;\
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MBK_OUT_LO=vst; export MBK_OUT_LO
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ENV_SYNTH = MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib; export MBK_CATA_LIB;\
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MBK_TARGET_LIB=$(ALLIANCE_TOP)/cells/sxlib; export MBK_TARGET_LIB;\
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MBK_WORK_LIB=.; export MBK_WORK_LIB;\
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MBK_CATAL_NAME=CATAL_VBE; export MBK_CATAL_NAME;\
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MBK_IN_LO=vst; export MBK_IN_LO;\
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MBK_OUT_LO=vst; export MBK_OUT_LO
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ENV_ROUTE = MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib; export MBK_CATA_LIB;\
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MBK_WORK_LIB=.; export MBK_WORK_LIB;\
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MBK_CATAL_NAME=NO_CATAL; export MBK_CATAL_NAME;\
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MBK_IN_PH=ap; export MBK_IN_PH;\
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MBK_OUT_PH=ap; export MBK_OUT_PH;\
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MBK_IN_LO=vst; export MBK_IN_LO;\
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MBK_OUT_LO=al; export MBK_OUT_LO
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ENV_PHYS = MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib; export MBK_CATA_LIB;\
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MBK_WORK_LIB=.; export MBK_WORK_LIB;\
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MBK_CATAL_NAME=NO_CATAL; export MBK_CATAL_NAME;\
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RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/cmos_11.rds; \
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export RDS_TECHNO_NAME;\
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RDS_IN=cif; export RDS_IN;\
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RDS_OUT=cif; export RDS_OUT;\
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MBK_IN_PH=ap; export MBK_IN_PH;\
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MBK_OUT_PH=ap; export MBK_OUT_PH;\
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MBK_IN_LO=al; export MBK_IN_LO;\
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MBK_OUT_LO=al; export MBK_OUT_LO
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all : multi8_drc
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# /*------------------------------------------------------------\
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# | |
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# | Vasy |
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# | |
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# \------------------------------------------------------------*/
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multi8.vst : addaccu.vhdl controller.vhdl multi8.vhdl sra.vhdl srb.vhdl
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$(ENV_VASY); $(VASY) -a -o -I vhdl -HLpV multi8
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# /*------------------------------------------------------------\
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# | |
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# | Behavioral Simulation |
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# | |
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# \------------------------------------------------------------*/
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result_beh_pat : multi8.vst
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$(ENV_ASIMUT); $(ASIMUT) multi8 multi8 result_beh
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$(TOUCH) result_beh_pat
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# /*------------------------------------------------------------\
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# | |
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# | Boolean Optimization |
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# | |
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# \------------------------------------------------------------*/
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srao_vbe : result_beh_pat
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$(ENV_SYNTH); $(BOP) -o sra srao
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$(ENV_SYNTH); $(PROOF) sra srao
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$(TOUCH) srao_vbe
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srbo_vbe : result_beh_pat
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$(ENV_SYNTH); $(BOP) -o srb srbo
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$(ENV_SYNTH); $(PROOF) srb srbo
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$(TOUCH) srbo_vbe
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addaccuo_vbe : result_beh_pat
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$(ENV_SYNTH); $(BOP) -o addaccu addaccuo addaccu
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$(ENV_SYNTH); $(PROOF) addaccu addaccuo
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$(TOUCH) addaccuo_vbe
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controllero_vbe : result_beh_pat
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$(ENV_SYNTH); $(BOP) -o controller controllero
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$(ENV_SYNTH); $(PROOF) controller controllero
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$(TOUCH) controllero_vbe
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multi8_modelo_vbe : result_beh_pat
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$(ENV_SYNTH); $(BOP) -o multi8_model multi8_modelo
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$(ENV_SYNTH); $(PROOF) multi8_model multi8_modelo
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$(TOUCH) multi8_modelo_vbe
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# /*------------------------------------------------------------\
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# | |
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# | Mapping |
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# | |
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# \------------------------------------------------------------*/
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sra.vst : srao_vbe
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$(ENV_SYNTH); $(SCMAP) srao sra
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srb.vst : srbo_vbe
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$(ENV_SYNTH); $(SCMAP) srbo srb
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addaccu.vst : addaccuo_vbe
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# $(ENV_SYNTH); $(SCMAP) addaccuo addaccu
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echo Bug with SCMAP just make a copy
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cp addaccu.vst.patched addaccu.vst
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$(TOUCH) addaccu.vst
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controller.vst : controllero_vbe
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$(ENV_SYNTH); $(SCMAP) controllero controller
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multi8_model.vst : multi8_modelo_vbe
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$(ENV_SYNTH); $(SCMAP) multi8_modelo multi8_model
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# /*------------------------------------------------------------\
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# | |
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# | Structural Simulation |
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# | |
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# \------------------------------------------------------------*/
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result_vst_pat : addaccu.vst controller.vst multi8.vst multi8_model.vst \
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sra.vst srb.vst
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$(ENV_SIMU_VST); $(ASIMUT) -zd multi8 multi8 result_vst
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$(TOUCH) result_vst_pat
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# /*------------------------------------------------------------\
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# | |
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# | Place And Route |
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# | |
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# \------------------------------------------------------------*/
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multi8.ap : result_vst_pat
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$(ENV_ROUTE); $(SCR) -p -r -i 1000 multi8 multi8
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# /*------------------------------------------------------------\
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# | |
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# | Extract |
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# | |
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# \------------------------------------------------------------*/
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multi8.al : multi8.ap
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$(ENV_PHYS); $(LYNX) -v multi8 multi8
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# /*------------------------------------------------------------\
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# | |
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# | NetList Comparison |
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# | |
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# \------------------------------------------------------------*/
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multi8_lvx : multi8.al
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$(ENV_PHYS); $(LVX) vst al multi8 multi8 -f
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$(TOUCH) multi8_lvx
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# /*------------------------------------------------------------\
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# | |
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# | Design Rules Check |
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# | |
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# \------------------------------------------------------------*/
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multi8_drc : multi8_lvx
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$(ENV_PHYS); $(DRUC) multi8
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$(TOUCH) multi8_drc
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# /*------------------------------------------------------------\
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# | |
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# | Clean |
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# | |
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# \------------------------------------------------------------*/
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realclean : clean
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clean :
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$(RM) -f *vst *vbe result_vst.pat result_beh.pat
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$(RM) -f result_vst_pat result_beh_pat multi8_drc multi8_lvx
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$(RM) -f *.al *.ap *.lax *.drc *.cif
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@ -0,0 +1,34 @@
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_arith.ALL;
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use IEEE.STD_LOGIC_unsigned.ALL;
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entity AddAccu is
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port ( CLR : in Std_Logic;
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LD : in Std_Logic;
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OUTS : in Std_Logic_Vector(15 downto 0) ;
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CLK : in Std_Logic;
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RESULT : out Std_Logic_Vector(15 downto 0) );
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end AddAccu;
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----------------------------------------------------------------------
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architecture DataFlow OF AddAccu is
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signal resultint : Std_Logic_Vector(15 downto 0) ;
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begin
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process (CLK)
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begin
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if CLK'event and CLK='0' then
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if CLR = '1' then resultint <= ( others => '0' );
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elsif LD = '1' then resultint <= resultint + OUTS;
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end if;
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end if;
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end process;
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RESULT <= resultint;
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end DataFlow;
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----------------------------------------------------------------------
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,59 @@
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity Controller is
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port (STB, CLK, LSB, Done, RST: in STD_LOGIC;
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Init, Shift, Add: out STD_LOGIC);
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end Controller;
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---------------------------------------------------
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architecture FSM of Controller is
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type States is (EndS,InitS, CheckS, AddS, ShiftS);
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signal State: States ;
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begin
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-- Drive control outputs based upon State
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Init <= '1' when State = InitS else '0';
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Add <= '1' when State = AddS else '0';
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Shift <= '1' when State = ShiftS else '0';
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-- Determine Next State from control inputs
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StateMachine:
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process (CLK)
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begin
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--compass stateMachine adj State
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if CLK'Event and CLK = '0' then
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if RST = '1' then State <= EndS;
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else
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case State is
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when InitS =>
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State <= CheckS;
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when CheckS =>
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if LSB = '1' then
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State <= AddS;
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elsif Done = '0' then
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State <= ShiftS;
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else
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State <= EndS;
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end if;
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when AddS =>
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State <= ShiftS;
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when ShiftS =>
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State <= CheckS;
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when EndS =>
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if STB = '1' then
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State <= InitS;
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end if;
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end case;
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end if;
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end if;
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end process;
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end FSM;
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---------------------------------------------------
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@ -0,0 +1,16 @@
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wave CLK
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wave RST
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wave STB
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wave DONE
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wave -dec A
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wave -dec B
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wave -dec RESULT
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force clk 1 50 , 0 100 -repeat 100
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force RST 1
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run
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force RST 0
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force STB 1
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force A 10#123
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force B 10#12
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run
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@ -0,0 +1,91 @@
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trace /MULTI8/U3/STATE
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cd MULTI8
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trace A
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trace B
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trace CLK
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trace RST
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trace STB
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trace RESULT
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trace DONE
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assign ("00000111") A
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assign ("00000011") B
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assign ('1') RST
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assign ('0') CLK
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run 50
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assign ('1') CLK
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run 50
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assign ('0') CLK
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run 50
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assign ('0') RST
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assign ('1') STB
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run 50
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assign ('1') CLK
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run 50
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assign ('0') CLK
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run 50
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run 50
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assign ('1') CLK
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run 50
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assign ('0') CLK
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run 50
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assign ('1') CLK
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run 50
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assign ('0') CLK
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run 50
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assign ('1') CLK
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run 50
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assign ('0') CLK
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run 50
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assign ('1') CLK
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run 50
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assign ('0') CLK
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run 50
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assign ('1') CLK
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run 50
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assign ('0') CLK
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run 50
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assign ('1') CLK
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run 50
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assign ('0') CLK
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run 50
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assign ('1') CLK
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run 50
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assign ('0') CLK
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run 50
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assign ('1') CLK
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run 50
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assign ('0') CLK
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run 50
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assign ('1') CLK
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run 50
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assign ('0') CLK
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run 50
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assign ('1') CLK
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run 50
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assign ('0') CLK
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run 50
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assign ('1') CLK
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run 50
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assign ('0') CLK
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run 50
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assign ('1') CLK
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run 50
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assign ('0') CLK
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run 50
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@ -0,0 +1,51 @@
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|||
-- input / output list :
|
||||
|
||||
in clk B;;
|
||||
in rst B;;
|
||||
in stb B;;
|
||||
in a (7 downto 0) X;;
|
||||
in b (7 downto 0) X;;
|
||||
out result (15 downto 0) X;;
|
||||
out done B;
|
||||
|
||||
begin
|
||||
|
||||
-- Pattern description :
|
||||
|
||||
-- C R S A B R D
|
||||
-- L S T E O
|
||||
-- K T B S N
|
||||
-- U E
|
||||
-- L
|
||||
-- T
|
||||
|
||||
: 0 1 0 00 00 ?**** ?u;
|
||||
: 1 1 0 00 00 ?**** ?u;
|
||||
: 0 1 0 00 00 ?**** ?u;
|
||||
: 0 0 0 00 00 ?**** ?u;
|
||||
: 0 0 1 00 00 ?**** ?u;
|
||||
: 1 0 1 00 00 ?**** ?u;
|
||||
: 0 0 1 00 00 ?**** ?u;
|
||||
: 0 0 0 02 03 ?**** ?u;
|
||||
: 1 0 0 02 03 ?**** ?u;
|
||||
: 0 0 0 02 03 ?0000 ?0;
|
||||
: 0 0 0 00 00 ?0000 ?0;
|
||||
: 1 0 0 00 00 ?0000 ?0;
|
||||
: 0 0 0 00 00 ?0000 ?0;
|
||||
: 0 0 0 00 00 ?0000 ?0;
|
||||
: 1 0 0 00 00 ?0000 ?0;
|
||||
: 0 0 0 00 00 ?0000 ?0;
|
||||
: 0 0 0 00 00 ?0000 ?0;
|
||||
: 1 0 0 00 00 ?0000 ?0;
|
||||
: 0 0 0 00 00 ?0000 ?0;
|
||||
: 0 0 0 00 00 ?0000 ?0;
|
||||
: 1 0 0 00 00 ?0000 ?0;
|
||||
: 0 0 0 00 00 ?0006 ?0;
|
||||
: 0 0 0 00 00 ?0006 ?0;
|
||||
: 1 0 0 00 00 ?0006 ?0;
|
||||
: 0 0 0 00 00 ?0006 ?1;
|
||||
: 0 0 0 00 00 ?0006 ?1;
|
||||
: 1 0 0 00 00 ?0006 ?1;
|
||||
: 0 0 0 00 00 ?0006 ?1;
|
||||
|
||||
end;
|
||||
|
|
@ -0,0 +1,121 @@
|
|||
-- Date of netlist generation: Dec-6-95
|
||||
----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity Multi8 is
|
||||
|
||||
|
||||
port ( A : in Std_Logic_Vector(7 downto 0) ;
|
||||
B : in Std_Logic_Vector(7 downto 0) ;
|
||||
CLK : in Std_Logic ;
|
||||
RST : in Std_Logic ;
|
||||
STB : in Std_Logic ;
|
||||
|
||||
RESULT : out Std_Logic_Vector(15 downto 0) ;
|
||||
DONE : out Std_Logic );
|
||||
|
||||
end Multi8;
|
||||
|
||||
----------------------------------------------------------------------
|
||||
|
||||
architecture Structural OF Multi8 is
|
||||
|
||||
component Controller
|
||||
port ( STB : in Std_Logic;
|
||||
CLK : in Std_Logic;
|
||||
LSB : in Std_Logic;
|
||||
DONE : in Std_Logic;
|
||||
RST : in Std_Logic;
|
||||
|
||||
INIT : out Std_Logic;
|
||||
SHIFT : out Std_Logic;
|
||||
ADD : out Std_Logic );
|
||||
end component;
|
||||
|
||||
component Srb
|
||||
port ( SHIFT : in Std_Logic;
|
||||
LD : in Std_Logic;
|
||||
CLK : in Std_Logic;
|
||||
B : in Std_Logic_Vector(7 downto 0) ;
|
||||
|
||||
OUTS : out Std_Logic_Vector(15 downto 0) );
|
||||
end component;
|
||||
|
||||
component AddAccu
|
||||
port ( CLR : in Std_Logic;
|
||||
LD : in Std_Logic;
|
||||
OUTS : in Std_Logic_Vector(15 downto 0) ;
|
||||
CLK : in Std_Logic;
|
||||
|
||||
RESULT : out Std_Logic_Vector(15 downto 0) );
|
||||
end component;
|
||||
|
||||
component Sra
|
||||
port ( SHIFT : in Std_Logic;
|
||||
LD : in Std_Logic;
|
||||
CLK : in Std_Logic;
|
||||
RST : in Std_Logic;
|
||||
A : in Std_Logic_Vector(7 downto 0) ;
|
||||
|
||||
DONE : out Std_Logic;
|
||||
LSB : out Std_Logic );
|
||||
end component;
|
||||
|
||||
|
||||
signal DONE_local: Std_Logic;
|
||||
signal U1_LSB : Std_Logic;
|
||||
signal U3_INIT : Std_Logic;
|
||||
signal U3_SHIFT : Std_Logic;
|
||||
signal U3_ADD : Std_Logic;
|
||||
signal OUT_INT : Std_Logic_vector(15 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
|
||||
U3: Controller
|
||||
port map ( STB => STB,
|
||||
CLK => CLK,
|
||||
LSB => U1_LSB,
|
||||
DONE => DONE_local,
|
||||
RST => RST,
|
||||
INIT => U3_INIT,
|
||||
SHIFT => U3_SHIFT,
|
||||
ADD => U3_ADD );
|
||||
|
||||
U2: Srb
|
||||
port map ( SHIFT => U3_SHIFT,
|
||||
LD => U3_INIT,
|
||||
CLK => CLK,
|
||||
B => B,
|
||||
OUTS => OUT_INT );
|
||||
|
||||
U5: AddAccu
|
||||
port map ( CLR => U3_INIT,
|
||||
LD => U3_ADD,
|
||||
OUTS => OUT_INT,
|
||||
CLK => CLK,
|
||||
RESULT => RESULT );
|
||||
|
||||
U1: Sra
|
||||
port map ( SHIFT => U3_SHIFT,
|
||||
LD => U3_INIT,
|
||||
RST => RST,
|
||||
CLK => CLK,
|
||||
A => A,
|
||||
DONE => DONE_local,
|
||||
LSB => U1_LSB );
|
||||
|
||||
DONE <= DONE_local;
|
||||
|
||||
end Structural;
|
||||
|
||||
configuration CFG_Multi8 of Multi8 is
|
||||
for Structural
|
||||
|
||||
end for;
|
||||
end CFG_Multi8;
|
||||
|
||||
|
||||
----------------------------------------------------------------------
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
|
||||
in clk B;;
|
||||
in rst B;;
|
||||
in stb B;;
|
||||
in A (7 downto 0) X;;
|
||||
in B (7 downto 0) X;;
|
||||
out result (15 downto 0) X;;
|
||||
out done B;
|
||||
|
||||
register u3.state(0 to 2) X;;
|
||||
register u1.outsint(7 downto 0) X;;
|
||||
|
||||
begin
|
||||
|
||||
-- PATTERN DESCRIPTION :
|
||||
|
||||
: 0 1 0 00 00 ?**** ?* ?* ?**;
|
||||
: 1 1 0 00 00 ?**** ?* ?* ?**;
|
||||
: 0 1 0 00 00 ?**** ?* ?* ?**;
|
||||
: 0 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 0 0 1 00 00 ?**** ?* ?* ?**;
|
||||
: 1 0 1 00 00 ?**** ?* ?* ?**;
|
||||
: 0 0 1 00 00 ?**** ?* ?* ?**;
|
||||
: 0 0 0 02 03 ?**** ?* ?* ?**;
|
||||
: 1 0 0 02 03 ?**** ?* ?* ?**;
|
||||
: 0 0 0 02 03 ?**** ?* ?* ?**;
|
||||
: 0 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 1 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 0 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 0 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 1 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 0 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 0 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 1 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 0 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 0 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 1 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 0 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 0 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 1 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 0 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 0 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 1 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 0 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 0 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 1 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 0 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 0 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 1 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 0 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 0 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 1 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 0 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 0 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 1 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 0 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 0 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 1 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 0 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 0 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 1 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 0 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 0 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 1 0 0 00 00 ?**** ?* ?* ?**;
|
||||
: 0 0 0 00 00 ?**** ?* ?* ?**;
|
||||
|
||||
end;
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_arith.ALL;
|
||||
use IEEE.STD_LOGIC_unsigned.ALL;
|
||||
|
||||
entity Sra is
|
||||
|
||||
port ( Shift : in Std_Logic ;
|
||||
LD : in Std_Logic ;
|
||||
RST : in Std_Logic;
|
||||
CLK : in Std_Logic ;
|
||||
A : in Std_Logic_Vector(7 downto 0);
|
||||
|
||||
Done : out Std_Logic ;
|
||||
LSB : out Std_Logic );
|
||||
|
||||
end Sra;
|
||||
|
||||
|
||||
----------------------------------------------------------------------
|
||||
|
||||
architecture DataFlow OF Sra is
|
||||
|
||||
signal outsint : Std_Logic_Vector(7 downto 0);
|
||||
begin
|
||||
process (CLK)
|
||||
begin
|
||||
if CLK'event and CLK='0' then
|
||||
if RST ='1' then outsint <= (others => '0');
|
||||
elsif LD = '1' then outsint <= A ;
|
||||
elsif Shift= '1' then
|
||||
outsint(7 downto 0) <= '0' & outsint(7 downto 1);
|
||||
else outsint <= outsint;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process( outsint )
|
||||
variable RESULT : Std_Logic;
|
||||
begin
|
||||
RESULT := '0';
|
||||
for j in outsint'range loop
|
||||
RESULT := outsint(j) or RESULT;
|
||||
exit when RESULT = '1';
|
||||
end loop;
|
||||
RESULT := not(RESULT);
|
||||
|
||||
Done <= RESULT;
|
||||
end process;
|
||||
LSB <= outsint(0);
|
||||
|
||||
end DataFlow;
|
||||
|
||||
|
||||
----------------------------------------------------------------------
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_arith.ALL;
|
||||
use IEEE.STD_LOGIC_unsigned.ALL;
|
||||
|
||||
entity Srb is
|
||||
|
||||
port ( Shift : in Std_Logic ;
|
||||
LD : in Std_Logic ;
|
||||
CLK : in Std_Logic ;
|
||||
B : in Std_Logic_Vector(7 downto 0);
|
||||
|
||||
OUTS : out Std_Logic_Vector(15 downto 0));
|
||||
|
||||
end Srb;
|
||||
|
||||
|
||||
----------------------------------------------------------------------
|
||||
|
||||
architecture DataFlow OF Srb is
|
||||
signal outsint : Std_Logic_Vector(15 downto 0);
|
||||
|
||||
begin
|
||||
process (CLK)
|
||||
begin
|
||||
if CLK'event and CLK='0' then
|
||||
if LD = '1' then outsint <=
|
||||
B(7)&B(7)&B(7)&B(7)&B(7)&B(7)&B(7)&B(7)&B ;
|
||||
elsif Shift= '1' then
|
||||
outsint(15 downto 0) <= outsint(14 downto 0) & '0';
|
||||
else outsint <= outsint;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
OUTS <= outsint;
|
||||
|
||||
end DataFlow;
|
||||
|
||||
|
||||
----------------------------------------------------------------------
|
||||
Loading…
Reference in New Issue