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ENFIN UN TUTORIAL POUR VASY !!!!! 

Description d'Hadamard synthetisable sous Synopsys et qui passe a la simulation
sur Alliance apres Transformation par VASY :-)))))
This commit is contained in:
The Syf Tool 2000-03-02 18:17:40 +00:00
parent ceb74f1000
commit 964e8582d7
17 changed files with 33373 additions and 0 deletions
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calcul C
compteur C
hadamard_model C
ram C
rom C
sequenceur C

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# /*------------------------------------------------------------\
# | |
# | This file is part of the Alliance CAD System Copyright |
# | (C) Laboratoire LIP6 - Département ASIM Universite P&M Curie|
# | |
# | Home page : http://www-asim.lip6.fr/alliance/ |
# | E-mail support : mailto:alliance-support@asim.lip6.fr |
# | |
# | This progam is free software; you can redistribute it |
# | and/or modify it under the terms of the GNU General Public |
# | License as published by the Free Software Foundation; |
# | either version 2 of the License, or (at your option) any |
# | later version. |
# | |
# | Alliance VLSI CAD System is distributed in the hope that |
# | it will be useful, but WITHOUT ANY WARRANTY; |
# | without even the implied warranty of MERCHANTABILITY or |
# | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General |
# | Public License for more details. |
# | |
# | You should have received a copy of the GNU General Public |
# | License along with the GNU C Library; see the file COPYING. |
# | If not, write to the Free Software Foundation, Inc., |
# | 675 Mass Ave, Cambridge, MA 02139, USA. |
# | |
# \------------------------------------------------------------*/
# /*------------------------------------------------------------\
# | |
# | Tool : VASY |
# | |
# | File : Makefile |
# | |
# | Author : Jacomme Ludovic |
# | |
# | Date : 30_01_98 |
# | |
# \------------------------------------------------------------*/
include $(ALLIANCE_TOP)/etc/$(ALLIANCE_OS).mk
include $(ALLIANCE_TOP)/etc/libraries.mk
# /*------------------------------------------------------------\
# | |
# | Cells |
# | |
# \------------------------------------------------------------*/
# /*------------------------------------------------------------\
# | |
# | Binary |
# | |
# \------------------------------------------------------------*/
VASY = $(ALLIANCE_TOP)/bin/vasy
ASIMUT = $(ALLIANCE_TOP)/bin/asimut
# /*------------------------------------------------------------\
# | |
# | Environement |
# | |
# \------------------------------------------------------------*/
ENV_VASY = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
MBK_CATAL_NAME=NO_CATAL; export MBK_CATAL_NAME
ENV_ASIMUT = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME;\
MBK_IN_LO=vst; export MBK_IN_LO;\
MBK_OUT_LO=vst; export MBK_OUT_LO
all : result_1.pat result_2.pat result_3.pat
# /*------------------------------------------------------------\
# | |
# | Asimut |
# | |
# \------------------------------------------------------------*/
result_1.pat : hadamard.vst
$(ENV_ASIMUT); $(ASIMUT) hadamard hadamard_1 result_1
result_2.pat : hadamard.vst
$(ENV_ASIMUT); $(ASIMUT) hadamard hadamard_2 result_2
result_3.pat : hadamard.vst
$(ENV_ASIMUT); $(ASIMUT) hadamard hadamard_3 result_3
# /*------------------------------------------------------------\
# | |
# | Vasy |
# | |
# \------------------------------------------------------------*/
hadamard.vst : hadamard.vhdl
$(ENV_VASY); $(VASY) -a -I vhdl -H hadamard
# /*------------------------------------------------------------\
# | |
# | Clean |
# | |
# \------------------------------------------------------------*/
realclean : clean
clean :
$(RM) -f *.vst *.vbe result_1.pat result_2.pat result_3.pat

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity calcul is
port (
ramout : in std_logic_vector( 7 downto 0);
hadout : out std_logic_vector(13 downto 0);
ope : in std_logic;
hph : in std_logic;
vaccu : in std_logic;
clraccu : in std_logic;
vbreg : in std_logic;
vhadout : in std_logic;
c2i : in std_logic;
reset : in std_logic;
ck : in std_logic);
end calcul;
architecture behavioral of calcul is
type pile is array (0 to 7) of std_logic_vector (13 downto 0);
signal op : std_logic_vector(13 downto 0);
signal mux : std_logic_vector(13 downto 0);
signal alu : std_logic_vector(13 downto 0);
signal re : std_logic_vector(13 downto 0);
signal rhadout : std_logic_vector(13 downto 0);
signal accu : std_logic_vector(13 downto 0);
signal breg : pile ;
begin
-- le multiplexeur d'abord --
-- *********************** --
mux <= breg (7) when hph='0' else "000000"&ramout;
-- calcul alu --
-- ********** --
op(13 downto 0) <= "11111111111111" when ope='1' else
"00000000000000";
re(0) <= (accu(0) xor ope) and mux(0);
re(13 downto 1) <= (mux(12 downto 0) and re(12 downto 0) )
or ( ( accu(12 downto 0) xor op(12 downto 0))
and ( mux(12 downto 0) or re(12 downto 0)) );
alu <= accu xor mux xor (re(13 downto 1) & '0');
-- accumulateur --
-- ************ --
process (ck)
begin
if (ck='0' and ck'event ) then
if (clraccu='1') then accu <= (others =>'0');
elsif (vaccu='1')
then accu <= alu;
else accu <= accu;
end if;
end if;
end process;
-- registre de sortie --
-- ****************** --
process (ck)
begin
if (ck='0' and ck'event ) then
if (reset='1') then rhadout <= (others =>'0');
elsif (vhadout='1')
then rhadout <= accu;
else rhadout <= rhadout;
end if;
end if;
end process;
hadout <= rhadout;
-- banc de regsitres a decalage --
-- **************************** --
process (ck)
begin
if (ck='0' and ck'event)
then
if (c2i='1')
then
if (vbreg='1')
then breg(0) <= alu;
else breg(0) <= breg(7);
end if;
breg (1 to 7) <= breg (0 to 6);
end if;
end if;
end process;
end behavioral;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity compteur is
port ( c1i : in std_logic;
c2i : in std_logic;
loi : in std_logic;
c1 : out std_logic_vector (2 downto 0) ;
c2 : out std_logic_vector (2 downto 0) ;
lo : out std_logic_vector (2 downto 0) ;
reset : in std_logic;
ck : in std_logic );
end compteur;
architecture behavioral of compteur is
signal rc1 : integer range 0 to 7;
signal rc2 : integer range 0 to 7;
signal rlo : integer range 0 to 7;
begin
process (ck)
begin
if (ck='0' and ck'event) then
if (reset='1') then rc1<=0; rc2<=0; rlo<=0;
else
if c1i='1' then rc1 <= (rc1 + 1) mod 8;
else rc1 <= rc1;
end if;
if c2i='1' then rc2 <= (rc2 + 1) mod 8;
else rc2 <= rc2;
end if;
if loi='1' then rlo <= (rlo + 1) mod 8;
else rlo <= rlo;
end if;
end if;
end if;
end process;
c1 <= (conv_std_logic_vector(rc1,c1'length));
c2 <= (conv_std_logic_vector (rc2,c2'length));
lo <= (conv_std_logic_vector (rlo,lo'length));
end behavioral;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity hadamard is
port ( ck : in std_logic;
data : in std_logic_vector (7 downto 0);
empty : in std_logic;
full : in std_logic;
reset : in std_logic;
hadout : out std_logic_vector (13 downto 0);
s_read : out std_logic;
s_write : out std_logic );
end hadamard;
architecture schematic of hadamard is
signal ramout : std_logic_vector(7 downto 0);
signal ope : std_logic;
signal hph : std_logic;
signal vaccu : std_logic;
signal clraccu : std_logic;
signal vbreg : std_logic;
signal vhadout : std_logic;
signal c1 : std_logic_vector(2 downto 0);
signal c2 : std_logic_vector(2 downto 0);
signal c1c2 : std_logic_vector(5 downto 0);
signal lo : std_logic_vector(2 downto 0);
signal loi : std_logic;
signal c2i : std_logic;
signal c1i : std_logic;
signal readout : std_logic;
signal nreadout : std_logic;
signal nck : std_logic;
component calcul
port( ramout : in std_logic_vector ( 7 downto 0);
hadout : out std_logic_vector (13 downto 0);
ope : in std_logic;
hph : in std_logic;
vaccu : in std_logic;
clraccu : in std_logic;
vbreg : in std_logic;
vhadout : in std_logic;
c2i : in std_logic;
reset : in std_logic;
ck : in std_logic );
end component;
component sequenceur
port( c1 : in std_logic_vector (2 downto 0);
c2 : in std_logic_vector (2 downto 0);
lo : in std_logic_vector (2 downto 0);
ck : in std_logic;
empty : in std_logic;
full : in std_logic;
reset : in std_logic;
c1i : out std_logic;
c2i : out std_logic;
loi : out std_logic;
clraccu : out std_logic;
hph : out std_logic;
s_read : out std_logic;
vaccu : out std_logic;
vbreg : out std_logic;
vhadout : out std_logic;
s_write : out std_logic );
end component;
component compteur
port( c1i : in std_logic;
c2i : in std_logic;
loi : in std_logic;
c1 : out std_logic_vector (2 downto 0);
c2 : out std_logic_vector (2 downto 0);
lo : out std_logic_vector (2 downto 0) ;
reset : in std_logic;
ck : in std_logic );
end component;
component rom
port( c1 : in std_logic_vector (2 downto 0);
c2 : in std_logic_vector (2 downto 0);
hph : in std_logic;
lo : in std_logic_vector (2 downto 0);
ope : out std_logic );
end component;
component ram
port ( A : in std_logic_vector(5 downto 0);
CEB, WEB : in std_logic;
INN : in std_logic_vector(7 downto 0);
OUTT : out std_logic_vector(7 downto 0) );
end component;
begin
c1c2 <= c1&c2;
s_read <= readout;
nreadout <= not(readout);
nck <= not(ck);
e_ram : ram
port map( A => c1c2
, CEB => nck
, WEB => nreadout
, INN => data
, OUTT => ramout );
e_calcul : calcul
port map( ramout => ramout
, hadout => hadout
, ope => ope
, hph => hph
, vaccu => vaccu
, clraccu => clraccu
, vbreg => vbreg
, vhadout => vhadout
, c2i => c2i
, reset => reset
, ck => ck );
e_sequenceur : sequenceur
port map( c1 => c1
, c2 => c2
, lo => lo
, ck => ck
, empty => empty
, full => full
, reset => reset
, c1i => c1i
, c2i => c2i
, loi => loi
, clraccu => clraccu
, hph => hph
, s_read => readout
, vaccu => vaccu
, vbreg => vbreg
, vhadout => vhadout
, s_write => s_write );
e_rom : rom
port map( c1 => c1
, c2 => c2
, lo => lo
, hph => hph
, ope => ope );
e_compteur : compteur
port map( c1i => c1i
, c2i => c2i
, loi => loi
, c1 => c1
, c2 => c2
, lo => lo
, reset => reset
, ck => ck );
end schematic;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
entity hadamard_tb is
end hadamard_tb;
architecture test_bench of hadamard_tb is
component hadamard
port ( ck : in std_logic;
data : in std_logic_vector (7 downto 0);
empty : in std_logic;
full : in std_logic;
reset : in std_logic;
hadout : out std_logic_vector (13 downto 0);
s_read : out std_logic;
s_write : out std_logic );
end component;
signal i_ck : std_logic;
signal i_data : std_logic_vector (7 downto 0);
signal i_empty : std_logic;
signal i_full : std_logic;
signal i_reset : std_logic;
signal i_hadout : std_logic_vector (13 downto 0);
signal i_read : std_logic;
signal i_write : std_logic;
begin
InsHadamard : hadamard
port map( i_ck, i_data, i_empty, i_full, i_reset,
i_hadout, i_read, i_write );
Stimulus:
process
--use IEEE.STD_LOGIC_TEXTIO.ALL;
use STD.TEXTIO.ALL;
FILE infile: TEXT is IN "hadamard.stim";
FILE outfile: TEXT is OUT "hadamard_res.stim";
VARIABLE L1, L2: LINE;
variable v_char : character;
variable v_ck : std_logic;
variable v_data : std_logic_vector (7 downto 0);
variable v_empty : std_logic;
variable v_full : std_logic;
variable v_reset : std_logic;
variable v_hadout : std_logic_vector (13 downto 0);
variable v_read : std_logic;
variable v_write : std_logic;
begin
While not (endfile(infile)) loop
readline (infile,L1);
read( L1, v_char);
if ( v_char = '#' )
then writeline(outfile,L1);
next;
end if;
read( L1, v_ck);
read( L1, v_data);
read( L1, v_empty);
read( L1, v_full);
read( L1, v_reset);
i_ck <= v_ck;
i_data <= v_data;
i_empty <= v_empty;
i_full <= v_full;
i_reset <= v_reset;
wait for 100 ns;
write( L2, i_ck);
write( L2, i_data);
write( L2, i_empty);
write( L2, i_full);
write( L2, i_reset);
write( L2, i_hadout);
write( L2, i_read);
write( L2, i_write);
writeline (outfile,L2);
end loop;
ASSERT FALSE REPORT "End of simulation !!!"
SEVERITY ERROR;
wait; -- to terminate simulation
end process;
end test_bench;
configuration CFG_test_bench of hadamard_tb is
use WORK.all;
for test_bench
FOR InsHadamard : Hadamard
use entity WORK.Hadamard(schematic);
end for;
end for;
end CFG_test_bench;

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---------------------------------------------------------
---------------- Bank description ----------------
---------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
--use IEEE.STD_LOGIC_signed.ALL;
ENTITY ram IS
port ( A : in std_logic_vector(5 downto 0);
CEB, WEB : in std_logic;
INN : in std_logic_vector(7 downto 0);
OUTT : out std_logic_vector(7 downto 0)
);
END ram;
ARCHITECTURE dataflow_view OF ram IS
SUBTYPE TYPE_WORD IS std_logic_vector(7 downto 0);
TYPE TYPE_RAM IS ARRAY(63 DOWNTO 0) OF TYPE_WORD;
SIGNAL memory : TYPE_RAM;
BEGIN
OUTT <= memory( CONV_INTEGER( A ) );
RAM_0 : PROCESS( CEB )
BEGIN
IF (CEB='0' AND CEB'EVENT )
THEN IF (WEB='0')
THEN memory( CONV_INTEGER( A ) ) <= INN;
END IF;
END IF;
END PROCESS RAM_0;
END dataflow_view;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.STD_LOGIC_arith.ALL;
entity rom is
port ( c1 : in std_logic_vector (2 downto 0);
c2 : in std_logic_vector (2 downto 0);
hph : in std_logic;
lo : in std_logic_vector (2 downto 0);
ope : out std_logic );
end rom;
architecture behavioral of rom is
signal adr : std_logic_vector (5 downto 0);
constant rom_data : std_logic_vector(0 to 63) := "0000000000001111001111000011001101100110011010010101101001010101";
begin
adr <= c2(2 downto 0)&c1(2 downto 0) when hph='0' else
lo(2 downto 0)&c1(2 downto 0) ;
ope <= rom_data(conv_integer(Adr));
end behavioral;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sequenceur is
port ( c1 : in std_logic_vector (2 downto 0);
c2 : in std_logic_vector (2 downto 0);
lo : in std_logic_vector (2 downto 0);
ck : in std_logic;
empty : in std_logic;
full : in std_logic;
reset : in std_logic;
c1i : out std_logic;
c2i : out std_logic;
clraccu : out std_logic;
hph : out std_logic;
loi : out std_logic;
s_read : out std_logic;
vaccu : out std_logic;
vbreg : out std_logic;
vhadout : out std_logic;
s_write : out std_logic );
end sequenceur;
architecture behavioral of sequenceur is
type etat_type is (E0,E1,E2,E3,E4,E5,E6,E7,E8,E9,E10);
signal next_state,current_state : etat_type;
begin
process (current_state,reset,empty,full,c1,c2,lo)
begin
if (reset='1') then
next_state <= E0;
s_read <= '0';
s_write <= '0';
clraccu <= '1';
hph <= '0';
vhadout <= '0';
vaccu <= '0';
vbreg <= '0';
c1i <= '0';
c2i <= '0';
loi <= '0';
else
case current_state is
when E0 =>
next_state <= E1;
s_read <= '0';
s_write <= '0';
clraccu <= '1';
hph <= '0';
vhadout <= '0';
vaccu <= '0';
vbreg <= '0';
c1i <= '0';
c2i <= '0';
loi <= '0';
when E1 =>
if (empty = '1') then next_state <= E1;
else next_state <= E2;
end if;
s_read <= '1';
s_write <= '0';
clraccu <= '0';
hph <= '0';
vhadout <= '0';
vaccu <= '0';
vbreg <= '0';
c1i <= '0';
c2i <= '0';
loi <= '0';
when E2 =>
if (c2 = "111") then next_state <= E3;
else next_state <= E1;
end if;
s_read <= '0';
s_write <= '0';
clraccu <= '0';
hph <= '0';
vhadout <= '0';
vaccu <= '0';
vbreg <= '0';
c1i <= '0';
c2i <= '1';
loi <= '0';
when E3 =>
if (c1 = "111") then next_state <= E4;
else next_state <= E1;
end if;
s_read <= '0';
s_write <= '0';
clraccu <= '0';
hph <= '0';
vhadout <= '0';
vaccu <= '0';
vbreg <= '0';
c1i <= '1';
c2i <= '0';
loi <= '0';
when E4 =>
if (c1 = "110") then next_state <= E5;
else next_state <= E4;
end if;
s_read <= '0';
s_write <= '0';
clraccu <= '0';
hph <= '1';
vhadout <= '0';
vaccu <= '1';
vbreg <= '0';
c1i <= '1';
c2i <= '0';
loi <= '0';
when E5 =>
if ( c2 = "111" ) then next_state <= E6;
else next_state <= E4;
end if;
s_read <= '0';
s_write <= '0';
clraccu <= '1';
hph <= '1';
vhadout <= '0';
vaccu <= '0';
vbreg <= '1';
c1i <= '1';
c2i <= '1';
loi <= '0';
when E6 =>
if (c2 = "111") then next_state <= E7;
else next_state <= E6;
end if;
s_read <= '0';
s_write <= '0';
clraccu <= '0';
hph <= '0';
vhadout <= '0';
vaccu <= '1';
vbreg <= '0';
c1i <= '0';
c2i <= '1';
loi <= '0';
when E7 =>
next_state <= E8;
s_read <= '0';
s_write <= '0';
clraccu <= '0';
hph <= '0';
vhadout <= '1';
vaccu <= '0';
vbreg <= '0';
c1i <= '0';
c2i <= '0';
loi <= '0';
when E8 =>
if (full = '1') then next_state <= E8;
else next_state <= E9;
end if;
s_read <= '0';
s_write <= '1';
clraccu <= '1';
hph <= '0';
vhadout <= '0';
vaccu <= '0';
vbreg <= '0';
c1i <= '0';
c2i <= '0';
loi <= '0';
when E9 =>
if (c1 = "111") then next_state <= E10;
else next_state <= E6;
end if;
s_read <= '0';
s_write <= '0';
clraccu <= '1';
hph <= '0';
vhadout <= '0';
vaccu <= '0';
vbreg <= '0';
c1i <= '1';
c2i <= '0';
loi <= '0';
when E10 =>
if(lo = "111") then next_state <= E0;
else next_state <= E4;
end if;
s_read <= '0';
s_write <= '0';
clraccu <= '1';
hph <= '0';
vhadout <= '0';
vaccu <= '0';
vbreg <= '0';
c1i <= '0';
c2i <= '0';
loi <= '1';
end case;
end if;
end process;
process(ck)
begin
if (ck='0' and ck'event) then
current_state <= next_state;
end if;
end process;
end behavioral;