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The Syf Tool 2000-03-02 17:15:49 +00:00
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@ -1,4 +1,4 @@
.\" $Id: vasy.5,v 1.3 2000/02/29 14:33:33 syf Exp $
.\" $Id: vasy.5,v 1.4 2000/03/02 17:15:49 syf Exp $
.\" @(#)VASY.5 1.0 Jan 28 1992 UPMC ; Ludovic Jacomme
.TH VASY 5 "December 11, 1999" "ASIM/LIP6" "VHDL subset of VASY."
@ -14,8 +14,7 @@ This document describes the VHDL subset accepted by VASY for RTL descriptions.
.PP
\fBCONCURRENT STATEMENTS\fP
.br
In an RTL architecture most of the concurrent statements are supported,
but generate constructs and port map clauses are not allowed.
In an RTL architecture most of the concurrent statements are supported.
.PP
Allowed concurrent statements are: