* Bibliotheque RFLIB :
- Bug : des "out" au lieu d'"inout", des parentheses oubliees. - Bug : un registre "latch" oublie dans "rf_mid_mem_r0.vbe".
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@ -1,7 +1,7 @@
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ENTITY rf_dec_bufad0 IS
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ENTITY rf_dec_bufad0 IS
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PORT (
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PORT (
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i : in BIT;
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i : in BIT;
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nq : out BIT;
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nq : inout BIT;
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q : out BIT;
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q : out BIT;
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vdd : in BIT;
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vdd : in BIT;
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vss : in BIT
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vss : in BIT
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@ -2,9 +2,9 @@ ENTITY rf_dec_bufad2 IS
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PORT (
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PORT (
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i0 : in BIT;
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i0 : in BIT;
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i1 : in BIT;
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i1 : in BIT;
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nq0 : out BIT;
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nq0 : inout BIT;
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q0 : out BIT;
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q0 : out BIT;
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nq1 : out BIT;
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nq1 : inout BIT;
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q1 : out BIT;
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q1 : out BIT;
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vdd : in BIT;
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vdd : in BIT;
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vss : in BIT
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vss : in BIT
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@ -2,9 +2,9 @@ ENTITY rf_dec_bufad2r IS
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PORT (
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PORT (
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i0 : in BIT;
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i0 : in BIT;
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i1 : in BIT;
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i1 : in BIT;
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nq0 : out BIT;
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nq0 : inout BIT;
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q0 : out BIT;
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q0 : out BIT;
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nq1 : out BIT;
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nq1 : inout BIT;
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q1 : out BIT;
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q1 : out BIT;
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vdd : in BIT;
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vdd : in BIT;
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vss : in BIT
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vss : in BIT
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@ -16,6 +16,6 @@ BEGIN
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REPORT "power supply is missing on rf_dec_nao3"
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REPORT "power supply is missing on rf_dec_nao3"
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SEVERITY WARNING;
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SEVERITY WARNING;
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nq <= not(i0 and (i1 or i2);
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nq <= not(i0 and (i1 or i2));
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END;
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END;
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@ -10,7 +10,6 @@ PORT (
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END rf_mid_mem_r0;
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END rf_mid_mem_r0;
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ARCHITECTURE VBE OF rf_mid_mem_r0 IS
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ARCHITECTURE VBE OF rf_mid_mem_r0 IS
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SIGNAL latch : REG_BIT REGISTER;
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BEGIN
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BEGIN
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ASSERT (vdd and not (vss))
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ASSERT (vdd and not (vss))
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@ -22,4 +21,5 @@ BEGIN
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rbus <= GUARDED '0';
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rbus <= GUARDED '0';
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END BLOCK label1;
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END BLOCK label1;
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END;
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END;
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