diff --git a/alliance/share/cells/rflib/rf_dec_bufad0.vbe b/alliance/share/cells/rflib/rf_dec_bufad0.vbe
index bdc7e789..03c3741f 100644
--- a/alliance/share/cells/rflib/rf_dec_bufad0.vbe
+++ b/alliance/share/cells/rflib/rf_dec_bufad0.vbe
@@ -1,7 +1,7 @@
 ENTITY rf_dec_bufad0 IS
 PORT (
   i      : in  BIT;
-  nq  	 : out BIT;
+  nq  	 : inout BIT;
   q  	 : out BIT;
   vdd	 : in  BIT;
   vss	 : in  BIT
diff --git a/alliance/share/cells/rflib/rf_dec_bufad2.vbe b/alliance/share/cells/rflib/rf_dec_bufad2.vbe
index 3e58ea6b..10b7cb27 100644
--- a/alliance/share/cells/rflib/rf_dec_bufad2.vbe
+++ b/alliance/share/cells/rflib/rf_dec_bufad2.vbe
@@ -2,9 +2,9 @@ ENTITY rf_dec_bufad2 IS
 PORT (
   i0     : in  BIT;
   i1     : in  BIT;
-  nq0  	 : out BIT;
+  nq0  	 : inout BIT;
   q0   	 : out BIT;
-  nq1  	 : out BIT;
+  nq1  	 : inout BIT;
   q1   	 : out BIT;
   vdd	 : in  BIT;
   vss	 : in  BIT
diff --git a/alliance/share/cells/rflib/rf_dec_bufad2r.vbe b/alliance/share/cells/rflib/rf_dec_bufad2r.vbe
index 05f71d9d..89f5751b 100644
--- a/alliance/share/cells/rflib/rf_dec_bufad2r.vbe
+++ b/alliance/share/cells/rflib/rf_dec_bufad2r.vbe
@@ -2,9 +2,9 @@ ENTITY rf_dec_bufad2r IS
 PORT (
   i0     : in  BIT;
   i1     : in  BIT;
-  nq0  	 : out BIT;
+  nq0  	 : inout BIT;
   q0   	 : out BIT;
-  nq1  	 : out BIT;
+  nq1  	 : inout BIT;
   q1   	 : out BIT;
   vdd	 : in  BIT;
   vss	 : in  BIT
diff --git a/alliance/share/cells/rflib/rf_dec_nao3.vbe b/alliance/share/cells/rflib/rf_dec_nao3.vbe
index 91d7b93f..892fa96e 100644
--- a/alliance/share/cells/rflib/rf_dec_nao3.vbe
+++ b/alliance/share/cells/rflib/rf_dec_nao3.vbe
@@ -16,6 +16,6 @@ BEGIN
   REPORT "power supply is missing on rf_dec_nao3"
   SEVERITY WARNING;
 
-  nq <= not(i0 and (i1 or i2);
+  nq <= not(i0 and (i1 or i2));
 
 END;
diff --git a/alliance/share/cells/rflib/rf_mid_mem_r0.vbe b/alliance/share/cells/rflib/rf_mid_mem_r0.vbe
index 2290b20f..71c03d0e 100644
--- a/alliance/share/cells/rflib/rf_mid_mem_r0.vbe
+++ b/alliance/share/cells/rflib/rf_mid_mem_r0.vbe
@@ -10,7 +10,6 @@ PORT (
 END rf_mid_mem_r0;
 
 ARCHITECTURE VBE OF rf_mid_mem_r0 IS
-  SIGNAL latch	 : REG_BIT REGISTER;
 
 BEGIN
   ASSERT (vdd and not (vss))
@@ -22,4 +21,5 @@ BEGIN
     rbus <= GUARDED '0';
   END BLOCK label1;
 
+
 END;