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* Bibliotheque RFLIB : 

- Bug : des "out" au lieu d'"inout", des parentheses oubliees.
  - Bug : un registre "latch" oublie dans "rf_mid_mem_r0.vbe".
This commit is contained in:
Jean-Paul Chaput 2000-11-06 15:42:10 +00:00
parent 98fbb18c88
commit 91a3a35df5
5 changed files with 7 additions and 7 deletions
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2
alliance/share/cells/rflib/rf_dec_bufad0.vbe
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@ -1,7 +1,7 @@
ENTITY rf_dec_bufad0 IS
PORT (
i : in BIT;
nq : out BIT;
nq : inout BIT;
q : out BIT;
vdd : in BIT;
vss : in BIT

4
alliance/share/cells/rflib/rf_dec_bufad2.vbe
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@ -2,9 +2,9 @@ ENTITY rf_dec_bufad2 IS
PORT (
i0 : in BIT;
i1 : in BIT;
nq0 : out BIT;
nq0 : inout BIT;
q0 : out BIT;
nq1 : out BIT;
nq1 : inout BIT;
q1 : out BIT;
vdd : in BIT;
vss : in BIT

4
alliance/share/cells/rflib/rf_dec_bufad2r.vbe
View File

@ -2,9 +2,9 @@ ENTITY rf_dec_bufad2r IS
PORT (
i0 : in BIT;
i1 : in BIT;
nq0 : out BIT;
nq0 : inout BIT;
q0 : out BIT;
nq1 : out BIT;
nq1 : inout BIT;
q1 : out BIT;
vdd : in BIT;
vss : in BIT

2
alliance/share/cells/rflib/rf_dec_nao3.vbe
View File

@ -16,6 +16,6 @@ BEGIN
REPORT "power supply is missing on rf_dec_nao3"
SEVERITY WARNING;
nq <= not(i0 and (i1 or i2);
nq <= not(i0 and (i1 or i2));
END;

2
alliance/share/cells/rflib/rf_mid_mem_r0.vbe
View File

@ -10,7 +10,6 @@ PORT (
END rf_mid_mem_r0;
ARCHITECTURE VBE OF rf_mid_mem_r0 IS
SIGNAL latch : REG_BIT REGISTER;
BEGIN
ASSERT (vdd and not (vss))
@ -22,4 +21,5 @@ BEGIN
rbus <= GUARDED '0';
END BLOCK label1;
END;