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tut fitpath

This commit is contained in:
Olivier Sirol 2000-01-19 17:18:04 +00:00
parent 5e99ddbb74
commit 8b9a34ba60
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545
alliance/share/tutorials/fitpath/Makefile Normal file
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#
# %% \textrm{This File Looks Nicer with\textsf{ LGrind} and \LaTeXe.} %%
# %| |%
# %| /---------------------------------------------------------------------\ |%
# %| | | |%
# %| | Alliance CAD System V.R | |%
# %| | F p G e n P a c k a g e V.RR | |%
# %| | | |%
# %| | Copyright(c) 95-AA, MASI, CAO-VLSI Team | |%
# %| | | |%
# %| | Author : Jean-Paul CHAPUT | |%
# %| | =================================================================== | |%
# %| | File : "Makefile" | |%
# %| | ******************************************************************* | |%
# %| | FpGen / DPR examples. | |%
# %| | | |%
# %| \---------------------------------------------------------------------/ |%
#
# Installation Dependent Variables.
TOP_LAB = $(ALLIANCE_TOP)
TOP_LIB = $(ALLIANCE_TOP)
# Alliance binary access paths.
ALLIANCE_BIN =$(ALLIANCE_TOP)/bin
FITPATH_BIN =$(ALLIANCE_TOP)/bin
USER_BIN =$(ALLIANCE_TOP)/bin
DPR_BIN =$(ALLIANCE_TOP)/bin
## ************************* Various MBK environment *************************
#
#
# Alliance leaf cells libraries paths.
# ====================================
#
RSA_LIB = $(TOP_LIB)/cells/rsa
DPLIB = $(TOP_LAB)/cells/dplib
FPLIB = $(TOP_LAB)/cells/fplib
FPGEN_LIB = ./mclib
CATA_LIB = $(FPGEN_LIB):$(RSA_LIB):$(FPLIB):$(DPLIB)
#
#
# MBK environment common to all Alliance tools.
# =============================================
#
MBK_STD = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
MBK_CATA_LIB=$(CATA_LIB); export MBK_CATA_LIB; \
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME; \
MBK_SEPAR=.; export MBK_SEPAR; \
MBK_VDD=vdd; export MBK_VDD; \
MBK_VSS=vss; export MBK_VSS; \
MBK_TARGET_LIB=$(DPLIB); export MBK_TARGET_LIB; \
MBK_LOG_NAME=""; export MBK_LOG_NAME; \
FPGEN_LIB=$(FPGEN_LIB); export FPGEN_LIB
#
#
# Avalaibles MBK netlist and layout formats.
# ==========================================
#
MBK_FNE = MBK_OUT_LO=fne; export MBK_OUT_LO; MBK_IN_LO=fne; export MBK_IN_LO
MBK_HNS = MBK_OUT_LO=hns; export MBK_OUT_LO; MBK_IN_LO=hns; export MBK_IN_LO
MBK_CP = MBK_OUT_PH=cp; export MBK_OUT_PH; MBK_IN_PH=cp; export MBK_IN_PH
MBK_VST = MBK_OUT_LO=vst; export MBK_OUT_LO; MBK_IN_LO=vst; export MBK_IN_LO
MBK_AL = MBK_OUT_LO=al; export MBK_OUT_LO; MBK_IN_LO=al; export MBK_IN_LO
MBK_AP = MBK_OUT_PH=ap; export MBK_OUT_PH; MBK_IN_PH=ap; export MBK_IN_PH
#
#
# Alliance Tools with the correct MBK environment.
# ================================================
#
BOP = $(MBK_STD); $(MBK_VST); $(MBK_AP); $(ALLIANCE_BIN)/bop
SCMAP = $(MBK_STD); $(MBK_VST); $(MBK_AP); $(ALLIANCE_BIN)/scmap
FPGEN = $(MBK_STD); $(MBK_VST); $(MBK_AP); $(ALLIANCE_BIN)/fpgen
# DPR = $(MBK_STD); $(MBK_VST); $(MBK_AP); $(ALLIANCE_BIN)/dpr
DRUC = $(MBK_STD); $(MBK_VST); $(MBK_AP); $(ALLIANCE_BIN)/druc
LYNX = $(MBK_STD); $(MBK_AL); $(MBK_AP); $(ALLIANCE_BIN)/lynx
DESB = $(MBK_STD); $(MBK_AL); $(ALLIANCE_BIN)/yagle
PROOF = $(MBK_STD); $(ALLIANCE_BIN)/proof
LVX = $(MBK_STD); $(ALLIANCE_BIN)/lvx
# FPGEN = $(MBK_STD); $(MBK_VST); $(MBK_AP); $(FITPATH_BIN)/fpgen
# DPR = $(MBK_STD); $(MBK_VST); $(MBK_AP); $(FITPATH_BIN)/dpr
DPR = $(MBK_STD); $(MBK_VST); $(MBK_AP); $(DPR_BIN)/dpr
# DPR = $(MBK_STD); $(MBK_VST); $(MBK_AP); $(LABO_BIN)/dpr
# LVX = $(MBK_STD); $(USER_BIN)/sparc/lvx-2.23
# DESB = $(MBK_STD); $(MBK_AL); $(USER_BIN)/sparc/desb-2.91
## ***************************** Starting Rules ******************************
help:
@echo 'Makefile:'; \
echo ''; \
echo ' "$$ make all" : run all examples.'; \
echo ' "$$ make sample" : run the more sample example.'; \
echo ' "$$ make place" : run optimized placement example.'; \
echo ' "$$ make usercol" : run operator customized example.'; \
echo ' "$$ make hierarchy" : run hierarchical design example.'; \
echo ' "$$ make clean" : delete all generated files.'; \
echo ''
all: sample place usercol hierarchy synthesis
sample: sample_druc sample_lvx sample_proof
place: place_druc place_lvx place_proof
usercol: usercol_druc usercol_lvx usercol_proof
synthesis: synthesis_druc synthesis_lvx synthesis_proof
hierarchy: hierarchy_druc hierarchy_lvx hierarchy_proof
bench: all
## *********************** Rules for sample Data-Path ************************
#
#
# FpGen : Generation of the Netlist.
# ==================================
#
sample_dpt.vst: sample_dpt.c
$(FPGEN) -v sample_dpt
#
#
# DPR : Routing the data-path.
# ============================
#
sample_dpt.ap: sample_dpt.dpr sample_dpt.vst
$(DPR) -V -p -r sample_dpt sample_dpt
#
#
# DRUC : Symbolic Design RUles Checker.
# =====================================
#
sample_druc: sample_dpt.ap
$(DRUC) sample_dpt
#
#
# LYNX : Gate level netlist extraction.
# =====================================
#
sample_dpt_gates.al: sample_dpt.ap
$(LYNX) -v -f sample_dpt sample_dpt_gates
#
#
# LVX : Netlist comparison.
# =========================
#
sample_lvx: sample_dpt.vst sample_dpt_gates.al
$(LVX) vst al sample_dpt sample_dpt_gates -f
#
#
# LYNX : Transistor netlist extraction.
# =====================================
#
sample_dpt.al: sample_dpt.ap
$(LYNX) -v -t sample_dpt sample_dpt
#
#
# DESB : Behavioral exctraction.
# ==============================
#
sample_dpt_desb.vbe: sample_dpt.inf sample_dpt.al
$(DESB) sample_dpt sample_dpt_desb -v -i
#
#
# PROOF : Formal proof.
# =====================
#
sample_proof: sample_dpt.vbe sample_dpt_desb.vbe
$(PROOF) -d sample_dpt sample_dpt_desb
## ************** Rules for Data-Path using optimized placement **************
#
#
# FpGen : Generation of the Netlist.
# ==================================
#
place_dpt.vst: place_dpt.c
$(FPGEN) -v place_dpt
#
#
# DPR : Routing the data-path.
# ============================
#
place_dpt.ap: place_dpt.dpr place_dpt.vst
$(DPR) -V -o -p -r place_dpt place_dpt
#
#
# DRUC : Symbolic Design RUles Checker.
# =====================================
#
place_druc: place_dpt.ap
$(DRUC) place_dpt
#
#
# LYNX : Gate level netlist extraction.
# =====================================
#
place_dpt_gates.al: place_dpt.ap
$(LYNX) -v -f place_dpt place_dpt_gates
#
#
# LVX : Netlist comparison.
# =========================
#
place_lvx: place_dpt.vst place_dpt_gates.al
$(LVX) vst al place_dpt place_dpt_gates -f
#
#
# LYNX : Transistor netlist extraction.
# =====================================
#
place_dpt.al: place_dpt.ap
$(LYNX) -v -t place_dpt place_dpt
#
#
# DESB : Behavioral exctraction.
# ==============================
#
place_dpt_desb.vbe: place_dpt.inf place_dpt.al
$(DESB) place_dpt place_dpt_desb -v -i
#
#
# PROOF : Formal proof.
# =====================
#
place_proof: sample_dpt.vbe place_dpt_desb.vbe
$(PROOF) -d sample_dpt place_dpt_desb
## *********** Rules for Data-Path using Hierarchical description ************
#
#
# FpGen : Generation of the Netlist.
# ==================================
#
hierarchy_dpt.vst: hierarchy_dpt.c
$(FPGEN) -v hierarchy_dpt
#
#
# DPR : Routing the data-path.
# ============================
#
hierarchy_dpt.ap: hierarchy_dpt.dpr hierarchy_dpt.vst
$(DPR) -V -p -r hierarchy_dpt hierarchy_dpt
#
#
# DRUC : Symbolic Design RUles Checker.
# =====================================
#
hierarchy_druc: hierarchy_dpt.ap
$(DRUC) hierarchy_dpt
#
#
# LYNX : Gate level netlist extraction.
# =====================================
#
hierarchy_dpt_gates.al: hierarchy_dpt.ap
$(LYNX) -v -f hierarchy_dpt hierarchy_dpt_gates
#
#
# LVX : Netlist comparison.
# =========================
#
hierarchy_lvx: hierarchy_dpt.vst hierarchy_dpt_gates.al
$(LVX) vst al hierarchy_dpt hierarchy_dpt_gates -f
#
#
# LYNX : Transistor netlist extraction.
# =====================================
#
hierarchy_dpt.al: hierarchy_dpt.ap
$(LYNX) -v -t hierarchy_dpt hierarchy_dpt
#
#
# DESB : Behavioral exctraction.
# ==============================
#
hierarchy_dpt_desb.vbe: hierarchy_dpt.inf hierarchy_dpt.al
$(DESB) hierarchy_dpt hierarchy_dpt_desb -v -i
#
#
# PROOF : Formal proof.
# =====================
#
hierarchy_proof: sample_dpt.vbe hierarchy_dpt_desb.vbe
$(PROOF) -d sample_dpt hierarchy_dpt_desb
## ******************* Rules for Data-Path using synthesis *******************
#
#
# Logic : Synthesis of the Adder.
# ===============================
#
adder_us.vst: adder_us.vbe
$(BOP) -o adder_us adder_us_opt
$(SCMAP) adder_us_opt adder_us
#
#
# FpGen : Generation of the Netlist.
# ==================================
#
synthesis_dpt.vst: adder_us.vst synthesis_dpt.c
$(FPGEN) -v synthesis_dpt
#
#
# DPR : Routing the data-path.
# ============================
#
synthesis_dpt.ap: synthesis_dpt.dpr synthesis_dpt.vst
$(DPR) -V -p -r synthesis_dpt synthesis_dpt
#
#
# DRUC : Symbolic Design RUles Checker.
# =====================================
#
synthesis_druc: synthesis_dpt.ap
$(DRUC) synthesis_dpt
#
#
# LYNX : Gate level netlist extraction.
# =====================================
#
synthesis_dpt_gates.al: synthesis_dpt.ap
$(LYNX) -v -f synthesis_dpt synthesis_dpt_gates
#
#
# LVX : Netlist comparison.
# =========================
#
synthesis_lvx: synthesis_dpt.vst synthesis_dpt_gates.al
$(LVX) vst al synthesis_dpt synthesis_dpt_gates -f
#
#
# LYNX : Transistor netlist extraction.
# =====================================
#
synthesis_dpt.al: synthesis_dpt.ap
$(LYNX) -v -t synthesis_dpt synthesis_dpt
#
#
# DESB : Behavioral exctraction.
# ==============================
#
synthesis_dpt_desb.vbe: synthesis_dpt.inf synthesis_dpt.al
$(DESB) synthesis_dpt synthesis_dpt_desb -v -i
#
#
# PROOF : Formal proof.
# =====================
#
synthesis_proof: sample_dpt.vbe synthesis_dpt_desb.vbe
$(PROOF) -d sample_dpt synthesis_dpt_desb
## ************** Rules for Data-Path using user defined column **************
#
#
# FpGen : Generation of the Netlist.
# ==================================
#
usercol_dpt.vst: usercol_dpt.c
$(FPGEN) -v usercol_dpt
#
#
# DPR : Routing the data-path.
# ============================
#
usercol_dpt.ap: usercol_dpt.dpr usercol_dpt.vst
$(DPR) -V -p -r usercol_dpt usercol_dpt
#
#
# DRUC : Symbolic Design RUles Checker.
# =====================================
#
usercol_druc: usercol_dpt.ap
$(DRUC) usercol_dpt
#
#
# LYNX : Gate level netlist extraction.
# =====================================
#
usercol_dpt_gates.al: usercol_dpt.ap
$(LYNX) -v -f usercol_dpt usercol_dpt_gates
#
#
# LVX : Netlist comparison.
# =========================
#
usercol_lvx: usercol_dpt.vst usercol_dpt_gates.al
$(LVX) vst al usercol_dpt usercol_dpt_gates -f
#
#
# LYNX : Transistor netlist extraction.
# =====================================
#
usercol_dpt.al: usercol_dpt.ap
$(LYNX) -v -t usercol_dpt usercol_dpt
#
#
# DESB : Behavioral exctraction.
# ==============================
#
usercol_dpt_desb.vbe: usercol_dpt.inf usercol_dpt.al
$(DESB) usercol_dpt usercol_dpt_desb -v -i
#
#
# PROOF : Formal proof.
# =====================
#
usercol_proof: sample_dpt.vbe usercol_dpt_desb.vbe
$(PROOF) -d sample_dpt usercol_dpt_desb
## *************************** Miscellaneous Rules ***************************
#
# Removing all generated files.
# =============================
#
clean:
rm -Rf *_desb.vbe \
*_opt.vbe \
*_bk.vbe \
*_cl.vbe \
*.vst \
*.hns \
*.fne \
*.err \
*.grr \
*.frr \
*.rep \
*.drc \
*.gds \
*.cif \
*.fcf \
*.deb \
*.dsbr \
*.al \
*.ap \
*.cp \
CATAL \
core \
Makefile-* \
$(FPGEN_LIB)/*

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6. FpGen/DPR (Data-Path package) in the subdirectory "datapath".
This tutorial presents tools and methodology to design data-path with
Alliance. The two tools are:
1 - FpGen : Data-Path netlists description language based upon C.
(similar to GenLib)
2 - DPR : Place and route tool dedicated to Data-Path.
The Data-Path choosen as example is derivated from the "ADDACCU" tutorial.
We show five differents ways to build this Data-Path. Each way using a
specific Data-Path features. The five examples are the followings:
1 - sample_dpt : Basic Data-Path, use only standart features.
2 - place_dpt : Data-Path using optimized placement.
3 - usercol_dpt : Data-Path using a customized operator.
4 - synthesis_dpt : Using logical synthesis to design a Data-Path
operator.
5 - hierarchy_dpt : Using a hierarchical approach to describe a
datapath netlist.
To automatically build the examples fives shell scripts and a makefile
are provided.

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-- ###---------------------------------------------------------------------###
-- # #
-- # Alliance CAD System V.R #
-- # FpGen Package V.RR #
-- # #
-- # Copyright(c) 93-AA, MASI, CAO-VLSI Team #
-- # #
-- # Author : Jean-Paul CHAPUT #
-- # E-mail : cao-vlsi@masi.ibp.fr #
-- # ======================================================================= #
-- # File : "adder_us.vbe" #
-- # *********************************************************************** #
-- # Adder behavioral description. #
-- # #
-- ###---------------------------------------------------------------------###
ENTITY adder_us IS
-- The order of the terminals must be the same as in the FpGen
-- Macro-Function : DP_ADD2F (that generate "add2f_8x8x0l_bk").
PORT(
a : in BIT_VECTOR(7 downto 0);
b : in BIT_VECTOR(7 downto 0);
cout_n : out BIT;
over_n : out BIT;
s : out BIT_VECTOR(7 downto 0);
vdd : in BIT;
vss : in BIT
);
END adder_us;
ARCHITECTURE behavior_data_flow OF adder_us IS
SIGNAL cry : BIT_VECTOR(8 downto 0);
BEGIN
cry(0) <= '0';
cry(8 downto 1) <= (a and b)
or (a and cry(7 downto 0))
or (b and cry(7 downto 0));
s <= a xor b xor cry(7 downto 0);
over_n <= not cry(7);
cout_n <= not cry(8);
ASSERT((vdd = '1') and (vss = '0'))
REPORT "Power supply is missing on adder_us"
SEVERITY WARNING;
END behavior_data_flow;

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/* Alliance CAD System V.R */
/* FpGen Package V.RR */
/* */
/* Copyright(c) 93-AA, MASI, CAO-VLSI Team */
/* */
/* Author : Jean-Paul CHAPUT */
/* E-mail : cao-vlsi@masi.ibp.fr */
/* ======================================================================== */
/* File : "hierarchy_dpt.c" */
/* ************************************************************************ */
/* Data-Path sample example. */
#include <genlib.h>
#include <fpgen.h>
static void mkSubDP();
static void mkSubDP()
{
/* Open the ALU part of the Data-Path.
* ===================================
*/
DP_DEFLOFIG( "alu_dpt", 8, LSB_INDEX_ZERO );
/* Interface description.
* ======================
*/
/* Control terminals declarations. */
DP_LOCON( "ctrl_ncout", OUT, "ctrl_ncout" );
DP_LOCON( "ctrl_nover", OUT, "ctrl_nover" );
DP_LOCON( "ctrl_zero" , OUT, "ctrl_zero" );
/* Data terminals declarations. */
DP_LOCON( "data_a[7:0]" , IN , "data_a[7:0]" );
DP_LOCON( "data_b[7:0]" , IN , "data_b[7:0]" );
DP_LOCON( "data_s[7:0]" , INOUT, "data_s[7:0]" );
/* Power supplies terminals. */
DP_LOCON( "vdd", IN , "vdd" );
DP_LOCON( "vss", IN , "vss" );
/* Data-Path netlist description.
* ==============================
*/
/* Fast Adder. */
DP_ADD2F( "adder",
"data_a[7:0]",
"data_b[7:0]",
"ctrl_ncout",
"ctrl_nover",
"data_s[7:0]",
EOL );
/* Zero Detect. */
DP_NUL( "zero", 8, 0,
"data_s[7:0]",
"ctrl_zero",
EOL );
/* Terminate the netlist description, and save on disk.
* ====================================================
*/
DP_SAVLOFIG();
}
main()
{
/* Generate the Zero Detect Column.
* ================================
*/
mkSubDP();
/* Open a new Data-Path figure.
* ============================
*/
DP_DEFLOFIG( "hierarchy_dpt", 8, LSB_INDEX_ZERO );
/* Interface description.
* ======================
*/
/* Control terminals declarations. */
DP_LOCON( "ctrl_sel" , IN , "ctrl_sel" );
DP_LOCON( "ctrl_ck" , IN , "ctrl_ck" );
DP_LOCON( "ctrl_wen" , IN , "ctrl_wen" );
DP_LOCON( "ctrl_ncout", OUT, "ctrl_ncout" );
DP_LOCON( "ctrl_nover", OUT, "ctrl_nover" );
DP_LOCON( "ctrl_zero" , OUT, "ctrl_zero" );
/* Data terminals declarations. */
DP_LOCON( "data_a[7:0]" , IN , "data_a[7:0]" );
DP_LOCON( "data_b[7:0]" , IN , "data_b[7:0]" );
DP_LOCON( "data_s[7:0]" , INOUT, "data_s[7:0]" );
/* Power supplies terminals. */
DP_LOCON( "vdd", IN , "vdd" );
DP_LOCON( "vss", IN , "vss" );
/* Data-Path netlist description.
* ==============================
*/
DP_TRACE( TRACE_ON );
/* Multiplexer. */
DP_MUX2CS( "multiplexer", 8, 0,
"ctrl_sel",
"data_b[7:0]",
"data_q[7:0]",
"data_m[7:0]",
EOL );
/* Fast Adder. */
DP_IMPORT( "alu_dpt",
"alu",
"ctrl_ncout",
"ctrl_nover",
"ctrl_zero",
"data_a[7:0]",
"data_m[7:0]",
"data_s[7:0]",
EOL );
/* Register. */
DP_PDFF( "memory", 8, 0,
"ctrl_wen",
"ctrl_ck",
"data_s[7:0]",
"data_q[7:0]",
"data_u[7:0]", /* This bus is unused. */
EOL );
DP_TRACE( TRACE_OFF );
/* Terminate the netlist description, and save on disk.
* ====================================================
*/
DP_SAVLOFIG();
/* A good C program must always terminate by an "exit(0)". */
exit(0);
}

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alliance/share/tutorials/fitpath/hierarchy_dpt.dpr Normal file
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#
#
# /* Alliance CAD System V.R */
# /* FpGen Package V.RR */
# /* */
# /* Copyright(c) 93-AA, MASI, CAO-VLSI Team */
# /* */
# /* Author : Jean-Paul CHAPUT */
# /* E-mail : cao-vlsi@masi.ibp.fr */
# /* ====================================================================== */
# /* File : "hierarchy_dpt.dpr" */
# /* ********************************************************************** */
# /* Hierarchical Data-Path example. */
#
#
# Terminal : Side : Slice : Track
DP_LOCON ctrl_zero NORTH DEFAULT DEFAULT
#
#
# Terminal : Side : Slice : Track
DP_LOCON data_a[7:0] WEST DEFAULT DEFAULT
DP_LOCON data_b[7:0] WEST DEFAULT DEFAULT
DP_LOCON data_s[7:0] EAST DEFAULT DEFAULT
#
#
# Number of vertical power refreshment.
DP_POWER 1 50

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RENAME
memory.pdff_*.memm_s : memory_m(*) ;
memory.pdff_*.mems_s : memory_s(*) ;
END

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#!/bin/sh
#
#
# /* Alliance CAD System V.R */
# /* FpGen Package V.RR */
# /* */
# /* Copyright(c) 93-AA, MASI, CAO-VLSI Team */
# /* */
# /* Author : Jean-Paul CHAPUT */
# /* E-mail : cao-vlsi@masi.ibp.fr */
# /* ====================================================================== */
# /* File : "hierarchy_dpt.sh" */
# /* ********************************************************************** */
# /* Data-Path using hierarchical description. */
#
#
# Installation Dependent Variables.
TOP=/labo
# FpGen Macro-Operators Library.
FPGEN_LIB=./mclib; export FPGEN_LIB
# MBK Enviroment variables settings.
MBK_IN_PH=ap; export MBK_IN_PH
MBK_IN_LO=vst; export MBK_IN_LO
MBK_OUT_PH=ap; export MBK_OUT_PH
MBK_OUT_LO=vst; export MBK_OUT_LO
MBK_WORK_LIB=.; export MBK_WORK_LIB
MBK_CATA_LIB=$TOP/cells/fitpath/fplib:$TOP/cells/rsa:$FPGEN_LIB
export MBK_CATA_LIB
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
MBK_VDD=vdd; export MBK_VDD
MBK_VSS=vss; export MBK_VSS
#
#
# FpGen : Generation of the Netlist.
# ==================================
#
fpgen -v hierarchy_dpt
#
#
# DPR : Routing the data-path.
# ============================
#
dpr -V -p -o -r hierarchy_dpt hierarchy_dpt
#
#
# DRUC : Symbolic Design RUles Checker.
# =====================================
#
druc sample_dpt
#
#
# LYNX : Gate level netlist extraction.
# =====================================
#
MBK_OUT_LO=al
MBK_IN_LO=al
lynx -v -f hierarchy_dpt hierarchy_dpt_gates
#
#
# LVX : Netlist comparison.
# =========================
#
lvx vst al hierarchy_dpt hierarchy_dpt_gates -f
#
#
# LYNX : Transistor netlist extraction.
# =====================================
#
lynx -v -t hierarchy_dpt hierarchy_dpt
#
#
# DESB : Behavioral exctraction.
# ==============================
#
desb hierarchy_dpt hierarchy_dpt_desb -v -i
#
#
# PROOF : Formal proof.
# =====================
#
proof -d sample_dpt hierarchy_dpt_desb

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/* Alliance CAD System V.R */
/* FpGen Package V.RR */
/* */
/* Copyright(c) 93-AA, MASI, CAO-VLSI Team */
/* */
/* Author : Jean-Paul CHAPUT */
/* E-mail : cao-vlsi@masi.ibp.fr */
/* ======================================================================== */
/* File : "sample_dpt.c" */
/* ************************************************************************ */
/* Data-Path sample example. */
#include <genlib.h>
#include <fpgen.h>
main()
{
/* Open a new Data-Path figure.
* ============================
*/
DP_DEFLOFIG( "place_dpt", 8, LSB_INDEX_ZERO );
/* Interface description.
* ======================
*/
/* Control terminals declarations. */
DP_LOCON( "ctrl_sel" , IN , "ctrl_sel" );
DP_LOCON( "ctrl_ck" , IN , "ctrl_ck" );
DP_LOCON( "ctrl_wen" , IN , "ctrl_wen" );
DP_LOCON( "ctrl_ncout", OUT, "ctrl_ncout" );
DP_LOCON( "ctrl_nover", OUT, "ctrl_nover" );
DP_LOCON( "ctrl_zero" , OUT, "ctrl_zero" );
/* Data terminals declarations. */
DP_LOCON( "data_a[7:0]" , IN , "data_a[7:0]" );
DP_LOCON( "data_b[7:0]" , IN , "data_b[7:0]" );
DP_LOCON( "data_s[7:0]" , INOUT, "data_s[7:0]" );
/* Power supplies terminals. */
DP_LOCON( "vdd", IN , "vdd" );
DP_LOCON( "vss", IN , "vss" );
/* Data-Path netlist description.
* ==============================
*/
DP_TRACE( TRACE_ON );
/* Zero Detect. */
DP_NUL( "zero", 8, 0,
"data_s[7:0]",
"ctrl_zero",
EOL );
/* Multiplexer. */
DP_MUX2CS( "multiplexer", 8, 0,
"ctrl_sel",
"data_b[7:0]",
"data_q[7:0]",
"data_m[7:0]",
EOL );
/* Fast Adder. */
DP_ADD2F( "adder",
"data_a[7:0]",
"data_m[7:0]",
"ctrl_ncout",
"ctrl_nover",
"data_s[7:0]",
EOL );
/* Register. */
DP_PDFF( "memory", 8, 0,
"ctrl_wen",
"ctrl_ck",
"data_s[7:0]",
"data_q[7:0]",
"data_u[7:0]", /* This bus is unused. */
EOL );
DP_TRACE( TRACE_OFF );
/* Terminate the netlist description, and save on disk.
* ====================================================
*/
DP_SAVLOFIG();
/* A good C program must always terminate by an "exit(0)". */
exit(0);
}

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#
#
# /* Alliance CAD System V.R */
# /* FpGen Package V.RR */
# /* */
# /* Copyright(c) 93-AA, MASI, CAO-VLSI Team */
# /* */
# /* Author : Jean-Paul CHAPUT */
# /* E-mail : cao-vlsi@masi.ibp.fr */
# /* ====================================================================== */
# /* File : "place_dpt.dpr" */
# /* ********************************************************************** */
# /* Data-Path sample example. */
#
#
# Terminal : Side : Slice : Track
DP_LOCON ctrl_zero NORTH DEFAULT DEFAULT
#
#
# Terminal : Side : Slice : Track
DP_LOCON data_a[7:0] WEST DEFAULT DEFAULT
DP_LOCON data_b[7:0] WEST DEFAULT DEFAULT
DP_LOCON data_s[7:0] EAST DEFAULT DEFAULT
#
#
# Number of vertical power refreshment.
DP_POWER 1 50

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RENAME
memory.pdff_*.memm_s : memory_m(*) ;
memory.pdff_*.mems_s : memory_s(*) ;
END

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#!/bin/sh
#
#
# /* Alliance CAD System V.R */
# /* FpGen Package V.RR */
# /* */
# /* Copyright(c) 93-AA, MASI, CAO-VLSI Team */
# /* */
# /* Author : Jean-Paul CHAPUT */
# /* E-mail : cao-vlsi@masi.ibp.fr */
# /* ====================================================================== */
# /* File : "place_dpt.sh" */
# /* ********************************************************************** */
# /* Data-Path using optimized placement example. */
#
#
# Installation Dependent Variables.
TOP=/labo
# FpGen Macro-Operators Library.
FPGEN_LIB=./mclib; export FPGEN_LIB
# MBK Enviroment variables settings.
MBK_IN_PH=ap; export MBK_IN_PH
MBK_IN_LO=vst; export MBK_IN_LO
MBK_OUT_PH=ap; export MBK_OUT_PH
MBK_OUT_LO=vst; export MBK_OUT_LO
MBK_WORK_LIB=.; export MBK_WORK_LIB
MBK_CATA_LIB=$TOP/cells/fitpath/fplib:$TOP/cells/rsa:$FPGEN_LIB
export MBK_CATA_LIB
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
MBK_VDD=vdd; export MBK_VDD
MBK_VSS=vss; export MBK_VSS
#
#
# FpGen : Generation of the Netlist.
# ==================================
#
fpgen -v place_dpt
#
#
# DPR : Routing the data-path.
# ============================
#
dpr -V -p -o -r place_dpt place_dpt
#
#
# DRUC : Symbolic Design RUles Checker.
# =====================================
#
druc sample_dpt
#
#
# LYNX : Gate level netlist extraction.
# =====================================
#
MBK_OUT_LO=al
MBK_IN_LO=al
lynx -v -f place_dpt place_dpt_gates
#
#
# LVX : Netlist comparison.
# =========================
#
lvx vst al place_dpt place_dpt_gates -f
#
#
# LYNX : Transistor netlist extraction.
# =====================================
#
lynx -v -t place_dpt place_dpt
#
#
# DESB : Behavioral exctraction.
# ==============================
#
desb place_dpt place_dpt_desb -v -i
#
#
# PROOF : Formal proof.
# =====================
#
proof -d sample_dpt place_dpt_desb

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/* Alliance CAD System V.R */
/* FpGen Package V.RR */
/* */
/* Copyright(c) 93-AA, MASI, CAO-VLSI Team */
/* */
/* Author : Jean-Paul CHAPUT */
/* E-mail : cao-vlsi@masi.ibp.fr */
/* ======================================================================== */
/* File : "sample_dpt.c" */
/* ************************************************************************ */
/* Data-Path sample example. */
#include <genlib.h>
#include <fpgen.h>
main()
{
/* DP_TRACE( TRACE_OFF ); */
/* Open a new Data-Path figure.
* ============================
*/
DP_DEFLOFIG( "sample_dpt", 8, LSB_INDEX_ZERO );
/* Interface description.
* ======================
*/
/* Control terminals declarations. */
DP_LOCON( "ctrl_sel" , IN , "ctrl_sel" );
DP_LOCON( "ctrl_ck" , IN , "ctrl_ck" );
DP_LOCON( "ctrl_wen" , IN , "ctrl_wen" );
DP_LOCON( "ctrl_ncout", OUT, "ctrl_ncout" );
DP_LOCON( "ctrl_nover", OUT, "ctrl_nover" );
DP_LOCON( "ctrl_zero" , OUT, "ctrl_zero" );
/* Data terminals declarations. */
DP_LOCON( "data_a[7:0]" , IN , "data_a[7:0]" );
DP_LOCON( "data_b[7:0]" , IN , "data_b[7:0]" );
DP_LOCON( "data_s[7:0]" , INOUT, "data_s[7:0]" );
/* Power supplies terminals. */
DP_LOCON( "vdd", IN , "vdd" );
DP_LOCON( "vss", IN , "vss" );
/* Data-Path netlist description.
* ==============================
*/
/* Multiplexer. */
DP_MUX2CS( "multiplexer", 8, 0,
"ctrl_sel",
"data_b[7:0]",
"data_q[7:0]",
"data_m[7:0]",
EOL );
/* Fast Adder. */
DP_ADD2F( "adder",
"data_a[7:0]",
"data_m[7:0]",
"ctrl_ncout",
"ctrl_nover",
"data_s[7:0]",
EOL );
/* Zero Detect. */
DP_NUL( "zero", 8, 0,
"data_s[7:0]",
"ctrl_zero",
EOL );
/* Register. */
DP_PDFF( "memory", 8, 0,
"ctrl_wen",
"ctrl_ck",
"data_s[7:0]",
"data_q[7:0]",
"data_u[7:0]", /* This bus is unused. */
EOL );
/* Terminate the netlist description, and save on disk.
* ====================================================
*/
DP_SAVLOFIG();
/* DP_TRACE( TRACE_OFF ); */
/* A good C program must always terminate by an "exit(0)". */
exit(0);
}

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#
#
# /* Alliance CAD System V.R */
# /* FpGen Package V.RR */
# /* */
# /* Copyright(c) 93-AA, MASI, CAO-VLSI Team */
# /* */
# /* Author : Jean-Paul CHAPUT */
# /* E-mail : cao-vlsi@masi.ibp.fr */
# /* ====================================================================== */
# /* File : "sample_dpt.dpr" */
# /* ********************************************************************** */
# /* Data-Path sample example. */
#
#
# Terminal : Side : Slice : Track
DP_LOCON ctrl_zero NORTH DEFAULT DEFAULT
#
#
# Terminal : Side : Slice : Track
DP_LOCON data_a[7:0] WEST DEFAULT DEFAULT
DP_LOCON data_b[7:0] WEST DEFAULT DEFAULT
DP_LOCON data_s[7:0] EAST DEFAULT DEFAULT
#
#
# Number of vertical power refreshment.
DP_POWER 1 50

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RENAME
memory.pdff_*.memm_s : memory_m(*) ;
memory.pdff_*.mems_s : memory_s(*) ;
END

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--
--
-- /* Alliance CAD System V.R */
-- /* FpGen Package V.RR */
-- /* */
-- /* Copyright(c) 93-AA, MASI, CAO-VLSI Team */
-- /* */
-- /* Author : Jean-Paul CHAPUT */
-- /* E-mail : cao-vlsi@masi.ibp.fr */
-- /* ===================================================================== */
-- /* File : "sample_dpt.c" */
-- /* ********************************************************************* */
-- /* Data-Path sample example. */
--
--
in ctrl_sel;;
in ctrl_ck;
in ctrl_wen;;
out ctrl_ncout;
out ctrl_nover;
out ctrl_zero;;
in data_a(7 downto 0) X;;
in data_b(7 downto 0) X;;
out data_s(7 downto 0) X;;
in vdd;
in vss;;
BEGIN
check_adder: 1 00 ?1?1?1 00 00 ?00 10;
: 1 00 ?1?1?0 01 00 ?01 10;
: 1 00 ?1?1?0 02 00 ?02 10;
: 1 00 ?1?1?0 03 00 ?03 10;
: 1 00 ?1?1?0 04 00 ?04 10;
: 1 00 ?1?1?0 05 00 ?05 10;
: 1 00 ?1?1?0 06 00 ?06 10;
: 1 00 ?1?1?0 07 00 ?07 10;
: 1 00 ?1?1?0 08 00 ?08 10;
: 1 00 ?1?1?0 09 00 ?09 10;
: 1 00 ?1?1?0 0A 00 ?0A 10;
: 1 00 ?1?1?0 0B 00 ?0B 10;
: 1 00 ?1?1?0 0C 00 ?0C 10;
: 1 00 ?1?1?0 0D 00 ?0D 10;
: 1 00 ?1?1?0 0E 00 ?0E 10;
: 1 00 ?1?1?0 0F 00 ?0F 10;
: 1 00 ?1?1?0 10 00 ?10 10;
: 1 00 ?1?1?0 20 00 ?20 10;
: 1 00 ?1?1?0 30 00 ?30 10;
: 1 00 ?1?1?0 40 00 ?40 10;
: 1 00 ?1?1?0 50 00 ?50 10;
: 1 00 ?1?1?0 60 00 ?60 10;
: 1 00 ?1?1?0 70 00 ?70 10;
: 1 00 ?1?1?0 80 00 ?80 10;
: 1 00 ?1?1?0 90 00 ?90 10;
: 1 00 ?1?1?0 A0 00 ?A0 10;
: 1 00 ?1?1?0 B0 00 ?B0 10;
: 1 00 ?1?1?0 C0 00 ?C0 10;
: 1 00 ?1?1?0 D0 00 ?D0 10;
: 1 00 ?1?1?0 E0 00 ?E0 10;
: 1 00 ?1?1?0 F0 00 ?F0 10;
: 1 00 ?1?1?0 FE 00 ?FE 10;
: 1 00 ?1?1?0 FF 00 ?FF 10;
check_ncout: 1 00 ?0?1?0 FF 80 ?7F 10;
check_nover: 1 00 ?0?0?0 FF 40 ?3F 10;
END;

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#!/bin/sh
#
#
# /* Alliance CAD System V.R */
# /* FpGen Package V.RR */
# /* */
# /* Copyright(c) 93-AA, MASI, CAO-VLSI Team */
# /* */
# /* Author : Jean-Paul CHAPUT */
# /* E-mail : cao-vlsi@masi.ibp.fr */
# /* ====================================================================== */
# /* File : "sample_dpt.sh" */
# /* ********************************************************************** */
# /* Data-Path sample example. */
#
#
# Installation Dependent Variables.
TOP=/labo
# FpGen Macro-Operators Library.
FPGEN_LIB=./mclib; export FPGEN_LIB
# MBK Enviroment variables settings.
MBK_IN_PH=ap; export MBK_IN_PH
MBK_IN_LO=vst; export MBK_IN_LO
MBK_OUT_PH=ap; export MBK_OUT_PH
MBK_OUT_LO=vst; export MBK_OUT_LO
MBK_WORK_LIB=.; export MBK_WORK_LIB
MBK_CATA_LIB=$TOP/cells/fitpath/fplib:$TOP/cells/rsa:$FPGEN_LIB
export MBK_CATA_LIB
MBK_CATAL_NAME=MON_CATAL; export MBK_CATAL_NAME
MBK_VDD=vdd; export MBK_VDD
MBK_VSS=vss; export MBK_VSS
#
#
# FpGen : Generation of the Netlist.
# ==================================
#
fpgen -v --dev sample_dpt
#
#
# DPR : Routing the data-path.
# ============================
#
dpr -V -p -r sample_dpt sample_dpt
#
#
# DRUC : Symbolic Design RUles Checker.
# =====================================
#
druc sample_dpt
#
#
# LYNX : Gate level netlist extraction.
# =====================================
#
MBK_OUT_LO=al
MBK_IN_LO=al
lynx -v -f sample_dpt sample_dpt_gates
#
#
# LVX : Netlist comparison.
# =========================
#
lvx vst al sample_dpt sample_dpt_gates -f
#
#
# LYNX : Transistor netlist extraction.
# =====================================
#
lynx -v -t sample_dpt sample_dpt
#
#
# DESB : Behavioral exctraction.
# ==============================
#
desb sample_dpt sample_dpt_desb -v -i
#
#
# PROOF : Formal proof.
# =====================
#
proof -d sample_dpt sample_dpt_desb

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-- ###---------------------------------------------------------------------###
-- # #
-- # Alliance CAD System V.R #
-- # FpGen Package V.RR #
-- # #
-- # Copyright(c) 93-AA, MASI, CAO-VLSI Team #
-- # #
-- # Author : Jean-Paul CHAPUT #
-- # E-mail : cao-vlsi@masi.ibp.fr #
-- # ======================================================================= #
-- # File : "sample_dpt.vbe" #
-- # *********************************************************************** #
-- # Data-Path sample example. #
-- # #
-- ###---------------------------------------------------------------------###
ENTITY sample_dpt IS
PORT(
-- Control terminals declarations.
ctrl_sel : in BIT;
ctrl_ck : in BIT;
ctrl_wen : in BIT;
ctrl_ncout : out BIT;
ctrl_nover : out BIT;
ctrl_zero : out BIT;
-- Data terminals declarations.
data_a : in BIT_VECTOR(7 downto 0);
data_b : in BIT_VECTOR(7 downto 0);
data_s : inout BIT_VECTOR(7 downto 0);
-- Power supplies terminals.
vdd : in BIT;
vss : in BIT
);
END sample_dpt;
ARCHITECTURE behavior_data_flow OF sample_dpt IS
SIGNAL wmd : BIT;
SIGNAL ws : BIT;
SIGNAL memory_m : REG_VECTOR(7 downto 0) REGISTER;
SIGNAL memory_s : REG_VECTOR(7 downto 0) REGISTER;
SIGNAL cry : BIT_VECTOR(8 downto 0);
SIGNAL dwen : BIT_VECTOR(7 downto 0);
SIGNAL data_m : BIT_VECTOR(7 downto 0);
SIGNAL data_q : BIT_VECTOR(7 downto 0);
BEGIN
-- Multiplexer (related to DP_MUX2CS).
WITH ctrl_sel SELECT
data_m <= data_b WHEN '1',
data_q WHEN '0';
-- Fast Adder (related to ADD2F).
cry(0) <= '0';
cry(8 downto 1) <= (data_m and data_a)
or (data_m and cry(7 downto 0))
or (data_a and cry(7 downto 0));
data_s <= data_m xor data_a xor cry(7 downto 0);
ctrl_nover <= not cry(7);
ctrl_ncout <= not cry(8);
-- Zero Detect (related to DP_NUL).
WITH data_s SELECT
ctrl_zero <= '1' WHEN B"00000000",
'0' WHEN OTHERS;
-- Register (related to DP_PDFF).
wmd <= ctrl_ck;
ws <= not ctrl_ck;
WITH ctrl_wen SELECT
dwen <= data_s WHEN '1',
data_q WHEN '0';
wmd:BLOCK( wmd ) BEGIN memory_m <= GUARDED not dwen; END BLOCK wmd;
ws :BLOCK( ws ) BEGIN memory_s <= GUARDED memory_m; END BLOCK ws;
data_q <= not memory_s;
ASSERT((vdd = '1') and (vss = '0'))
REPORT "Power supply is missing on sample_dpt"
SEVERITY WARNING;
END behavior_data_flow;

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-- ###---------------------------------------------------------------------###
-- # #
-- # Alliance CAD System V.R #
-- # FpGen Package V.RR #
-- # #
-- # Copyright(c) 93-AA, MASI, CAO-VLSI Team #
-- # #
-- # Author : Jean-Paul CHAPUT #
-- # E-mail : cao-vlsi@masi.ibp.fr #
-- # ======================================================================= #
-- # File : "sample_dpt.vbe" #
-- # *********************************************************************** #
-- # Data-Path sample example. #
-- # #
-- ###---------------------------------------------------------------------###
ENTITY sample_dpt IS
PORT(
-- Control terminals declarations.
ctrl_sel : in BIT;
ctrl_ck : in BIT;
ctrl_wen : in BIT;
ctrl_ncout : out BIT;
ctrl_nover : out BIT;
ctrl_zero : out BIT;
-- Data terminals declarations.
data_a : in BIT_VECTOR(7 downto 0);
data_b : in BIT_VECTOR(7 downto 0);
data_s : inout BIT_VECTOR(7 downto 0);
-- Power supplies terminals.
vdd : in BIT;
vss : in BIT
);
END sample_dpt;
ARCHITECTURE behavior_data_flow OF sample_dpt IS
SIGNAL wmd : BIT;
SIGNAL ws : BIT;
SIGNAL memory_m : REG_VECTOR(7 downto 0) REGISTER;
SIGNAL memory_s : REG_VECTOR(7 downto 0) REGISTER;
SIGNAL cry : BIT_VECTOR(8 downto 0);
SIGNAL dwen : BIT_VECTOR(7 downto 0);
SIGNAL data_m : BIT_VECTOR(7 downto 0);
SIGNAL data_q : BIT_VECTOR(7 downto 0);
BEGIN
-- Multiplexer (related to DP_MUX2CS).
WITH ctrl_sel SELECT
data_m <= data_b WHEN '1',
data_q WHEN '0';
-- Fast Adder (related to ADD2F).
cry(0) <= '0';
cry(8 downto 1) <= (data_m and data_a)
or (data_m and cry(7 downto 0))
or (data_a and cry(7 downto 0));
data_s <= data_m xor data_a xor cry(7 downto 0);
ctrl_nover <= not cry(7);
ctrl_ncout <= not cry(8);
-- Zero Detect (related to DP_NUL).
WITH data_s SELECT
ctrl_zero <= '1' WHEN B"00000000",
'0' WHEN OTHERS;
-- Register (related to DP_PDFF).
wmd <= not (not (ctrl_ck) or not (ctrl_wen)) ;
ws <= not ctrl_ck;
WITH ctrl_wen SELECT
dwen <= data_s WHEN '1',
data_q WHEN '0';
wmd:BLOCK( wmd ) BEGIN memory_m <= GUARDED not data_s; END BLOCK wmd;
ws :BLOCK( ws ) BEGIN memory_s <= GUARDED memory_m; END BLOCK ws;
data_q <= not memory_s;
ASSERT((vdd = '1') and (vss = '0'))
REPORT "Power supply is missing on sample_dpt"
SEVERITY WARNING;
END behavior_data_flow;

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/* Alliance CAD System V.R */
/* FpGen Package V.RR */
/* */
/* Copyright(c) 93-AA, MASI, CAO-VLSI Team */
/* */
/* Author : Jean-Paul CHAPUT */
/* E-mail : cao-vlsi@masi.ibp.fr */
/* ======================================================================== */
/* File : "synthesis_dpt.c" */
/* ************************************************************************ */
/* Example of synthesis inside a Data-Path. */
#include <genlib.h>
#include <fpgen.h>
main()
{
/* Open a new Data-Path figure.
* ============================
*/
DP_DEFLOFIG( "synthesis_dpt", 8, LSB_INDEX_ZERO );
/* Interface description.
* ======================
*/
/* Control terminals declarations. */
DP_LOCON( "ctrl_sel" , IN , "ctrl_sel" );
DP_LOCON( "ctrl_ck" , IN , "ctrl_ck" );
DP_LOCON( "ctrl_wen" , IN , "ctrl_wen" );
DP_LOCON( "ctrl_ncout", OUT, "ctrl_ncout" );
DP_LOCON( "ctrl_nover", OUT, "ctrl_nover" );
DP_LOCON( "ctrl_zero" , OUT, "ctrl_zero" );
/* Data terminals declarations. */
DP_LOCON( "data_a[7:0]" , IN , "data_a[7:0]" );
DP_LOCON( "data_b[7:0]" , IN , "data_b[7:0]" );
DP_LOCON( "data_s[7:0]" , INOUT, "data_s[7:0]" );
/* Power supplies terminals. */
DP_LOCON( "vdd", IN , "vdd" );
DP_LOCON( "vss", IN , "vss" );
/* Data-Path netlist description.
* ==============================
*/
DP_TRACE( TRACE_ON );
/* Multiplexer. */
DP_MUX2CS( "multiplexer", 8, 0,
"ctrl_sel",
"data_b[7:0]",
"data_q[7:0]",
"data_m[7:0]",
EOL );
/* Synthetized Adder. */
DP_IMPORT( "adder_us",
"adder",
"data_a[7:0]",
"data_m[7:0]",
"ctrl_ncout",
"ctrl_nover",
"data_s[7:0]",
EOL );
/* Zero Detect. */
DP_NUL( "zero", 8, 0,
"data_s[7:0]",
"ctrl_zero",
EOL );
/* Register. */
DP_PDFF( "memory", 8, 0,
"ctrl_wen",
"ctrl_ck",
"data_s[7:0]",
"data_q[7:0]",
"data_u[7:0]", /* This bus is unused. */
EOL );
DP_TRACE( TRACE_OFF );
/* Terminate the netlist description, and save on disk.
* ====================================================
*/
DP_SAVLOFIG();
/* A good C program must always terminate by an "exit(0)". */
exit(0);
}

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#
#
# /* Alliance CAD System V.R */
# /* FpGen Package V.RR */
# /* */
# /* Copyright(c) 93-AA, MASI, CAO-VLSI Team */
# /* */
# /* Author : Jean-Paul CHAPUT */
# /* E-mail : cao-vlsi@masi.ibp.fr */
# /* ====================================================================== */
# /* File : "synthesis_dpt.dpr" */
# /* ********************************************************************** */
# /* Data-Path sample example. */
#
#
# Terminal : Side : Slice : Track
DP_LOCON ctrl_zero NORTH DEFAULT DEFAULT
DP_LOCON ctrl_ncout NORTH DEFAULT DEFAULT
DP_LOCON ctrl_nover NORTH DEFAULT DEFAULT
#
#
# Terminal : Side : Slice : Track
DP_LOCON data_a[7:0] WEST DEFAULT DEFAULT
DP_LOCON data_b[7:0] WEST DEFAULT DEFAULT
DP_LOCON data_s[7:0] EAST DEFAULT DEFAULT
#
#
# Model Name : Iterations : Height : CPC
DP_GLUE adder_us 5000 8 2
#
#
# Number and wide of vertical power refreshment.
DP_POWER 1 50

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RENAME
memory.pdff_*.memm_s : memory_m(*) ;
memory.pdff_*.mems_s : memory_s(*) ;
END

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#!/bin/sh
#
#
# /* Alliance CAD System V.R */
# /* FpGen Package V.RR */
# /* */
# /* Copyright(c) 93-AA, MASI, CAO-VLSI Team */
# /* */
# /* Author : Jean-Paul CHAPUT */
# /* E-mail : cao-vlsi@masi.ibp.fr */
# /* ====================================================================== */
# /* File : "synthesis_dpt.sh" */
# /* ********************************************************************** */
# /* Data-Path using synthetized block example. */
#
#
# Installation Dependent Variables.
TOP=/labo
# FpGen Macro-Operators Library.
FPGEN_LIB=./mclib; export FPGEN_LIB
# MBK Enviroment Variables Settings.
MBK_IN_PH=cp; export MBK_IN_PH
MBK_IN_LO=hns; export MBK_IN_LO
MBK_OUT_PH=cp; export MBK_OUT_PH
MBK_OUT_LO=hns; export MBK_OUT_LO
MBK_WORK_LIB=.; export MBK_WORK_LIB
MBK_CATA_LIB=$FPGEN_LIB
MBK_CATA_LIB=$MBK_CATA_LIB:$TOP/cells/fitpath/fplib
MBK_CATA_LIB=$MBK_CATA_LIB:$TOP/cells/fitpath/dplib/ecpd10
export MBK_CATA_LIB
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
MBK_VDD=vdd; export MBK_VDD
MBK_VSS=vss; export MBK_VSS
# LOGIC Environment Variables.
MBK_TARGET_LIB=$TOP/cells/fitpath/dplib/ecpd10
export MBK_TARGET_LIB
MBK_NAME_LOG=""; export MBK_NAME_LOG
#
#
# Logic : Synthesis of the Adder.
# ===============================
# Two steps :
# 1) Optimise data-flow equations.
# 2) Synthesis, using TARGET library.
#
logic -o adder_us adder_us_opt
logic -s adder_us_opt adder_us
#
#
# FpGen : Generation of the Netlist.
# ==================================
#
fpgen --dev -v synthesis_dpt
#
#
# DPR : Routing the data-path.
# ============================
#
dpr -V -p -r synthesis_dpt synthesis_dpt
#
#
# DRUC : Symbolic Design RUles Checker.
# =====================================
#
druc synthesis_dpt
#
#
# LYNX : Gate level netlist extraction.
# =====================================
#
MBK_OUT_LO=al
MBK_IN_LO=al
lynx -v -f synthesis_dpt synthesis_dpt_gates
#
#
# LVX : Netlist comparison.
# =========================
#
lvx hns al synthesis_dpt synthesis_dpt_gates -f
#
#
# LYNX : Transistor netlist extraction.
# =====================================
#
lynx -v -t synthesis_dpt synthesis_dpt
#
#
# DESB : Behavioral exctraction.
# ==============================
#
desb synthesis_dpt synthesis_dpt_desb -v -i
#
#
# PROOF : Formal proof.
# =====================
#
proof -d sample_dpt synthesis_dpt_desb

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/* Alliance CAD System V.R */
/* FpGen Package V.RR */
/* */
/* Copyright(c) 93-AA, MASI, CAO-VLSI Team */
/* */
/* Author : Jean-Paul CHAPUT */
/* E-mail : cao-vlsi@masi.ibp.fr */
/* ======================================================================== */
/* File : "usercol_dpt.c" */
/* ************************************************************************ */
/* Example of synthesis inside a Data-Path. */
#include <genlib.h>
#include <fpgen.h>
static void mkZeroDetect();
static void mkZeroDetect()
{
/* Open the GenLib figure (the user data-path column).
* ===================================================
*/
DEF_LOFIG( "nul_us" );
/* Interface description.
* ======================
*/
LOCON( "i0[7:0]", IN , "i0[7:0]" );
LOCON( "zero" , OUT, "zero" );
LOCON( "vdd" , IN , "vdd" );
LOCON( "vss" , IN , "vss" );
/* 8 bits Zero Detect netlist description.
* =======================================
*/
LOINS( "no2_dp", "no2_0", "i0[0]", "i0[1]", "z2_0", "vdd", "vss", 0L );
LOINS( "no2_dp", "no2_2", "i0[2]", "i0[3]", "z2_1", "vdd", "vss", 0L );
LOINS( "no2_dp", "no2_4", "i0[4]", "i0[5]", "z2_2", "vdd", "vss", 0L );
LOINS( "no2_dp", "no2_6", "i0[6]", "i0[7]", "z2_3", "vdd", "vss", 0L );
LOINS( "na2_dp", "na2_1", "z2_0", "z2_1", "z4_0", "vdd", "vss", 0L );
LOINS( "na2_dp", "na2_5", "z2_2", "z2_3", "z4_1", "vdd", "vss", 0L );
LOINS( "no2_dp", "no2_3", "z4_0", "z4_1", "zero", "vdd", "vss", 0L );
/* Terminate the netlist description, and save on disk.
* ====================================================
*/
SAVE_LOFIG();
}
main()
{
/* Generate the Zero Detect Column.
* ================================
*/
mkZeroDetect();
/* Open a new Data-Path figure.
* ============================
*/
DP_DEFLOFIG( "usercol_dpt", 8, LSB_INDEX_ZERO );
/* Interface description.
* ======================
*/
/* Control terminals declarations. */
DP_LOCON( "ctrl_sel" , IN , "ctrl_sel" );
DP_LOCON( "ctrl_ck" , IN , "ctrl_ck" );
DP_LOCON( "ctrl_wen" , IN , "ctrl_wen" );
DP_LOCON( "ctrl_ncout", OUT, "ctrl_ncout" );
DP_LOCON( "ctrl_nover", OUT, "ctrl_nover" );
DP_LOCON( "ctrl_zero" , OUT, "ctrl_zero" );
/* Data terminals declarations. */
DP_LOCON( "data_a[7:0]" , IN , "data_a[7:0]" );
DP_LOCON( "data_b[7:0]" , IN , "data_b[7:0]" );
DP_LOCON( "data_s[7:0]" , INOUT, "data_s[7:0]" );
/* Power supplies terminals. */
DP_LOCON( "vdd", IN , "vdd" );
DP_LOCON( "vss", IN , "vss" );
/* Data-Path netlist description.
* ==============================
*/
DP_TRACE( TRACE_ON );
/* Multiplexer. */
DP_MUX2CS( "multiplexer", 8, 0,
"ctrl_sel",
"data_b[7:0]",
"data_q[7:0]",
"data_m[7:0]",
EOL );
/* Fast Adder. */
DP_ADD2F( "adder",
"data_a[7:0]",
"data_m[7:0]",
"ctrl_ncout",
"ctrl_nover",
"data_s[7:0]",
EOL );
/* Zero Detect. */
DP_IMPORT( "nul_us",
"zero",
"data_s[7:0]",
"ctrl_zero",
EOL );
/* Register. */
DP_PDFF( "memory", 8, 0,
"ctrl_wen",
"ctrl_ck",
"data_s[7:0]",
"data_q[7:0]",
"data_u[7:0]", /* This bus is unused. */
EOL );
DP_TRACE( TRACE_OFF );
/* Terminate the netlist description, and save on disk.
* ====================================================
*/
DP_SAVLOFIG();
/* A good C program must always terminate by an "exit(0)". */
exit(0);
}

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#
#
# /* Alliance CAD System V.R */
# /* FpGen Package V.RR */
# /* */
# /* Copyright(c) 93-AA, MASI, CAO-VLSI Team */
# /* */
# /* Author : Jean-Paul CHAPUT */
# /* E-mail : cao-vlsi@masi.ibp.fr */
# /* ====================================================================== */
# /* File : "usercol_dpt.dpr" */
# /* ********************************************************************** */
# /* Data-Path sample example. */
#
#
# Terminal : Side : Slice : Track
DP_LOCON ctrl_zero NORTH DEFAULT DEFAULT
#
#
# Terminal : Side : Slice : Track
DP_LOCON data_a[7:0] WEST DEFAULT DEFAULT
DP_LOCON data_b[7:0] WEST DEFAULT DEFAULT
DP_LOCON data_s[7:0] EAST DEFAULT DEFAULT
#
#
# Number of vertical power refreshment.
DP_POWER 1 50

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RENAME
memory.pdff_*.memm_s : memory_m(*) ;
memory.pdff_*.mems_s : memory_s(*) ;
END

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#!/bin/sh
#
#
# /* Alliance CAD System V.R */
# /* FpGen Package V.RR */
# /* */
# /* Copyright(c) 93-AA, MASI, CAO-VLSI Team */
# /* */
# /* Author : Jean-Paul CHAPUT */
# /* E-mail : cao-vlsi@masi.ibp.fr */
# /* ====================================================================== */
# /* File : "usercol_dpt.sh" */
# /* ********************************************************************** */
# /* Data-Path using user defined column example. */
#
#
# Installation Dependent Variables.
TOP=/labo
# FpGen Macro-Operators Library.
FPGEN_LIB=./mclib; export FPGEN_LIB
# MBK Enviroment variables settings.
MBK_IN_PH=ap; export MBK_IN_PH
MBK_IN_LO=vst; export MBK_IN_LO
MBK_OUT_PH=ap; export MBK_OUT_PH
MBK_OUT_LO=vst; export MBK_OUT_LO
MBK_WORK_LIB=.; export MBK_WORK_LIB
MBK_CATA_LIB=$FPGEN_LIB
MBK_CATA_LIB=$MBK_CATA_LIB:$TOP/cells/rsa
MBK_CATA_LIB=$MBK_CATA_LIB:$TOP/cells/fitpath/fplib
MBK_CATA_LIB=$MBK_CATA_LIB:$TOP/cells/fitpath/dplib/ecpd10
export MBK_CATA_LIB
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
MBK_VDD=vdd; export MBK_VDD
MBK_VSS=vss; export MBK_VSS
#
#
# FpGen : Generation of the Netlist.
# ==================================
#
fpgen -v usercol_dpt
#
#
# DPR : Routing the data-path.
# ============================
#
dpr -V -p -r usercol_dpt usercol_dpt
#
#
# DRUC : Symbolic Design RUles Checker.
# =====================================
#
druc sample_dpt
#
#
# LYNX : Gate level netlist extraction.
# =====================================
#
MBK_OUT_LO=al
MBK_IN_LO=al
lynx -v -f usercol_dpt usercol_dpt_gates
#
#
# LVX : Netlist comparison.
# =========================
#
lvx vst al usercol_dpt usercol_dpt_gates -f
#
#
# LYNX : Transistor netlist extraction.
# =====================================
#
lynx -v -t usercol_dpt usercol_dpt
#
#
# DESB : Behavioral exctraction.
# ==============================
#
desb usercol_dpt usercol_dpt_desb -v -i
#
#
# PROOF : Formal proof.
# =====================
#
proof -d sample_dpt usercol_dpt_desb