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Corrected behavioral view in order to be simulated with Asimut.

This commit is contained in:
Jean-Paul Chaput 2004-08-31 08:37:17 +00:00
parent a025203d40
commit 8a4b6d3e9d
2 changed files with 112 additions and 40 deletions
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59
alliance/src/cells/src/ramlib/ram_mem_data.vbe
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@ -1,20 +1,49 @@
ENTITY ram_mem_data IS entity RAM_MEM_DATA is
PORT (
selxi : in BIT; port
bit0 : in BIT; (
nbit0 : in BIT; SELXI : in bit ;
bit1 : in BIT; BIT0 : inout wor_bit bus;
nbit1 : in BIT; NBIT0 : inout wor_bit bus;
vdd : in BIT; BIT1 : inout wor_bit bus;
vss : in BIT NBIT1 : inout wor_bit bus;
VDD : in bit ;
VSS : in bit
); );
END ram_mem_data;
ARCHITECTURE VBE OF ram_mem_data IS end RAM_MEM_DATA;
BEGIN architecture vbe of RAM_MEM_DATA is
ASSERT (vdd and not (vss))
REPORT "power supply is missing on ram_mem_data" signal LATCH0 : reg_bit register;
SEVERITY WARNING; signal LATCH1 : reg_bit register;
begin
assert (VDD ='1' and VSS = '0')
report "power supply is missing on ram_mem_data"
severity WARNING;
WRITE_0 : BLOCK ((SELXI and (BIT0 xor NBIT0)) = '1')
begin
LATCH0 <= guarded BIT0;
end block;
WRITE_1 : BLOCK ((SELXI and (BIT1 xor NBIT1)) = '1')
begin
LATCH1 <= guarded BIT1;
end block;
READ_0 : BLOCK ((SELXI and not SELXI'STABLE) = '1')
begin
BIT0 <= guarded LATCH0;
NBIT0 <= guarded not LATCH0;
end block;
READ_1 : BLOCK ((SELXI and not SELXI'STABLE) = '1')
begin
BIT1 <= guarded LATCH1;
NBIT1 <= guarded not LATCH1;
end block;
END; END;

89
alliance/src/cells/src/ramlib/ram_sense_data.vbe
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@ -1,27 +1,70 @@
ENTITY ram_sense_data IS entity RAM_SENSE_DATA is
PORT (
bit0 : in BIT; port
nbit0 : in BIT; (
bit1 : in BIT; bit0 : inout wor_bit bus;
nbit1 : in BIT; Nbit0 : inout wor_bit bus;
ad0x : in BIT; bit1 : inout wor_bit bus;
nad0x : in BIT; Nbit1 : inout wor_bit bus;
sensex : in BIT; AD0X : in bit ;
nsensex : in BIT; NAD0X : in bit ;
prechx : in BIT; SENSEX : in bit ;
writex : in BIT; NSENSEX : in bit ;
din : in BIT; PRECHX : in bit ;
dout : out BIT; WRITEX : in bit ;
vdd : in BIT; DIN : in bit ;
vss : in BIT DOUT : out mux_bit bus;
VDD : in bit ;
VSS : in bit
); );
END ram_sense_data;
ARCHITECTURE VBE OF ram_sense_data IS end RAM_SENSE_DATA;
BEGIN architecture vbe of RAM_SENSE_DATA is
ASSERT (vdd and not (vss))
REPORT "power supply is missing on ram_sense_data"
SEVERITY WARNING;
END; begin
assert (VDD = '1' and VSS = '0')
report "power supply is missing on ram_sense_data"
severity WARNING;
assert ((AD0X xor NAD0X ) = '1')
report "conflicting ad0x / nad0x in ram_sense_data"
severity WARNING;
assert ((SENSEX xor NSENSEX) = '1')
report "conflicting sensex / nsensex in ram_sense_data"
severity WARNING;
WRITE_0 : block (NAD0X = '1' and WRITEX = '1')
begin
BIT0 <= guarded DIN;
NBIT0 <= guarded not DIN;
end block;
WRITE_1 : block (AD0X = '1' and WRITEX = '1')
begin
BIT1 <= guarded DIN;
NBIT1 <= guarded not DIN;
end block;
SENSE_0 : block (PRECHX = '0' and WRITEX = '0' and (BIT0 xor NBIT0) = '1')
begin
BIT0 <= guarded BIT0 ;
NBIT0 <= guarded NBIT0;
end block;
SENSE_1 : block (PRECHX = '0' and WRITEX = '0' and (BIT1 xor NBIT1) = '1')
begin
BIT1 <= guarded BIT1 ;
NBIT1 <= guarded NBIT1;
end block;
DATA_OUT : block (SENSEX = '1')
begin
with AD0X select
DOUT <= guarded bit0 when '0',
bit1 when '1';
end block;
end;