From 8a4b6d3e9da4abb814a812b629b5e6af951e01e5 Mon Sep 17 00:00:00 2001
From: Jean-Paul Chaput <Jean-Paul.Chaput@lip6.fr>
Date: Tue, 31 Aug 2004 08:37:17 +0000
Subject: [PATCH] Corrected behavioral view in order to be simulated with
 Asimut.

---
 .../src/cells/src/ramlib/ram_mem_data.vbe     | 61 +++++++++----
 .../src/cells/src/ramlib/ram_sense_data.vbe   | 91 ++++++++++++++-----
 2 files changed, 112 insertions(+), 40 deletions(-)

diff --git a/alliance/src/cells/src/ramlib/ram_mem_data.vbe b/alliance/src/cells/src/ramlib/ram_mem_data.vbe
index 756980ec..99fba01d 100644
--- a/alliance/src/cells/src/ramlib/ram_mem_data.vbe
+++ b/alliance/src/cells/src/ramlib/ram_mem_data.vbe
@@ -1,20 +1,49 @@
-ENTITY ram_mem_data IS
-PORT (
-  selxi  : in  BIT;
-  bit0   : in  BIT;
-  nbit0  : in  BIT;
-  bit1   : in  BIT;
-  nbit1  : in  BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END ram_mem_data;
+entity RAM_MEM_DATA is
 
-ARCHITECTURE VBE OF ram_mem_data IS
+  port
+    (
+    SELXI  : in    bit        ;
+    BIT0   : inout wor_bit bus;
+    NBIT0  : inout wor_bit bus;
+    BIT1   : inout wor_bit bus;
+    NBIT1  : inout wor_bit bus;
+    VDD    : in    bit        ;
+    VSS    : in    bit
+    );
 
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on ram_mem_data"
-  SEVERITY WARNING;
+end RAM_MEM_DATA;
+
+architecture vbe of RAM_MEM_DATA is
+
+signal LATCH0 : reg_bit register;
+signal LATCH1 : reg_bit register;
+
+begin
+
+  assert (VDD ='1' and VSS = '0')
+    report "power supply is missing on ram_mem_data"
+    severity WARNING;
+
+  WRITE_0 : BLOCK ((SELXI and (BIT0 xor NBIT0)) = '1')
+  begin
+    LATCH0 <= guarded BIT0;
+  end block;
+
+  WRITE_1 : BLOCK ((SELXI and (BIT1 xor NBIT1)) = '1')
+  begin
+    LATCH1 <= guarded BIT1;
+  end block;
+
+  READ_0  : BLOCK ((SELXI and not SELXI'STABLE) = '1')
+  begin
+    BIT0  <= guarded     LATCH0;
+    NBIT0 <= guarded not LATCH0;
+  end block;
+
+  READ_1  : BLOCK ((SELXI and not SELXI'STABLE) = '1')
+  begin
+    BIT1  <= guarded     LATCH1;
+    NBIT1 <= guarded not LATCH1;
+  end block;
 
 END;
diff --git a/alliance/src/cells/src/ramlib/ram_sense_data.vbe b/alliance/src/cells/src/ramlib/ram_sense_data.vbe
index 39adcffa..747388b0 100644
--- a/alliance/src/cells/src/ramlib/ram_sense_data.vbe
+++ b/alliance/src/cells/src/ramlib/ram_sense_data.vbe
@@ -1,27 +1,70 @@
-ENTITY ram_sense_data IS
-PORT (
-  bit0     : in  BIT;
-  nbit0    : in  BIT;
-  bit1     : in  BIT;
-  nbit1    : in  BIT;
-  ad0x     : in  BIT;
-  nad0x    : in  BIT;
-  sensex   : in  BIT;
-  nsensex  : in  BIT;
-  prechx   : in  BIT;
-  writex   : in  BIT;
-  din      : in  BIT;
-  dout     : out  BIT;
-  vdd	   : in  BIT;
-  vss	   : in  BIT
-);
-END ram_sense_data;
+entity RAM_SENSE_DATA is
 
-ARCHITECTURE VBE OF ram_sense_data IS
+  port
+    (
+    bit0     : inout wor_bit bus;
+    Nbit0    : inout wor_bit bus;
+    bit1     : inout wor_bit bus;
+    Nbit1    : inout wor_bit bus;
+    AD0X     : in    bit        ;
+    NAD0X    : in    bit        ;
+    SENSEX   : in    bit        ;
+    NSENSEX  : in    bit        ;
+    PRECHX   : in    bit        ;
+    WRITEX   : in    bit        ;
+    DIN      : in    bit        ;
+    DOUT     : out   mux_bit bus;
+    VDD      : in    bit        ;
+    VSS      : in    bit
+    );
 
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on ram_sense_data"
-  SEVERITY WARNING;
+end RAM_SENSE_DATA;
 
-END;
+architecture vbe of RAM_SENSE_DATA is
+
+begin
+
+  assert (VDD = '1' and VSS = '0')
+    report "power supply is missing on ram_sense_data"
+    severity WARNING;
+
+  assert ((AD0X   xor NAD0X  ) = '1')
+    report "conflicting ad0x / nad0x in ram_sense_data"
+    severity WARNING;
+
+  assert ((SENSEX xor NSENSEX) = '1')
+    report "conflicting sensex / nsensex in ram_sense_data"
+    severity WARNING;
+
+  WRITE_0 : block (NAD0X = '1' and WRITEX = '1')
+  begin
+    BIT0  <= guarded     DIN;
+    NBIT0 <= guarded not DIN;
+  end block;
+
+  WRITE_1 : block (AD0X  = '1' and WRITEX = '1')
+  begin
+    BIT1  <= guarded     DIN;
+    NBIT1 <= guarded not DIN;
+  end block;
+
+  SENSE_0 : block (PRECHX = '0' and WRITEX = '0' and (BIT0 xor NBIT0) = '1')
+  begin
+    BIT0  <= guarded BIT0 ;
+    NBIT0 <= guarded NBIT0;
+  end block;
+
+  SENSE_1 : block (PRECHX = '0' and WRITEX = '0' and (BIT1 xor NBIT1) = '1')
+  begin
+    BIT1  <= guarded BIT1 ;
+    NBIT1 <= guarded NBIT1;
+  end block;
+
+  DATA_OUT : block (SENSEX = '1')
+  begin
+    with AD0X select
+      DOUT <= guarded bit0 when '0',
+                      bit1 when '1';
+  end block;
+
+end;