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alliance
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pour que les cellules soient aussi decrite en vhdl standard 

merci a vasy et Adrijean.
This commit is contained in:
Franck Wajsburt 2001-08-20 09:15:29 +00:00
parent c5d84f70d8
commit 89a047d1e6
95 changed files with 2096 additions and 0 deletions
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20
alliance/share/cells/sxlib/a2_x2.vhd Normal file
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--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY a2_x2 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END a2_x2;
ARCHITECTURE RTL OF a2_x2 IS
BEGIN
q <= (i0 AND i1);
END RTL;

20
alliance/share/cells/sxlib/a2_x4.vhd Normal file
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@ -0,0 +1,20 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY a2_x4 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END a2_x4;
ARCHITECTURE RTL OF a2_x4 IS
BEGIN
q <= (i0 AND i1);
END RTL;

21
alliance/share/cells/sxlib/a3_x2.vhd Normal file
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@ -0,0 +1,21 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY a3_x2 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END a3_x2;
ARCHITECTURE RTL OF a3_x2 IS
BEGIN
q <= ((i0 AND i1) AND i2);
END RTL;

21
alliance/share/cells/sxlib/a3_x4.vhd Normal file
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@ -0,0 +1,21 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY a3_x4 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END a3_x4;
ARCHITECTURE RTL OF a3_x4 IS
BEGIN
q <= ((i0 AND i1) AND i2);
END RTL;

22
alliance/share/cells/sxlib/a4_x2.vhd Normal file
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@ -0,0 +1,22 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY a4_x2 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
i3 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END a4_x2;
ARCHITECTURE RTL OF a4_x2 IS
BEGIN
q <= (((i0 AND i1) AND i2) AND i3);
END RTL;

22
alliance/share/cells/sxlib/a4_x4.vhd Normal file
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@ -0,0 +1,22 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY a4_x4 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
i3 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END a4_x4;
ARCHITECTURE RTL OF a4_x4 IS
BEGIN
q <= (((i0 AND i1) AND i2) AND i3);
END RTL;

20
alliance/share/cells/sxlib/an12_x1.vhd Normal file
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@ -0,0 +1,20 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY an12_x1 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END an12_x1;
ARCHITECTURE RTL OF an12_x1 IS
BEGIN
q <= (NOT(i0) AND i1);
END RTL;

20
alliance/share/cells/sxlib/an12_x4.vhd Normal file
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@ -0,0 +1,20 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY an12_x4 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END an12_x4;
ARCHITECTURE RTL OF an12_x4 IS
BEGIN
q <= (NOT(i0) AND i1);
END RTL;

21
alliance/share/cells/sxlib/ao22_x2.vhd Normal file
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@ -0,0 +1,21 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY ao22_x2 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END ao22_x2;
ARCHITECTURE RTL OF ao22_x2 IS
BEGIN
q <= ((i0 OR i1) AND i2);
END RTL;

21
alliance/share/cells/sxlib/ao22_x4.vhd Normal file
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@ -0,0 +1,21 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY ao22_x4 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END ao22_x4;
ARCHITECTURE RTL OF ao22_x4 IS
BEGIN
q <= ((i0 OR i1) AND i2);
END RTL;

22
alliance/share/cells/sxlib/ao2o22_x2.vhd Normal file
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@ -0,0 +1,22 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY ao2o22_x2 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
i3 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END ao2o22_x2;
ARCHITECTURE RTL OF ao2o22_x2 IS
BEGIN
q <= ((i0 OR i1) AND (i2 OR i3));
END RTL;

22
alliance/share/cells/sxlib/ao2o22_x4.vhd Normal file
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@ -0,0 +1,22 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY ao2o22_x4 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
i3 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END ao2o22_x4;
ARCHITECTURE RTL OF ao2o22_x4 IS
BEGIN
q <= ((i0 OR i1) AND (i2 OR i3));
END RTL;

19
alliance/share/cells/sxlib/buf_x2.vhd Normal file
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@ -0,0 +1,19 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY buf_x2 IS
PORT(
i : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END buf_x2;
ARCHITECTURE RTL OF buf_x2 IS
BEGIN
q <= i;
END RTL;

19
alliance/share/cells/sxlib/buf_x4.vhd Normal file
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@ -0,0 +1,19 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY buf_x4 IS
PORT(
i : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END buf_x4;
ARCHITECTURE RTL OF buf_x4 IS
BEGIN
q <= i;
END RTL;

19
alliance/share/cells/sxlib/buf_x8.vhd Normal file
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@ -0,0 +1,19 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY buf_x8 IS
PORT(
i : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END buf_x8;
ARCHITECTURE RTL OF buf_x8 IS
BEGIN
q <= i;
END RTL;

34
alliance/share/cells/sxlib/fulladder_x2.vhd Normal file
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@ -0,0 +1,34 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY fulladder_x2 IS
PORT(
a1 : IN STD_LOGIC;
a2 : IN STD_LOGIC;
a3 : IN STD_LOGIC;
a4 : IN STD_LOGIC;
b1 : IN STD_LOGIC;
b2 : IN STD_LOGIC;
b3 : IN STD_LOGIC;
b4 : IN STD_LOGIC;
cin1 : IN STD_LOGIC;
cin2 : IN STD_LOGIC;
cin3 : IN STD_LOGIC;
cout : OUT STD_LOGIC;
sout : OUT STD_LOGIC
);
END fulladder_x2;
ARCHITECTURE RTL OF fulladder_x2 IS
SIGNAL ncout : STD_LOGIC;
BEGIN
cout <= NOT(ncout);
sout <= (((a3 AND b3) AND cin2) OR (((a4 OR b4) OR cin3) AND ncout));
ncout <= NOT(((a1 AND b1) OR ((a2 OR b2) AND cin1)));
END RTL;

34
alliance/share/cells/sxlib/fulladder_x4.vhd Normal file
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@ -0,0 +1,34 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY fulladder_x4 IS
PORT(
a1 : IN STD_LOGIC;
a2 : IN STD_LOGIC;
a3 : IN STD_LOGIC;
a4 : IN STD_LOGIC;
b1 : IN STD_LOGIC;
b2 : IN STD_LOGIC;
b3 : IN STD_LOGIC;
b4 : IN STD_LOGIC;
cin1 : IN STD_LOGIC;
cin2 : IN STD_LOGIC;
cin3 : IN STD_LOGIC;
cout : OUT STD_LOGIC;
sout : OUT STD_LOGIC
);
END fulladder_x4;
ARCHITECTURE RTL OF fulladder_x4 IS
SIGNAL ncout : STD_LOGIC;
BEGIN
cout <= NOT(ncout);
sout <= (((a3 AND b3) AND cin2) OR (((a4 OR b4) OR cin3) AND ncout));
ncout <= NOT(((a1 AND b1) OR ((a2 OR b2) AND cin1)));
END RTL;

22
alliance/share/cells/sxlib/halfadder_x2.vhd Normal file
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@ -0,0 +1,22 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY halfadder_x2 IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
cout : OUT STD_LOGIC;
sout : OUT STD_LOGIC
);
END halfadder_x2;
ARCHITECTURE RTL OF halfadder_x2 IS
BEGIN
cout <= (a AND b);
sout <= (a XOR b);
END RTL;

22
alliance/share/cells/sxlib/halfadder_x4.vhd Normal file
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@ -0,0 +1,22 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY halfadder_x4 IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
cout : OUT STD_LOGIC;
sout : OUT STD_LOGIC
);
END halfadder_x4;
ARCHITECTURE RTL OF halfadder_x4 IS
BEGIN
cout <= (a AND b);
sout <= (a XOR b);
END RTL;

19
alliance/share/cells/sxlib/inv_x1.vhd Normal file
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@ -0,0 +1,19 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY inv_x1 IS
PORT(
i : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END inv_x1;
ARCHITECTURE RTL OF inv_x1 IS
BEGIN
nq <= NOT(i);
END RTL;

19
alliance/share/cells/sxlib/inv_x2.vhd Normal file
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@ -0,0 +1,19 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY inv_x2 IS
PORT(
i : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END inv_x2;
ARCHITECTURE RTL OF inv_x2 IS
BEGIN
nq <= NOT(i);
END RTL;

19
alliance/share/cells/sxlib/inv_x4.vhd Normal file
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@ -0,0 +1,19 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY inv_x4 IS
PORT(
i : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END inv_x4;
ARCHITECTURE RTL OF inv_x4 IS
BEGIN
nq <= NOT(i);
END RTL;

19
alliance/share/cells/sxlib/inv_x8.vhd Normal file
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@ -0,0 +1,19 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY inv_x8 IS
PORT(
i : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END inv_x8;
ARCHITECTURE RTL OF inv_x8 IS
BEGIN
nq <= NOT(i);
END RTL;

21
alliance/share/cells/sxlib/mx2_x2.vhd Normal file
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@ -0,0 +1,21 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY mx2_x2 IS
PORT(
cmd : IN STD_LOGIC;
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END mx2_x2;
ARCHITECTURE RTL OF mx2_x2 IS
BEGIN
q <= ((i1 AND cmd) OR (NOT(cmd) AND i0));
END RTL;

21
alliance/share/cells/sxlib/mx2_x4.vhd Normal file
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@ -0,0 +1,21 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY mx2_x4 IS
PORT(
cmd : IN STD_LOGIC;
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END mx2_x4;
ARCHITECTURE RTL OF mx2_x4 IS
BEGIN
q <= ((i1 AND cmd) OR (NOT(cmd) AND i0));
END RTL;

23
alliance/share/cells/sxlib/mx3_x2.vhd Normal file
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@ -0,0 +1,23 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY mx3_x2 IS
PORT(
cmd0 : IN STD_LOGIC;
cmd1 : IN STD_LOGIC;
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END mx3_x2;
ARCHITECTURE RTL OF mx3_x2 IS
BEGIN
q <= ((NOT(cmd0) AND i0) OR (cmd0 AND ((cmd1 AND i1) OR (NOT(cmd1) AND i2))));
END RTL;

23
alliance/share/cells/sxlib/mx3_x4.vhd Normal file
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@ -0,0 +1,23 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY mx3_x4 IS
PORT(
cmd0 : IN STD_LOGIC;
cmd1 : IN STD_LOGIC;
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END mx3_x4;
ARCHITECTURE RTL OF mx3_x4 IS
BEGIN
q <= ((NOT(cmd0) AND i0) OR (cmd0 AND ((cmd1 AND i1) OR (NOT(cmd1) AND i2))));
END RTL;

20
alliance/share/cells/sxlib/na2_x1.vhd Normal file
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@ -0,0 +1,20 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY na2_x1 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END na2_x1;
ARCHITECTURE RTL OF na2_x1 IS
BEGIN
nq <= NOT((i0 AND i1));
END RTL;

20
alliance/share/cells/sxlib/na2_x4.vhd Normal file
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@ -0,0 +1,20 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY na2_x4 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END na2_x4;
ARCHITECTURE RTL OF na2_x4 IS
BEGIN
nq <= NOT((i0 AND i1));
END RTL;

21
alliance/share/cells/sxlib/na3_x1.vhd Normal file
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@ -0,0 +1,21 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY na3_x1 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END na3_x1;
ARCHITECTURE RTL OF na3_x1 IS
BEGIN
nq <= NOT(((i0 AND i1) AND i2));
END RTL;

21
alliance/share/cells/sxlib/na3_x4.vhd Normal file
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@ -0,0 +1,21 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY na3_x4 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END na3_x4;
ARCHITECTURE RTL OF na3_x4 IS
BEGIN
nq <= NOT(((i0 AND i1) AND i2));
END RTL;

22
alliance/share/cells/sxlib/na4_x1.vhd Normal file
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@ -0,0 +1,22 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY na4_x1 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
i3 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END na4_x1;
ARCHITECTURE RTL OF na4_x1 IS
BEGIN
nq <= NOT((((i0 AND i1) AND i2) AND i3));
END RTL;

22
alliance/share/cells/sxlib/na4_x4.vhd Normal file
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@ -0,0 +1,22 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY na4_x4 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
i3 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END na4_x4;
ARCHITECTURE RTL OF na4_x4 IS
BEGIN
nq <= NOT((((i0 AND i1) AND i2) AND i3));
END RTL;

21
alliance/share/cells/sxlib/nao22_x1.vhd Normal file
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@ -0,0 +1,21 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY nao22_x1 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END nao22_x1;
ARCHITECTURE RTL OF nao22_x1 IS
BEGIN
nq <= NOT(((i0 OR i1) AND i2));
END RTL;

21
alliance/share/cells/sxlib/nao22_x4.vhd Normal file
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@ -0,0 +1,21 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY nao22_x4 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END nao22_x4;
ARCHITECTURE RTL OF nao22_x4 IS
BEGIN
nq <= NOT(((i0 OR i1) AND i2));
END RTL;

22
alliance/share/cells/sxlib/nao2o22_x1.vhd Normal file
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@ -0,0 +1,22 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY nao2o22_x1 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
i3 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END nao2o22_x1;
ARCHITECTURE RTL OF nao2o22_x1 IS
BEGIN
nq <= NOT(((i0 OR i1) AND (i2 OR i3)));
END RTL;

22
alliance/share/cells/sxlib/nao2o22_x4.vhd Normal file
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@ -0,0 +1,22 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY nao2o22_x4 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
i3 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END nao2o22_x4;
ARCHITECTURE RTL OF nao2o22_x4 IS
BEGIN
nq <= NOT(((i0 OR i1) AND (i2 OR i3)));
END RTL;

21
alliance/share/cells/sxlib/nmx2_x1.vhd Normal file
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@ -0,0 +1,21 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY nmx2_x1 IS
PORT(
cmd : IN STD_LOGIC;
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END nmx2_x1;
ARCHITECTURE RTL OF nmx2_x1 IS
BEGIN
nq <= NOT(((i0 AND NOT(cmd)) OR (i1 AND cmd)));
END RTL;

21
alliance/share/cells/sxlib/nmx2_x4.vhd Normal file
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@ -0,0 +1,21 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY nmx2_x4 IS
PORT(
cmd : IN STD_LOGIC;
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END nmx2_x4;
ARCHITECTURE RTL OF nmx2_x4 IS
BEGIN
nq <= NOT(((i0 AND NOT(cmd)) OR (i1 AND cmd)));
END RTL;

23
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--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY nmx3_x1 IS
PORT(
cmd0 : IN STD_LOGIC;
cmd1 : IN STD_LOGIC;
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END nmx3_x1;
ARCHITECTURE RTL OF nmx3_x1 IS
BEGIN
nq <= NOT(((NOT(cmd0) AND i0) OR (cmd0 AND ((cmd1 AND i1) OR (NOT(cmd1) AND i2)))));
END RTL;

23
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@ -0,0 +1,23 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY nmx3_x4 IS
PORT(
cmd0 : IN STD_LOGIC;
cmd1 : IN STD_LOGIC;
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END nmx3_x4;
ARCHITECTURE RTL OF nmx3_x4 IS
BEGIN
nq <= NOT(((NOT(cmd0) AND i0) OR (cmd0 AND ((cmd1 AND i1) OR (NOT(cmd1) AND i2)))));
END RTL;

20
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@ -0,0 +1,20 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY no2_x1 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END no2_x1;
ARCHITECTURE RTL OF no2_x1 IS
BEGIN
nq <= NOT((i0 OR i1));
END RTL;

20
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@ -0,0 +1,20 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY no2_x4 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END no2_x4;
ARCHITECTURE RTL OF no2_x4 IS
BEGIN
nq <= NOT((i0 OR i1));
END RTL;

21
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@ -0,0 +1,21 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY no3_x1 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END no3_x1;
ARCHITECTURE RTL OF no3_x1 IS
BEGIN
nq <= NOT(((i0 OR i1) OR i2));
END RTL;

21
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@ -0,0 +1,21 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY no3_x4 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END no3_x4;
ARCHITECTURE RTL OF no3_x4 IS
BEGIN
nq <= NOT(((i0 OR i1) OR i2));
END RTL;

22
alliance/share/cells/sxlib/no4_x1.vhd Normal file
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@ -0,0 +1,22 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY no4_x1 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
i3 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END no4_x1;
ARCHITECTURE RTL OF no4_x1 IS
BEGIN
nq <= NOT((((i0 OR i1) OR i2) OR i3));
END RTL;

22
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@ -0,0 +1,22 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY no4_x4 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
i3 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END no4_x4;
ARCHITECTURE RTL OF no4_x4 IS
BEGIN
nq <= NOT((((i0 OR i1) OR i2) OR i3));
END RTL;

21
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@ -0,0 +1,21 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY noa22_x1 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END noa22_x1;
ARCHITECTURE RTL OF noa22_x1 IS
BEGIN
nq <= NOT(((i0 AND i1) OR i2));
END RTL;

21
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@ -0,0 +1,21 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY noa22_x4 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END noa22_x4;
ARCHITECTURE RTL OF noa22_x4 IS
BEGIN
nq <= NOT(((i0 AND i1) OR i2));
END RTL;

22
alliance/share/cells/sxlib/noa2a22_x1.vhd Normal file
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@ -0,0 +1,22 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY noa2a22_x1 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
i3 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END noa2a22_x1;
ARCHITECTURE RTL OF noa2a22_x1 IS
BEGIN
nq <= NOT(((i0 AND i1) OR (i2 AND i3)));
END RTL;

22
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@ -0,0 +1,22 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY noa2a22_x4 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
i3 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END noa2a22_x4;
ARCHITECTURE RTL OF noa2a22_x4 IS
BEGIN
nq <= NOT(((i0 AND i1) OR (i2 AND i3)));
END RTL;

24
alliance/share/cells/sxlib/noa2a2a23_x1.vhd Normal file
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@ -0,0 +1,24 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY noa2a2a23_x1 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
i3 : IN STD_LOGIC;
i4 : IN STD_LOGIC;
i5 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END noa2a2a23_x1;
ARCHITECTURE RTL OF noa2a2a23_x1 IS
BEGIN
nq <= NOT((((i0 AND i1) OR (i2 AND i3)) OR (i4 AND i5)));
END RTL;

24
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@ -0,0 +1,24 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY noa2a2a23_x4 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
i3 : IN STD_LOGIC;
i4 : IN STD_LOGIC;
i5 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END noa2a2a23_x4;
ARCHITECTURE RTL OF noa2a2a23_x4 IS
BEGIN
nq <= NOT((((i0 AND i1) OR (i2 AND i3)) OR (i4 AND i5)));
END RTL;

26
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@ -0,0 +1,26 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY noa2a2a2a24_x1 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
i3 : IN STD_LOGIC;
i4 : IN STD_LOGIC;
i5 : IN STD_LOGIC;
i6 : IN STD_LOGIC;
i7 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END noa2a2a2a24_x1;
ARCHITECTURE RTL OF noa2a2a2a24_x1 IS
BEGIN
nq <= NOT(((((i0 AND i1) OR (i2 AND i3)) OR (i4 AND i5)) OR (i6 AND i7)));
END RTL;

26
alliance/share/cells/sxlib/noa2a2a2a24_x4.vhd Normal file
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@ -0,0 +1,26 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY noa2a2a2a24_x4 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
i3 : IN STD_LOGIC;
i4 : IN STD_LOGIC;
i5 : IN STD_LOGIC;
i6 : IN STD_LOGIC;
i7 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END noa2a2a2a24_x4;
ARCHITECTURE RTL OF noa2a2a2a24_x4 IS
BEGIN
nq <= NOT(((((i0 AND i1) OR (i2 AND i3)) OR (i4 AND i5)) OR (i6 AND i7)));
END RTL;

23
alliance/share/cells/sxlib/noa2ao222_x1.vhd Normal file
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@ -0,0 +1,23 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY noa2ao222_x1 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
i3 : IN STD_LOGIC;
i4 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END noa2ao222_x1;
ARCHITECTURE RTL OF noa2ao222_x1 IS
BEGIN
nq <= NOT(((i0 AND i1) OR ((i2 OR i3) AND i4)));
END RTL;

23
alliance/share/cells/sxlib/noa2ao222_x4.vhd Normal file
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@ -0,0 +1,23 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY noa2ao222_x4 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
i3 : IN STD_LOGIC;
i4 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END noa2ao222_x4;
ARCHITECTURE RTL OF noa2ao222_x4 IS
BEGIN
nq <= NOT(((i0 AND i1) OR ((i2 OR i3) AND i4)));
END RTL;

25
alliance/share/cells/sxlib/noa3ao322_x1.vhd Normal file
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@ -0,0 +1,25 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY noa3ao322_x1 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
i3 : IN STD_LOGIC;
i4 : IN STD_LOGIC;
i5 : IN STD_LOGIC;
i6 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END noa3ao322_x1;
ARCHITECTURE RTL OF noa3ao322_x1 IS
BEGIN
nq <= NOT((((i0 AND i1) AND i2) OR (((i3 OR i4) OR i5) AND i6)));
END RTL;

25
alliance/share/cells/sxlib/noa3ao322_x4.vhd Normal file
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@ -0,0 +1,25 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY noa3ao322_x4 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
i3 : IN STD_LOGIC;
i4 : IN STD_LOGIC;
i5 : IN STD_LOGIC;
i6 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END noa3ao322_x4;
ARCHITECTURE RTL OF noa3ao322_x4 IS
BEGIN
nq <= NOT((((i0 AND i1) AND i2) OR (((i3 OR i4) OR i5) AND i6)));
END RTL;

26
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@ -0,0 +1,26 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY nts_x1 IS
PORT(
cmd : IN STD_LOGIC;
i : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END nts_x1;
ARCHITECTURE RTL OF nts_x1 IS
BEGIN
PROCESS ( i, cmd )
BEGIN
IF (cmd = '1')
THEN nq <= NOT(i);
ELSE nq <= 'Z';
END IF;
END PROCESS;
END RTL;

26
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@ -0,0 +1,26 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY nts_x2 IS
PORT(
cmd : IN STD_LOGIC;
i : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END nts_x2;
ARCHITECTURE RTL OF nts_x2 IS
BEGIN
PROCESS ( i, cmd )
BEGIN
IF (cmd = '1')
THEN nq <= NOT(i);
ELSE nq <= 'Z';
END IF;
END PROCESS;
END RTL;

20
alliance/share/cells/sxlib/nxr2_x1.vhd Normal file
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@ -0,0 +1,20 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY nxr2_x1 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END nxr2_x1;
ARCHITECTURE RTL OF nxr2_x1 IS
BEGIN
nq <= NOT((i0 XOR i1));
END RTL;

20
alliance/share/cells/sxlib/nxr2_x4.vhd Normal file
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@ -0,0 +1,20 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY nxr2_x4 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
nq : OUT STD_LOGIC
);
END nxr2_x4;
ARCHITECTURE RTL OF nxr2_x4 IS
BEGIN
nq <= NOT((i0 XOR i1));
END RTL;

20
alliance/share/cells/sxlib/o2_x2.vhd Normal file
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@ -0,0 +1,20 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY o2_x2 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END o2_x2;
ARCHITECTURE RTL OF o2_x2 IS
BEGIN
q <= (i0 OR i1);
END RTL;

20
alliance/share/cells/sxlib/o2_x4.vhd Normal file
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@ -0,0 +1,20 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY o2_x4 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END o2_x4;
ARCHITECTURE RTL OF o2_x4 IS
BEGIN
q <= (i0 OR i1);
END RTL;

21
alliance/share/cells/sxlib/o3_x2.vhd Normal file
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@ -0,0 +1,21 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY o3_x2 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END o3_x2;
ARCHITECTURE RTL OF o3_x2 IS
BEGIN
q <= ((i0 OR i1) OR i2);
END RTL;

21
alliance/share/cells/sxlib/o3_x4.vhd Normal file
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@ -0,0 +1,21 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY o3_x4 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END o3_x4;
ARCHITECTURE RTL OF o3_x4 IS
BEGIN
q <= ((i0 OR i1) OR i2);
END RTL;

22
alliance/share/cells/sxlib/o4_x2.vhd Normal file
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@ -0,0 +1,22 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY o4_x2 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
i3 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END o4_x2;
ARCHITECTURE RTL OF o4_x2 IS
BEGIN
q <= (((i0 OR i1) OR i2) OR i3);
END RTL;

22
alliance/share/cells/sxlib/o4_x4.vhd Normal file
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@ -0,0 +1,22 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY o4_x4 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
i3 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END o4_x4;
ARCHITECTURE RTL OF o4_x4 IS
BEGIN
q <= (((i0 OR i1) OR i2) OR i3);
END RTL;

21
alliance/share/cells/sxlib/oa22_x2.vhd Normal file
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@ -0,0 +1,21 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY oa22_x2 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END oa22_x2;
ARCHITECTURE RTL OF oa22_x2 IS
BEGIN
q <= ((i0 AND i1) OR i2);
END RTL;

21
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@ -0,0 +1,21 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY oa22_x4 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END oa22_x4;
ARCHITECTURE RTL OF oa22_x4 IS
BEGIN
q <= ((i0 AND i1) OR i2);
END RTL;

22
alliance/share/cells/sxlib/oa2a22_x2.vhd Normal file
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@ -0,0 +1,22 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY oa2a22_x2 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
i3 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END oa2a22_x2;
ARCHITECTURE RTL OF oa2a22_x2 IS
BEGIN
q <= ((i0 AND i1) OR (i2 AND i3));
END RTL;

22
alliance/share/cells/sxlib/oa2a22_x4.vhd Normal file
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@ -0,0 +1,22 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY oa2a22_x4 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
i3 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END oa2a22_x4;
ARCHITECTURE RTL OF oa2a22_x4 IS
BEGIN
q <= ((i0 AND i1) OR (i2 AND i3));
END RTL;

24
alliance/share/cells/sxlib/oa2a2a23_x2.vhd Normal file
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@ -0,0 +1,24 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY oa2a2a23_x2 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
i3 : IN STD_LOGIC;
i4 : IN STD_LOGIC;
i5 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END oa2a2a23_x2;
ARCHITECTURE RTL OF oa2a2a23_x2 IS
BEGIN
q <= (((i0 AND i1) OR (i2 AND i3)) OR (i4 AND i5));
END RTL;

24
alliance/share/cells/sxlib/oa2a2a23_x4.vhd Normal file
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@ -0,0 +1,24 @@
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY oa2a2a23_x4 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
i3 : IN STD_LOGIC;
i4 : IN STD_LOGIC;
i5 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END oa2a2a23_x4;
ARCHITECTURE RTL OF oa2a2a23_x4 IS
BEGIN
q <= (((i0 AND i1) OR (i2 AND i3)) OR (i4 AND i5));
END RTL;

26
alliance/share/cells/sxlib/oa2a2a2a24_x2.vhd Normal file
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--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY oa2a2a2a24_x2 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
i3 : IN STD_LOGIC;
i4 : IN STD_LOGIC;
i5 : IN STD_LOGIC;
i6 : IN STD_LOGIC;
i7 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END oa2a2a2a24_x2;
ARCHITECTURE RTL OF oa2a2a2a24_x2 IS
BEGIN
q <= ((((i0 AND i1) OR (i2 AND i3)) OR (i4 AND i5)) OR (i6 AND i7));
END RTL;

26
alliance/share/cells/sxlib/oa2a2a2a24_x4.vhd Normal file
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--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY oa2a2a2a24_x4 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
i3 : IN STD_LOGIC;
i4 : IN STD_LOGIC;
i5 : IN STD_LOGIC;
i6 : IN STD_LOGIC;
i7 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END oa2a2a2a24_x4;
ARCHITECTURE RTL OF oa2a2a2a24_x4 IS
BEGIN
q <= ((((i0 AND i1) OR (i2 AND i3)) OR (i4 AND i5)) OR (i6 AND i7));
END RTL;

23
alliance/share/cells/sxlib/oa2ao222_x2.vhd Normal file
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--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY oa2ao222_x2 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
i3 : IN STD_LOGIC;
i4 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END oa2ao222_x2;
ARCHITECTURE RTL OF oa2ao222_x2 IS
BEGIN
q <= ((i0 AND i1) OR (i4 AND (i2 OR i3)));
END RTL;

23
alliance/share/cells/sxlib/oa2ao222_x4.vhd Normal file
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--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY oa2ao222_x4 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
i3 : IN STD_LOGIC;
i4 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END oa2ao222_x4;
ARCHITECTURE RTL OF oa2ao222_x4 IS
BEGIN
q <= ((i0 AND i1) OR (i4 AND (i2 OR i3)));
END RTL;

25
alliance/share/cells/sxlib/oa3ao322_x2.vhd Normal file
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--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY oa3ao322_x2 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
i3 : IN STD_LOGIC;
i4 : IN STD_LOGIC;
i5 : IN STD_LOGIC;
i6 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END oa3ao322_x2;
ARCHITECTURE RTL OF oa3ao322_x2 IS
BEGIN
q <= (((i0 AND i1) AND i2) OR (i6 AND ((i3 OR i4) OR i5)));
END RTL;

25
alliance/share/cells/sxlib/oa3ao322_x4.vhd Normal file
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--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY oa3ao322_x4 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
i3 : IN STD_LOGIC;
i4 : IN STD_LOGIC;
i5 : IN STD_LOGIC;
i6 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END oa3ao322_x4;
ARCHITECTURE RTL OF oa3ao322_x4 IS
BEGIN
q <= (((i0 AND i1) AND i2) OR (i6 AND ((i3 OR i4) OR i5)));
END RTL;

20
alliance/share/cells/sxlib/on12_x1.vhd Normal file
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--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY on12_x1 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END on12_x1;
ARCHITECTURE RTL OF on12_x1 IS
BEGIN
q <= (NOT(i0) OR i1);
END RTL;

20
alliance/share/cells/sxlib/on12_x4.vhd Normal file
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--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY on12_x4 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END on12_x4;
ARCHITECTURE RTL OF on12_x4 IS
BEGIN
q <= (NOT(i0) OR i1);
END RTL;

18
alliance/share/cells/sxlib/one_x0.vhd Normal file
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--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY one_x0 IS
PORT(
q : OUT STD_LOGIC
);
END one_x0;
ARCHITECTURE RTL OF one_x0 IS
BEGIN
q <= '1';
END RTL;

16
alliance/share/cells/sxlib/powmid_x0.vhd Normal file
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--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY powmid_x0 IS
PORT(
);
END powmid_x0;
ARCHITECTURE RTL OF powmid_x0 IS
BEGIN
END RTL;

16
alliance/share/cells/sxlib/rowend_x0.vhd Normal file
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--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY rowend_x0 IS
PORT(
);
END rowend_x0;
ARCHITECTURE RTL OF rowend_x0 IS
BEGIN
END RTL;

27
alliance/share/cells/sxlib/sff1_x4.vhd Normal file
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--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY sff1_x4 IS
PORT(
ck : IN STD_LOGIC;
i : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END sff1_x4;
ARCHITECTURE RTL OF sff1_x4 IS
SIGNAL sff_m : STD_LOGIC;
BEGIN
q <= sff_m;
PROCESS ( ck )
BEGIN
IF ((ck = '1') AND ck'EVENT)
THEN sff_m <= i;
END IF;
END PROCESS;
END RTL;

29
alliance/share/cells/sxlib/sff2_x4.vhd Normal file
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--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY sff2_x4 IS
PORT(
ck : IN STD_LOGIC;
cmd : IN STD_LOGIC;
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END sff2_x4;
ARCHITECTURE RTL OF sff2_x4 IS
SIGNAL sff_m : STD_LOGIC;
BEGIN
q <= sff_m;
PROCESS ( ck )
BEGIN
IF ((ck = '1') AND ck'EVENT)
THEN sff_m <= ((i1 AND cmd) OR (i0 AND NOT(cmd)));
END IF;
END PROCESS;
END RTL;

31
alliance/share/cells/sxlib/sff3_x4.vhd Normal file
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--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY sff3_x4 IS
PORT(
ck : IN STD_LOGIC;
cmd0 : IN STD_LOGIC;
cmd1 : IN STD_LOGIC;
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END sff3_x4;
ARCHITECTURE RTL OF sff3_x4 IS
SIGNAL sff_m : STD_LOGIC;
BEGIN
q <= sff_m;
PROCESS ( ck )
BEGIN
IF ((ck = '1') AND ck'EVENT)
THEN sff_m <= ((NOT(cmd0) AND i0) OR (cmd0 AND ((cmd1 AND i1) OR (NOT(cmd1) AND i2))));
END IF;
END PROCESS;
END RTL;

16
alliance/share/cells/sxlib/tie_x0.vhd Normal file
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--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY tie_x0 IS
PORT(
);
END tie_x0;
ARCHITECTURE RTL OF tie_x0 IS
BEGIN
END RTL;

26
alliance/share/cells/sxlib/ts_x4.vhd Normal file
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--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY ts_x4 IS
PORT(
cmd : IN STD_LOGIC;
i : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END ts_x4;
ARCHITECTURE RTL OF ts_x4 IS
BEGIN
PROCESS ( i, cmd )
BEGIN
IF (cmd = '1')
THEN q <= i;
ELSE q <= 'Z';
END IF;
END PROCESS;
END RTL;

26
alliance/share/cells/sxlib/ts_x8.vhd Normal file
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--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY ts_x8 IS
PORT(
cmd : IN STD_LOGIC;
i : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END ts_x8;
ARCHITECTURE RTL OF ts_x8 IS
BEGIN
PROCESS ( i, cmd )
BEGIN
IF (cmd = '1')
THEN q <= i;
ELSE q <= 'Z';
END IF;
END PROCESS;
END RTL;

20
alliance/share/cells/sxlib/xr2_x1.vhd Normal file
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--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY xr2_x1 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END xr2_x1;
ARCHITECTURE RTL OF xr2_x1 IS
BEGIN
q <= (i0 XOR i1);
END RTL;

20
alliance/share/cells/sxlib/xr2_x4.vhd Normal file
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--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY xr2_x4 IS
PORT(
i0 : IN STD_LOGIC;
i1 : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END xr2_x4;
ARCHITECTURE RTL OF xr2_x4 IS
BEGIN
q <= (i0 XOR i1);
END RTL;

18
alliance/share/cells/sxlib/zero_x0.vhd Normal file
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--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY zero_x0 IS
PORT(
nq : OUT STD_LOGIC
);
END zero_x0;
ARCHITECTURE RTL OF zero_x0 IS
BEGIN
nq <= '0';
END RTL;