27 lines
352 B
VHDL
27 lines
352 B
VHDL
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--
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-- Generated by VASY
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--
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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ENTITY ts_x4 IS
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PORT(
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cmd : IN STD_LOGIC;
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i : IN STD_LOGIC;
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q : OUT STD_LOGIC
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);
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END ts_x4;
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ARCHITECTURE RTL OF ts_x4 IS
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BEGIN
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PROCESS ( i, cmd )
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BEGIN
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IF (cmd = '1')
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THEN q <= i;
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ELSE q <= 'Z';
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END IF;
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END PROCESS;
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END RTL;
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