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invert polarity

This commit is contained in:
Francois Donnet 2004-06-04 16:25:43 +00:00
parent 33554c4d67
commit 62501bace7
2 changed files with 4 additions and 2 deletions
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5
alliance/src/vasy/src/vasy_drvvlog.c
View File

@ -432,10 +432,11 @@ static void VasyVerilogTreatAsg( RtlFigure, RtlAsg )
( RtlType == RTL_BIVEX_FALLING_EDGE ) )
{
VexCond = RtlBiVex->VEX_COND;
SensName = GetVexAtomValue( VexCond );
if ( RtlType == RTL_BIVEX_FALLING_EDGE ) SensType = VASY_VERILOG_SENS_POSEDGE;
else SensType = VASY_VERILOG_SENS_NEGEDGE;
if ( RtlType == RTL_BIVEX_FALLING_EDGE ) SensType = VASY_VERILOG_SENS_NEGEDGE;
else SensType = VASY_VERILOG_SENS_POSEDGE;
SensList = addptype( SensList, SensType, SensName );
}

1
alliance/src/vasy/src/vasy_main.c
View File

@ -262,6 +262,7 @@ int main( argc, argv )
int Index;
printf("HELLO\n");
alliancebanner_with_contrib(
"VASY", VERSION, "VHDL Analyzer for SYnthesis",
"2000", ALLIANCE_VERSION, "Ludovic Jacomme", "Frederic Petrot" );