From 62501bace7794babffd61ca1e6b62b50d71d9585 Mon Sep 17 00:00:00 2001 From: Francois Donnet Date: Fri, 4 Jun 2004 16:25:43 +0000 Subject: [PATCH] invert polarity --- alliance/src/vasy/src/vasy_drvvlog.c | 5 +++-- alliance/src/vasy/src/vasy_main.c | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/alliance/src/vasy/src/vasy_drvvlog.c b/alliance/src/vasy/src/vasy_drvvlog.c index 31d66138..dc13038c 100644 --- a/alliance/src/vasy/src/vasy_drvvlog.c +++ b/alliance/src/vasy/src/vasy_drvvlog.c @@ -432,10 +432,11 @@ static void VasyVerilogTreatAsg( RtlFigure, RtlAsg ) ( RtlType == RTL_BIVEX_FALLING_EDGE ) ) { VexCond = RtlBiVex->VEX_COND; + SensName = GetVexAtomValue( VexCond ); - if ( RtlType == RTL_BIVEX_FALLING_EDGE ) SensType = VASY_VERILOG_SENS_POSEDGE; - else SensType = VASY_VERILOG_SENS_NEGEDGE; + if ( RtlType == RTL_BIVEX_FALLING_EDGE ) SensType = VASY_VERILOG_SENS_NEGEDGE; + else SensType = VASY_VERILOG_SENS_POSEDGE; SensList = addptype( SensList, SensType, SensName ); } diff --git a/alliance/src/vasy/src/vasy_main.c b/alliance/src/vasy/src/vasy_main.c index da731e84..fbf26495 100644 --- a/alliance/src/vasy/src/vasy_main.c +++ b/alliance/src/vasy/src/vasy_main.c @@ -262,6 +262,7 @@ int main( argc, argv ) int Index; + printf("HELLO\n"); alliancebanner_with_contrib( "VASY", VERSION, "VHDL Analyzer for SYnthesis", "2000", ALLIANCE_VERSION, "Ludovic Jacomme", "Frederic Petrot" );