Generic/Generate/Structurel
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.\" $Id: vasy.1,v 1.4 2000/02/11 10:47:08 syf Exp $
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.\" $Id: vasy.1,v 1.5 2000/03/02 17:15:40 syf Exp $
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.\" @(#)Labo.l 2.2 95/09/24 UPMC; Author: Jacomme L.
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.\" @(#)Labo.l 2.2 95/09/24 UPMC; Author: Jacomme L.
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.pl -.4
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.pl -.4
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.TH VASY 1 "November 26, 1999" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
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.TH VASY 1 "November 26, 1999" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
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@ -8,17 +8,20 @@ VASY \- VHDL Analyzer for Synthesis
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.so man1/alc_origin.1
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.so man1/alc_origin.1
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.SH SYNOPSIS
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.SH SYNOPSIS
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.TP
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.TP
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\f4vasy \-V|v|a|s|S [-I input_format] input_name [output_name]
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\f4vasy \-V|v|a|s|S|H [-I input_format] input_name [output_name]
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.br
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.br
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.SH DESCRIPTION
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.SH DESCRIPTION
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.br
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.br
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\fBVASY\fp is a VHDL Analyzer for Synthesis.
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\fBVASY\fp is a hierarchical VHDL Analyzer for Synthesis.
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\fBVASY\fp performs a semantic analysis of a VHDL RTL description
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\fBVASY\fp performs a semantic analysis of a VHDL RTL description
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\fBinput_name\fP, with a VHDL subset much more extended than the Alliance one
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\fBinput_name\fP, with a VHDL subset much more extended than the Alliance one
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(see vasy(5) for more details), and identifies with precision all the
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(see vasy(5) for more details), and identifies with precision all the
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memorizing elements and tristate buffers.
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memorizing elements and tristate buffers.
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.br
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.br
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After this analysis, \fBVASY\fp drives an equivalent description
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During its analysis, \fBVASY\fp expands generic parameters, executes generic map
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and generate statements, and also unrolls static FOR loops.
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.br
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At the end, \fBVASY\fp drives an equivalent description
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\fBoutput_name\fP (in Verilog or VHDL format) accepted by most of
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\fBoutput_name\fP (in Verilog or VHDL format) accepted by most of
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synthesis tools.
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synthesis tools.
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.br
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.br
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@ -52,14 +55,22 @@ Uses Std_logic instead of Bit (taken into account only with option -s).
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\f4\-I\fP
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\f4\-I\fP
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Specifies the VHDL input format such as Alliance VHDL format \fBvbe\fP(5),
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Specifies the VHDL input format such as Alliance VHDL format \fBvbe\fP(5),
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\fBvst\fP(5) or industrial VHDL format \fBvhd\fP or \fBvhdl\fP.
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\fBvst\fP(5) or industrial VHDL format \fBvhd\fP or \fBvhdl\fP.
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.TP 10
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\f4\-H\fP
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In a structural description, all model of instances are recursively analyzed.
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(By default \fBVASY\fp analyzes only models with generic parameters)
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The leaves cells are defined by a special file (see catal(5) for details).
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.ti 7
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.ti 7
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.SH SEE ALSO
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.SH SEE ALSO
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.BR vasy (5),
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.BR vasy (5),
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.BR vbe (5),
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.BR vbe (5),
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.BR vhdl (5),
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.BR vhdl (5),
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.BR catal (5).
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.BR asimut (1),
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.BR asimut (1),
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.BR MBK_WORK_LIB (1).
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.BR MBK_WORK_LIB (1).
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.BR MBK_CATA_LIB (1).
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.BR MBK_CATAL_NAME (1).
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.so man1/alc_bug_report.1
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.so man1/alc_bug_report.1
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