riscv
/
alliance
mirror of https://gitlab.lip6.fr/vlsi-eda/alliance.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Generic/Generate/Structurel

This commit is contained in:
The Syf Tool 2000-03-02 17:15:40 +00:00
parent 0d1cc01ca8
commit 61bdf990d4
1 changed files with 15 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
alliance/share/man/man1/vasy.1
View File

@ -1,4 +1,4 @@
.\" $Id: vasy.1,v 1.4 2000/02/11 10:47:08 syf Exp $ .\" $Id: vasy.1,v 1.5 2000/03/02 17:15:40 syf Exp $
.\" @(#)Labo.l 2.2 95/09/24 UPMC; Author: Jacomme L. .\" @(#)Labo.l 2.2 95/09/24 UPMC; Author: Jacomme L.
.pl -.4 .pl -.4
.TH VASY 1 "November 26, 1999" "ASIM/LIP6" "CAO\-VLSI Reference Manual" .TH VASY 1 "November 26, 1999" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
@ -8,17 +8,20 @@ VASY \- VHDL Analyzer for Synthesis
.so man1/alc_origin.1 .so man1/alc_origin.1
.SH SYNOPSIS .SH SYNOPSIS
.TP .TP
\f4vasy \-V|v|a|s|S [-I input_format] input_name [output_name] \f4vasy \-V|v|a|s|S|H [-I input_format] input_name [output_name]
.br .br
.SH DESCRIPTION .SH DESCRIPTION
.br .br
\fBVASY\fp is a VHDL Analyzer for Synthesis. \fBVASY\fp is a hierarchical VHDL Analyzer for Synthesis.
\fBVASY\fp performs a semantic analysis of a VHDL RTL description \fBVASY\fp performs a semantic analysis of a VHDL RTL description
\fBinput_name\fP, with a VHDL subset much more extended than the Alliance one \fBinput_name\fP, with a VHDL subset much more extended than the Alliance one
(see vasy(5) for more details), and identifies with precision all the (see vasy(5) for more details), and identifies with precision all the
memorizing elements and tristate buffers. memorizing elements and tristate buffers.
.br .br
After this analysis, \fBVASY\fp drives an equivalent description During its analysis, \fBVASY\fp expands generic parameters, executes generic map
and generate statements, and also unrolls static FOR loops.
.br
At the end, \fBVASY\fp drives an equivalent description
\fBoutput_name\fP (in Verilog or VHDL format) accepted by most of \fBoutput_name\fP (in Verilog or VHDL format) accepted by most of
synthesis tools. synthesis tools.
.br .br
@ -52,14 +55,22 @@ Uses Std_logic instead of Bit (taken into account only with option -s).
\f4\-I\fP \f4\-I\fP
Specifies the VHDL input format such as Alliance VHDL format \fBvbe\fP(5), Specifies the VHDL input format such as Alliance VHDL format \fBvbe\fP(5),
\fBvst\fP(5) or industrial VHDL format \fBvhd\fP or \fBvhdl\fP. \fBvst\fP(5) or industrial VHDL format \fBvhd\fP or \fBvhdl\fP.
.TP 10
\f4\-H\fP
In a structural description, all model of instances are recursively analyzed.
(By default \fBVASY\fp analyzes only models with generic parameters)
The leaves cells are defined by a special file (see catal(5) for details).
.ti 7 .ti 7
.SH SEE ALSO .SH SEE ALSO
.BR vasy (5), .BR vasy (5),
.BR vbe (5), .BR vbe (5),
.BR vhdl (5), .BR vhdl (5),
.BR catal (5).
.BR asimut (1), .BR asimut (1),
.BR MBK_WORK_LIB (1). .BR MBK_WORK_LIB (1).
.BR MBK_CATA_LIB (1).
.BR MBK_CATAL_NAME (1).
.so man1/alc_bug_report.1 .so man1/alc_bug_report.1