- A 32 bits square root circuit
This commit is contained in:
Ludovic Jacomme
parent
f0eebe930e
commit
612ea3c233
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@ -0,0 +1,8 @@
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s0 C
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s0b C
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s1 C
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s1b C
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sb C
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sm C
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sn C
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sqrt32_model C
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@ -0,0 +1,370 @@
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# /*------------------------------------------------------------\
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# | |
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# | File : Makefile |
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# | |
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# | Author : Jacomme Ludovic |
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# | |
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# \------------------------------------------------------------*/
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# /*------------------------------------------------------------\
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# | |
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# | Cells |
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# | |
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# \------------------------------------------------------------*/
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# /*------------------------------------------------------------\
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# | |
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# | Binary |
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# | |
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# \------------------------------------------------------------*/
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ALLIANCE_BIN=$(ALLIANCE_TOP)/bin
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VASY = $(ALLIANCE_BIN)/vasy
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ASIMUT = $(ALLIANCE_BIN)/asimut
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BOOM = $(ALLIANCE_BIN)/boom
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BOOG = $(ALLIANCE_BIN)/boog
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LOON = $(ALLIANCE_BIN)/loon
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OCP = $(ALLIANCE_BIN)/ocp
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NERO = $(ALLIANCE_BIN)/nero
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COUGAR = $(ALLIANCE_BIN)/cougar
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LVX = $(ALLIANCE_BIN)/lvx
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DRUC = $(ALLIANCE_BIN)/druc
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S2R = $(ALLIANCE_BIN)/s2r
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DREAL = $(ALLIANCE_BIN)/dreal
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GRAAL = $(ALLIANCE_BIN)/graal
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XSCH = $(ALLIANCE_BIN)/xsch
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XPAT = $(ALLIANCE_BIN)/xpat
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XFSM = $(ALLIANCE_BIN)/xfsm
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TOUCH = touch
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TARGET_LIB = $(ALLIANCE_TOP)/cells/sxlib
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RDS_TECHNO_SYMB = ../etc/techno-symb.rds
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RDS_TECHNO = ../etc/techno-035.rds
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SPI_MODEL = $(ALLIANCE_TOP)/etc/spimodel.cfg
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METAL_LEVEL = 5
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# /*------------------------------------------------------------\
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# | |
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# | Environement |
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# | |
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# \------------------------------------------------------------*/
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ENV_VASY = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
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MBK_CATAL_NAME=NO_CATAL; export MBK_CATAL_NAME
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ENV_BOOM = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
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ENV_BOOG = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
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MBK_IN_LO=vst; export MBK_IN_LO; \
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MBK_OUT_LO=vst; export MBK_OUT_LO; \
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MBK_TARGET_LIB=$(TARGET_LIB); export MBK_TARGET_LIB; \
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
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ENV_LOON = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
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MBK_IN_LO=vst; export MBK_IN_LO; \
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MBK_OUT_LO=vst; export MBK_OUT_LO; \
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MBK_TARGET_LIB=$(TARGET_LIB); export MBK_TARGET_LIB; \
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MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
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ENV_ASIMUT_VASY = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
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MBK_CATAL_NAME=CATAL_ASIMUT_VASY; export MBK_CATAL_NAME;\
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MBK_IN_LO=vst; export MBK_IN_LO;\
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MBK_OUT_LO=vst; export MBK_OUT_LO
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ENV_ASIMUT_SYNTH = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME;\
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MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
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MBK_IN_LO=vst; export MBK_IN_LO;\
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MBK_OUT_LO=vst; export MBK_OUT_LO
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ENV_OCP = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
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MBK_IN_LO=vst; export MBK_IN_LO; \
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MBK_OUT_LO=vst; export MBK_OUT_LO; \
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MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
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MBK_IN_PH=ap; export MBK_IN_PH; \
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MBK_OUT_PH=ap; export MBK_OUT_PH; \
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
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ENV_NERO = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
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MBK_IN_LO=vst; export MBK_IN_LO; \
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MBK_OUT_LO=vst; export MBK_OUT_LO; \
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MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
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MBK_IN_PH=ap; export MBK_IN_PH; \
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MBK_OUT_PH=ap; export MBK_OUT_PH; \
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
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ENV_COUGAR_SPI = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
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MBK_IN_LO=spi; export MBK_IN_LO; \
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MBK_OUT_LO=spi; export MBK_OUT_LO; \
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MBK_SPI_NAMEDNODES="true"; export MBK_SPI_NAMEDNODES; \
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MBK_SPI_MODEL=$(SPI_MODEL); export MBK_SPI_MODEL; \
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RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME; \
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RDS_IN=cif; export RDS_IN; \
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RDS_OUT=cif; export RDS_OUT; \
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MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
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MBK_IN_PH=ap; export MBK_IN_PH; \
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MBK_OUT_PH=ap; export MBK_OUT_PH; \
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
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ENV_COUGAR = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
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MBK_IN_LO=al; export MBK_IN_LO; \
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MBK_OUT_LO=al; export MBK_OUT_LO; \
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RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME; \
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RDS_IN=cif; export RDS_IN; \
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RDS_OUT=cif; export RDS_OUT; \
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MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
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MBK_IN_PH=ap; export MBK_IN_PH; \
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MBK_OUT_PH=ap; export MBK_OUT_PH; \
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
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ENV_LVX = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
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MBK_IN_LO=vst; export MBK_IN_LO; \
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MBK_OUT_LO=vst; export MBK_OUT_LO; \
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MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
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ENV_DRUC = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
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RDS_TECHNO_NAME=$(RDS_TECHNO_SYMB); export RDS_TECHNO_NAME; \
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MBK_IN_PH=ap; export MBK_IN_PH; \
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MBK_OUT_PH=ap; export MBK_OUT_PH; \
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MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
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ENV_S2R = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
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RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME; \
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RDS_IN=cif; export RDS_IN; \
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RDS_OUT=cif; export RDS_OUT; \
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MBK_IN_PH=ap; export MBK_IN_PH; \
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MBK_OUT_PH=ap; export MBK_OUT_PH; \
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MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
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all : sqrt32.cif
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# /*------------------------------------------------------------\
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# | |
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# | Vasy |
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# | |
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# \------------------------------------------------------------*/
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sqrt32.vst s0.vbe s0b.vbe s1.vbe s1b.vbe sb.vbe sm.vbe sn.vbe sqrt32_model.vbe : sqrt32.vhdl
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$(ENV_VASY); $(VASY) -a -B -o -p -I vhdl -H sqrt32
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# /*------------------------------------------------------------\
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# | |
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# | Asimut |
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# | |
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# \------------------------------------------------------------*/
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res_vasy_1.pat : sqrt32.vst s0.vbe s0b.vbe s1.vbe s1b.vbe sb.vbe sm.vbe sn.vbe sqrt32_model.vbe
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$(ENV_ASIMUT_VASY); $(ASIMUT) sqrt32 sqrt32 res_vasy_1
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res_synth_1.pat : sqrt32.vst s0.vst s0b.vst s1.vst s1b.vst sb.vst sm.vst sn.vst sqrt32_model.vst
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$(ENV_ASIMUT_SYNTH); $(ASIMUT) sqrt32 sqrt32 res_synth_1
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# /*------------------------------------------------------------\
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# | |
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# | Boom |
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# | |
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# \------------------------------------------------------------*/
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boom.done : s0_o.vbe s0b_o.vbe s1_o.vbe s1b_o.vbe sb_o.vbe sm_o.vbe sn_o.vbe sqrt32_model_o.vbe
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@$(TOUCH) boom.done
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s0_o.vbe : s0.vbe res_vasy_1.pat
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$(ENV_BOOM); $(BOOM) -VP s0 s0_o
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s0b_o.vbe : s0b.vbe res_vasy_1.pat
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$(ENV_BOOM); $(BOOM) -VP s0b s0b_o
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s1_o.vbe : s1.vbe res_vasy_1.pat
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$(ENV_BOOM); $(BOOM) -VP s1 s1_o
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s1b_o.vbe : s1b.vbe res_vasy_1.pat
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$(ENV_BOOM); $(BOOM) -VP s1b s1b_o
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sb_o.vbe : sb.vbe res_vasy_1.pat
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$(ENV_BOOM); $(BOOM) -VP sb sb_o
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sm_o.vbe : sm.vbe res_vasy_1.pat
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$(ENV_BOOM); $(BOOM) -VP sm sm_o
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sn_o.vbe : sn.vbe res_vasy_1.pat
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$(ENV_BOOM); $(BOOM) -VP sn sn_o
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sqrt32_model_o.vbe : sqrt32_model.vbe res_vasy_1.pat
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$(ENV_BOOM); $(BOOM) -VP sqrt32_model sqrt32_model_o
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# /*------------------------------------------------------------\
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# | |
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# | Boog |
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# | |
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# \------------------------------------------------------------*/
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boog.done : sqrt32.vst s0_o.vst s0b_o.vst s1_o.vst s1b_o.vst sb_o.vst sm_o.vst sn_o.vst sqrt32_model_o.vst
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@$(TOUCH) boog.done
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s0_o.vst : s0_o.vbe res_vasy_1.pat
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$(ENV_BOOG); $(BOOG) s0_o
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s0b_o.vst : s0b_o.vbe res_vasy_1.pat
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$(ENV_BOOG); $(BOOG) s0b_o
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s1_o.vst : s1_o.vbe res_vasy_1.pat
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$(ENV_BOOG); $(BOOG) s1_o
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s1b_o.vst : s1b_o.vbe res_vasy_1.pat
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$(ENV_BOOG); $(BOOG) s1b_o
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sb_o.vst : sb_o.vbe res_vasy_1.pat
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$(ENV_BOOG); $(BOOG) sb_o
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sm_o.vst : sm_o.vbe res_vasy_1.pat
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$(ENV_BOOG); $(BOOG) sm_o
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sn_o.vst : sn_o.vbe res_vasy_1.pat
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$(ENV_BOOG); $(BOOG) sn_o
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sqrt32_model_o.vst : sqrt32_model_o.vbe
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$(ENV_BOOG); $(BOOG) sqrt32_model_o
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# /*------------------------------------------------------------\
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# | |
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# | Loon |
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# | |
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# \------------------------------------------------------------*/
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loon.done : sqrt32.vst s0.vst s0b.vst s1.vst s1b.vst sb.vst sm.vst sn.vst sqrt32_model.vst
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@$(TOUCH) loon.done
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s0.vst : s0_o.vst res_vasy_1.pat
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$(ENV_LOON); $(LOON) s0_o s0
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s0b.vst : s0b_o.vst res_vasy_1.pat
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$(ENV_LOON); $(LOON) s0b_o s0b
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s1.vst : s1_o.vst res_vasy_1.pat
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$(ENV_LOON); $(LOON) s1_o s1
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s1b.vst : s1b_o.vst res_vasy_1.pat
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$(ENV_LOON); $(LOON) s1b_o s1b
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sb.vst : sb_o.vst res_vasy_1.pat
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$(ENV_LOON); $(LOON) sb_o sb
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sm.vst : sm_o.vst res_vasy_1.pat
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$(ENV_LOON); $(LOON) sm_o sm
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sn.vst : sn_o.vst res_vasy_1.pat
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$(ENV_LOON); $(LOON) sn_o sn
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sqrt32_model.vst : sqrt32_model_o.vst
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$(ENV_LOON); $(LOON) sqrt32_model_o sqrt32_model
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# /*------------------------------------------------------------\
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# | |
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# | OCP |
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# | |
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# \------------------------------------------------------------*/
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sqrt32_p.ap : res_synth_1.pat
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$(ENV_OCP); $(OCP) -v -ioc sqrt32 -gnuplot sqrt32 sqrt32_p
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# /*------------------------------------------------------------\
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# | |
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# | NERO |
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# | |
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# \------------------------------------------------------------*/
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sqrt32.ap : sqrt32_p.ap sqrt32.vst
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$(ENV_NERO); $(NERO) -V -$(METAL_LEVEL) -p sqrt32_p sqrt32 sqrt32
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# /*------------------------------------------------------------\
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# | |
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# | Cougar |
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# | |
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# \------------------------------------------------------------*/
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sqrt32_e.al : sqrt32.ap
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$(ENV_COUGAR); $(COUGAR) -v -ac sqrt32 sqrt32_e
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sqrt32_et.al : sqrt32.ap
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$(ENV_COUGAR); $(COUGAR) -v -t -ac sqrt32 sqrt32_et
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sqrt32_e.spi : sqrt32.ap sqrt32_e.al
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$(ENV_COUGAR_SPI); $(COUGAR) -v -ac sqrt32 sqrt32_e
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sqrt32_et.spi : sqrt32.ap sqrt32_e.al
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$(ENV_COUGAR_SPI); $(COUGAR) -v -t -ac sqrt32 sqrt32_et
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sqrt32_er.al : sqrt32.cif
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$(ENV_COUGAR); $(COUGAR) -v -r -t sqrt32 sqrt32_er
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# /*------------------------------------------------------------\
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# | |
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# | Lvx |
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# | |
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# \------------------------------------------------------------*/
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lvx.done : sqrt32.vst sqrt32_e.al
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$(ENV_LVX); $(LVX) vst al sqrt32 sqrt32_e -f
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$(TOUCH) lvx.done
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# /*------------------------------------------------------------\
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# | |
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# | Druc |
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# | |
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# \------------------------------------------------------------*/
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druc.done : lvx.done sqrt32.ap
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$(ENV_DRUC); $(DRUC) sqrt32
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$(TOUCH) druc.done
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# /*------------------------------------------------------------\
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# | |
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# | S2R |
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# | |
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# \------------------------------------------------------------*/
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sqrt32.cif : druc.done
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$(ENV_S2R); $(S2R) -v -t sqrt32
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# /*------------------------------------------------------------\
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# | |
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# | TOOLS |
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# | |
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# \------------------------------------------------------------*/
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graal: sqrt32.ap
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$(ENV_S2R); $(GRAAL) -l sqrt32
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xsch: sqrt32.vst
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$(ENV_LOON); $(XSCH) -l sqrt32
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xscht: sqrt32_et.al
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$(ENV_COUGAR); $(XSCH) -l sqrt32_et
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xpat: res_synth_1.pat
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$(ENV_ASIMUT_SYNTH); $(XPAT) -l res_synth_1
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dreal: sqrt32.cif
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$(ENV_S2R); $(DREAL) -l sqrt32
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# /*------------------------------------------------------------\
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# | |
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# | Clean |
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# | |
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# \------------------------------------------------------------*/
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realclean : clean
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clean :
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$(RM) -f *.vst *.vbe *.boom *.done *.xsc *.al *.ap *.gpl *.gds \
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*.log *.drc *.cif *.fin *.dat *.out sqrt32_e.spi res_synth_1.pat \
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res_vasy_1.pat
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@ -0,0 +1,18 @@
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# /*------------------------------------------------------------\
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# | |
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# | File : README |
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# | |
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# | Author : Jacomme Ludovic |
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# | |
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# \------------------------------------------------------------*/
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This directory contains the VHDL description of combinatorial 32 bits
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sqrt chip and the associated stimuli file, and also a configuration file for IO
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placement (used during the Place and Route step).
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The Makefile set environement variables properly and run Alliance tools,
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following each step of the design flow from VHDL up to real layout in a
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pseudo 0.35 techno.
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The environement variable ALLIANCE_TOP as to be set.
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@ -0,0 +1,16 @@
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity S0 is
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port ( x : in std_logic;
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u : in std_logic;
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d : out std_logic;
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bo : out std_logic);
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end S0;
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architecture circuits of S0 is
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begin -- circuits of S0
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bo <= not x;
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d <= not x when u='1' else x;
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end circuits; -- of S0
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@ -0,0 +1,12 @@
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library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
|
||||
entity S0b is
|
||||
port ( x : in std_logic;
|
||||
bo : out std_logic);
|
||||
end S0b;
|
||||
|
||||
architecture circuits of S0b is
|
||||
begin -- circuits of S0b
|
||||
bo <= not x;
|
||||
end circuits; -- of S0b
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
|
||||
entity S1 is -- subtractor multiplexor
|
||||
port ( x : in std_logic;
|
||||
b : in std_logic;
|
||||
u : in std_logic;
|
||||
d : out std_logic;
|
||||
bo : out std_logic);
|
||||
end S1;
|
||||
|
||||
architecture circuits of S1 is
|
||||
signal t100, t001, td : std_logic;
|
||||
begin -- circuits of S1
|
||||
t001 <= (not x) and b;
|
||||
t100 <= x and (not b);
|
||||
bo <= t001;
|
||||
td <= t100 or t001;
|
||||
d <= td when u='1' else x;
|
||||
end circuits; -- of S1
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
|
||||
entity S1b is
|
||||
port ( x : in std_logic;
|
||||
b : in std_logic;
|
||||
bo : out std_logic);
|
||||
end S1b;
|
||||
|
||||
architecture circuits of S1b is
|
||||
begin -- circuits of S1b
|
||||
bo <= (not x) and b;
|
||||
end circuits; -- of S1b
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
|
||||
entity Sb is
|
||||
port ( x : in std_logic;
|
||||
y : in std_logic;
|
||||
b : in std_logic;
|
||||
bo : out std_logic);
|
||||
end Sb;
|
||||
|
||||
architecture circuits of Sb is
|
||||
signal t011, t111, t010, t001 : std_logic;
|
||||
begin -- circuits of Sb
|
||||
t011 <= (not x) and y and b;
|
||||
t111 <= x and y and b;
|
||||
t010 <= (not x) and y and (not b);
|
||||
t001 <= (not x) and (not y) and b;
|
||||
bo <= t011 or t111 or t010 or t001;
|
||||
end circuits; -- of Sb
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
|
||||
entity Sm is -- subtractor multiplexor
|
||||
port ( x : in std_logic;
|
||||
y : in std_logic;
|
||||
b : in std_logic;
|
||||
u : in std_logic;
|
||||
d : out std_logic;
|
||||
bo : out std_logic);
|
||||
end Sm;
|
||||
|
||||
architecture circuits of Sm is
|
||||
signal t011, t111, t010, t001, t100, td : std_logic;
|
||||
begin -- circuits of Sm
|
||||
t011 <= (not x) and y and b;
|
||||
t111 <= x and y and b;
|
||||
t010 <= (not x) and y and (not b);
|
||||
t001 <= (not x) and (not y) and b;
|
||||
t100 <= x and (not y) and (not b);
|
||||
bo <= t011 or t111 or t010 or t001;
|
||||
td <= t100 or t001 or t010 or t111;
|
||||
d <= td when u='1' else x;
|
||||
end circuits; -- of Sm
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
|
||||
entity Sn is -- subtractor multiplexor
|
||||
port ( x : in std_logic;
|
||||
b : in std_logic;
|
||||
bo : out std_logic);
|
||||
end Sn;
|
||||
|
||||
architecture circuits of Sn is
|
||||
begin -- circuits of Sn
|
||||
bo <= (not x) nand b; -- complemented
|
||||
end circuits; -- of Sn
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
|
||||
TOP ( # IOs are ordered from left to right
|
||||
(IOPIN p(31).0 );
|
||||
(IOPIN p(30).0 );
|
||||
(IOPIN p(29).0 );
|
||||
(IOPIN p(28).0 );
|
||||
(IOPIN p(27).0 );
|
||||
(IOPIN p(26).0 );
|
||||
(IOPIN p(25).0 );
|
||||
(IOPIN p(24).0 );
|
||||
(IOPIN p(23).0 );
|
||||
(IOPIN p(22).0 );
|
||||
(IOPIN p(21).0 );
|
||||
(IOPIN p(20).0 );
|
||||
(IOPIN p(19).0 );
|
||||
(IOPIN p(18).0 );
|
||||
(IOPIN p(17).0 );
|
||||
(IOPIN p(16).0 );
|
||||
(IOPIN p(15).0 );
|
||||
(IOPIN p(14).0 );
|
||||
(IOPIN p(13).0 );
|
||||
(IOPIN p(12).0 );
|
||||
(IOPIN p(11).0 );
|
||||
(IOPIN p(10).0 );
|
||||
(IOPIN p(9).0 );
|
||||
(IOPIN p(8).0 );
|
||||
(IOPIN p(7).0 );
|
||||
(IOPIN p(6).0 );
|
||||
(IOPIN p(5).0 );
|
||||
(IOPIN p(4).0 );
|
||||
(IOPIN p(3).0 );
|
||||
(IOPIN p(2).0 );
|
||||
(IOPIN p(1).0 );
|
||||
(IOPIN p(0).0 );
|
||||
)
|
||||
BOTTOM ( # IOs are ordered from left to right
|
||||
(IOPIN u(15).0 );
|
||||
(IOPIN u(14).0 );
|
||||
(IOPIN u(13).0 );
|
||||
(IOPIN u(12).0 );
|
||||
(IOPIN u(11).0 );
|
||||
(IOPIN u(10).0 );
|
||||
(IOPIN u(9).0 );
|
||||
(IOPIN u(8).0 );
|
||||
(IOPIN u(7).0 );
|
||||
(IOPIN u(6).0 );
|
||||
(IOPIN u(5).0 );
|
||||
(IOPIN u(4).0 );
|
||||
(IOPIN u(3).0 );
|
||||
(IOPIN u(2).0 );
|
||||
(IOPIN u(1).0 );
|
||||
(IOPIN u(0).0 );
|
||||
)
|
||||
IGNORE ( # IOs are ignored(not placed) by IO Placer
|
||||
)
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
|
||||
in P (31 downto 0) X;;;
|
||||
out U (15 downto 0) X;;;
|
||||
in vss B;;
|
||||
in vdd B;;
|
||||
|
||||
begin
|
||||
|
||||
-- Pattern description :
|
||||
-- P U V V
|
||||
-- P U V V
|
||||
-- P U V V
|
||||
-- P U V V
|
||||
-- P U V V
|
||||
|
||||
< +50ns>: 00000004 ?**** 0 1;
|
||||
< +50ns>: 00000004 ?**** 0 1;
|
||||
< +50ns>: 00000010 ?**** 0 1;
|
||||
< +50ns>: 00000010 ?**** 0 1;
|
||||
< +50ns>: 00000120 ?**** 0 1;
|
||||
< +50ns>: 00000120 ?**** 0 1;
|
||||
< +50ns>: 7fffffff ?**** 0 1;
|
||||
< +50ns>: 7fffffff ?**** 0 1;
|
||||
|
||||
end;
|
||||
|
|
@ -0,0 +1,305 @@
|
|||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
|
||||
entity sqrt32 is
|
||||
port ( P : in std_logic_vector(31 downto 0);
|
||||
U : out std_logic_vector(15 downto 0));
|
||||
end sqrt32;
|
||||
|
||||
architecture circuits of sqrt32 is
|
||||
|
||||
component S0
|
||||
port ( x : in std_logic;
|
||||
u : in std_logic;
|
||||
d : out std_logic;
|
||||
bo : out std_logic);
|
||||
end component;
|
||||
component S0b
|
||||
port ( x : in std_logic;
|
||||
bo : out std_logic);
|
||||
end component;
|
||||
component S1 -- subtractor multiplexor
|
||||
port ( x : in std_logic;
|
||||
b : in std_logic;
|
||||
u : in std_logic;
|
||||
d : out std_logic;
|
||||
bo : out std_logic);
|
||||
end component;
|
||||
component S1b
|
||||
port ( x : in std_logic;
|
||||
b : in std_logic;
|
||||
bo : out std_logic);
|
||||
end component;
|
||||
component Sb
|
||||
port ( x : in std_logic;
|
||||
y : in std_logic;
|
||||
b : in std_logic;
|
||||
bo : out std_logic);
|
||||
end component;
|
||||
component Sm -- subtractor multiplexor
|
||||
port ( x : in std_logic;
|
||||
y : in std_logic;
|
||||
b : in std_logic;
|
||||
u : in std_logic;
|
||||
d : out std_logic;
|
||||
bo : out std_logic);
|
||||
end component;
|
||||
component Sn -- subtractor multiplexor
|
||||
port ( x : in std_logic;
|
||||
b : in std_logic;
|
||||
bo : out std_logic);
|
||||
end component;
|
||||
signal b0000, b0001, b0002, b0003, b0004, b0005, b0006, b0007, b0008,
|
||||
b0009, b0010, b0011, b0012, b0013, b0014, b0015, b0016,
|
||||
b0017 : std_logic;
|
||||
signal x0102, x0103, x0104, x0105, x0106, x0107, x0108, x0109, x0110,
|
||||
x0111, x0112, x0113, x0114, x0115, x0116, x0117 : std_logic;
|
||||
signal b0102, b0103, b0104, b0105, b0106, b0107, b0108, b0109, b0110,
|
||||
b0111, b0112, b0113, b0114, b0115, b0116, b0117, b0118 : std_logic;
|
||||
signal x0204, x0205, x0206, x0207, x0208, x0209, x0210, x0211, x0212,
|
||||
x0213, x0214, x0215, x0216, x0217, x0218 : std_logic;
|
||||
signal b0204, b0205, b0206, b0207, b0208, b0209, b0210, b0211, b0212,
|
||||
b0213, b0214, b0215, b0216, b0217, b0218, b0219 : std_logic;
|
||||
signal x0306, x0307, x0308, x0309, x0310, x0311, x0312, x0313, x0314,
|
||||
x0315, x0316, x0317, x0318, x0319 : std_logic;
|
||||
signal b0306, b0307, b0308, b0309, b0310, b0311, b0312, b0313, b0314,
|
||||
b0315, b0316, b0317, b0318, b0319, b0320 : std_logic;
|
||||
signal x0408, x0409, x0410, x0411, x0412, x0413, x0414, x0415, x0416,
|
||||
x0417, x0418, x0419, x0420 : std_logic;
|
||||
signal b0408, b0409, b0410, b0411, b0412, b0413, b0414, b0415, b0416,
|
||||
b0417, b0418, b0419, b0420, b0421 : std_logic;
|
||||
signal x0510, x0511, x0512, x0513, x0514, x0515, x0516, x0517, x0518,
|
||||
x0519, x0520, x0521 : std_logic;
|
||||
signal b0510, b0511, b0512, b0513, b0514, b0515, b0516, b0517, b0518,
|
||||
b0519, b0520, b0521, b0522 : std_logic;
|
||||
signal x0612, x0613, x0614, x0615, x0616, x0617, x0618, x0619, x0620,
|
||||
x0621, x0622 : std_logic;
|
||||
signal b0612, b0613, b0614, b0615, b0616, b0617, b0618, b0619, b0620,
|
||||
b0621, b0622, b0623 : std_logic;
|
||||
signal x0714, x0715, x0716, x0717, x0718, x0719, x0720, x0721, x0722,
|
||||
x0723 : std_logic;
|
||||
signal b0714, b0715, b0716, b0717, b0718, b0719, b0720, b0721, b0722,
|
||||
b0723, b0724 : std_logic;
|
||||
signal x0816, x0817, x0818, x0819, x0820, x0821, x0822, x0823,
|
||||
x0824 : std_logic;
|
||||
signal b0816, b0817, b0818, b0819, b0820, b0821, b0822, b0823,
|
||||
b0824, b0825 : std_logic;
|
||||
signal x0918, x0919, x0920, x0921, x0922, x0923, x0924, x0925 : std_logic;
|
||||
signal b0918, b0919, b0920, b0921, b0922, b0923, b0924, b0925,
|
||||
b0926 : std_logic;
|
||||
signal x1020, x1021, x1022, x1023, x1024, x1025, x1026 : std_logic;
|
||||
signal b1020, b1021, b1022, b1023, b1024, b1025, b1026, b1027 : std_logic;
|
||||
signal x1122, x1123, x1124, x1125, x1126, x1127 : std_logic;
|
||||
signal b1122, b1123, b1124, b1125, b1126, b1127, b1128 : std_logic;
|
||||
signal x1224, x1225, x1226, x1227, x1228 : std_logic;
|
||||
signal b1224, b1225, b1226, b1227, b1228, b1229 : std_logic;
|
||||
signal x1326, x1327, x1328, x1329 : std_logic;
|
||||
signal b1326, b1327, b1328, b1329, b1330 : std_logic;
|
||||
signal x1428, x1429, x1430 : std_logic;
|
||||
signal b1428, b1429, b1430, b1431 : std_logic;
|
||||
signal x1530, x1531 : std_logic;
|
||||
signal b1530, b1531, bxx : std_logic;
|
||||
begin -- circuits of sqrt32
|
||||
-- x y b u d bo
|
||||
s1530: S0 port map(P(30), b1531, x1530, b1530);
|
||||
s1531: S1 port map(P(31), b1530, b1531, x1531, bxx );
|
||||
b1531 <= not bxx;
|
||||
|
||||
s1428: S0 port map(P(28), b1431, x1428, b1428);
|
||||
s1429: S1 port map(P(29), b1428, b1431, x1429, b1429);
|
||||
s1430: Sm port map(x1530, b1531, b1429, b1431, x1430, b1430);
|
||||
s1431: Sn port map(x1531, b1430, b1431);
|
||||
|
||||
s1326: S0 port map(P(26), b1330, x1326, b1326);
|
||||
s1327: S1 port map(P(27), b1326, b1330, x1327, b1327);
|
||||
s1328: Sm port map(x1428, b1431, b1327, b1330, x1328, b1328);
|
||||
s1329: Sm port map(x1429, b1531, b1328, b1330, x1329, b1329);
|
||||
s1330: Sn port map(x1430, b1329, b1330);
|
||||
|
||||
s1224: S0 port map(P(24), b1229, x1224, b1224);
|
||||
s1225: S1 port map(P(25), b1224, b1229, x1225, b1225);
|
||||
s1226: Sm port map(x1326, b1330, b1225, b1229, x1226, b1226);
|
||||
s1227: Sm port map(x1327, b1431, b1226, b1229, x1227, b1227);
|
||||
s1228: Sm port map(x1328, b1531, b1227, b1229, x1228, b1228);
|
||||
s1229: Sn port map(x1329, b1228, b1229);
|
||||
|
||||
s1122: S0 port map(P(22), b1128, x1122, b1122);
|
||||
s1123: S1 port map(P(23), b1122, b1128, x1123, b1123);
|
||||
s1124: Sm port map(x1224, b1229, b1123, b1128, x1124, b1124);
|
||||
s1125: Sm port map(x1225, b1330, b1124, b1128, x1125, b1125);
|
||||
s1126: Sm port map(x1226, b1431, b1125, b1128, x1126, b1126);
|
||||
s1127: Sm port map(x1227, b1531, b1126, b1128, x1127, b1127);
|
||||
s1128: Sn port map(x1228, b1127, b1128);
|
||||
|
||||
s1020: S0 port map(P(20), b1027, x1020, b1020);
|
||||
s1021: S1 port map(P(21), b1020, b1027, x1021, b1021);
|
||||
s1022: Sm port map(x1122, b1128, b1021, b1027, x1022, b1022);
|
||||
s1023: Sm port map(x1123, b1229, b1022, b1027, x1023, b1023);
|
||||
s1024: Sm port map(x1124, b1330, b1023, b1027, x1024, b1024);
|
||||
s1025: Sm port map(x1125, b1431, b1024, b1027, x1025, b1025);
|
||||
s1026: Sm port map(x1126, b1531, b1025, b1027, x1026, b1026);
|
||||
s1027: Sn port map(x1127, b1026, b1027);
|
||||
|
||||
s0918: S0 port map(P(18), b0926, x0918, b0918);
|
||||
s0919: S1 port map(P(19), b0918, b0926, x0919, b0919);
|
||||
s0920: Sm port map(x1020, b1027, b0919, b0926, x0920, b0920);
|
||||
s0921: Sm port map(x1021, b1128, b0920, b0926, x0921, b0921);
|
||||
s0922: Sm port map(x1022, b1229, b0921, b0926, x0922, b0922);
|
||||
s0923: Sm port map(x1023, b1330, b0922, b0926, x0923, b0923);
|
||||
s0924: Sm port map(x1024, b1431, b0923, b0926, x0924, b0924);
|
||||
s0925: Sm port map(x1025, b1531, b0924, b0926, x0925, b0925);
|
||||
s0926: Sn port map(x1026, b0925, b0926);
|
||||
|
||||
s0816: S0 port map(P(16), b0825, x0816, b0816);
|
||||
s0817: S1 port map(P(17), b0816, b0825, x0817, b0817);
|
||||
s0818: Sm port map(x0918, b0926, b0817, b0825, x0818, b0818);
|
||||
s0819: Sm port map(x0919, b1027, b0818, b0825, x0819, b0819);
|
||||
s0820: Sm port map(x0920, b1128, b0819, b0825, x0820, b0820);
|
||||
s0821: Sm port map(x0921, b1229, b0820, b0825, x0821, b0821);
|
||||
s0822: Sm port map(x0922, b1330, b0821, b0825, x0822, b0822);
|
||||
s0823: Sm port map(x0923, b1431, b0822, b0825, x0823, b0823);
|
||||
s0824: Sm port map(x0924, b1531, b0823, b0825, x0824, b0824);
|
||||
s0825: Sn port map(x0925, b0824, b0825);
|
||||
|
||||
s0714: S0 port map(P(14), b0724, x0714, b0714);
|
||||
s0715: S1 port map(P(15), b0714, b0724, x0715, b0715);
|
||||
s0716: Sm port map(x0816, b0825, b0715, b0724, x0716, b0716);
|
||||
s0717: Sm port map(x0817, b0926, b0716, b0724, x0717, b0717);
|
||||
s0718: Sm port map(x0818, b1027, b0717, b0724, x0718, b0718);
|
||||
s0719: Sm port map(x0819, b1128, b0718, b0724, x0719, b0719);
|
||||
s0720: Sm port map(x0820, b1229, b0719, b0724, x0720, b0720);
|
||||
s0721: Sm port map(x0821, b1330, b0720, b0724, x0721, b0721);
|
||||
s0722: Sm port map(x0822, b1431, b0721, b0724, x0722, b0722);
|
||||
s0723: Sm port map(x0823, b1531, b0722, b0724, x0723, b0723);
|
||||
s0724: Sn port map(x0824, b0723, b0724);
|
||||
|
||||
s0612: S0 port map(P(12), b0623, x0612, b0612);
|
||||
s0613: S1 port map(P(13), b0612, b0623, x0613, b0613);
|
||||
s0614: Sm port map(x0714, b0724, b0613, b0623, x0614, b0614);
|
||||
s0615: Sm port map(x0715, b0825, b0614, b0623, x0615, b0615);
|
||||
s0616: Sm port map(x0716, b0926, b0615, b0623, x0616, b0616);
|
||||
s0617: Sm port map(x0717, b1027, b0616, b0623, x0617, b0617);
|
||||
s0618: Sm port map(x0718, b1128, b0617, b0623, x0618, b0618);
|
||||
s0619: Sm port map(x0719, b1229, b0618, b0623, x0619, b0619);
|
||||
s0620: Sm port map(x0720, b1330, b0619, b0623, x0620, b0620);
|
||||
s0621: Sm port map(x0721, b1431, b0620, b0623, x0621, b0621);
|
||||
s0622: Sm port map(x0722, b1531, b0621, b0623, x0622, b0622);
|
||||
s0623: Sn port map(x0723, b0622, b0623);
|
||||
|
||||
s0510: S0 port map(P(10), b0522, x0510, b0510);
|
||||
s0511: S1 port map(P(11), b0510, b0522, x0511, b0511);
|
||||
s0512: Sm port map(x0612, b0622, b0511, b0522, x0512, b0512);
|
||||
s0513: Sm port map(x0613, b0723, b0512, b0522, x0513, b0513);
|
||||
s0514: Sm port map(x0614, b0825, b0513, b0522, x0514, b0514);
|
||||
s0515: Sm port map(x0615, b0926, b0514, b0522, x0515, b0515);
|
||||
s0516: Sm port map(x0616, b1027, b0515, b0522, x0516, b0516);
|
||||
s0517: Sm port map(x0617, b1128, b0516, b0522, x0517, b0517);
|
||||
s0518: Sm port map(x0618, b1229, b0517, b0522, x0518, b0518);
|
||||
s0519: Sm port map(x0619, b1330, b0518, b0522, x0519, b0519);
|
||||
s0520: Sm port map(x0620, b1431, b0519, b0522, x0520, b0520);
|
||||
s0521: Sm port map(x0621, b1531, b0520, b0522, x0521, b0521);
|
||||
s0522: Sn port map(x0622, b0521, b0522);
|
||||
|
||||
s0408: S0 port map(P(8), b0421, x0408, b0408);
|
||||
s0409: S1 port map(P(9), b0408, b0421, x0409, b0409);
|
||||
s0410: Sm port map(x0510, b0522, b0409, b0421, x0410, b0410);
|
||||
s0411: Sm port map(x0511, b0623, b0410, b0421, x0411, b0411);
|
||||
s0412: Sm port map(x0512, b0724, b0411, b0421, x0412, b0412);
|
||||
s0413: Sm port map(x0513, b0825, b0412, b0421, x0413, b0413);
|
||||
s0414: Sm port map(x0514, b0926, b0413, b0421, x0414, b0414);
|
||||
s0415: Sm port map(x0515, b1027, b0414, b0421, x0415, b0415);
|
||||
s0416: Sm port map(x0516, b1128, b0415, b0421, x0416, b0416);
|
||||
s0417: Sm port map(x0517, b1229, b0416, b0421, x0417, b0417);
|
||||
s0418: Sm port map(x0518, b1330, b0417, b0421, x0418, b0418);
|
||||
s0419: Sm port map(x0519, b1431, b0418, b0421, x0419, b0419);
|
||||
s0420: Sm port map(x0520, b1531, b0419, b0421, x0420, b0420);
|
||||
s0421: Sn port map(x0521, b0420, b0421);
|
||||
|
||||
s0306: S0 port map(P(6), b0320, x0306, b0306);
|
||||
s0307: S1 port map(P(7), b0306, b0320, x0307, b0307);
|
||||
s0308: Sm port map(x0408, b0421, b0307, b0320, x0308, b0308);
|
||||
s0309: Sm port map(x0409, b0522, b0308, b0320, x0309, b0309);
|
||||
s0310: Sm port map(x0410, b0623, b0309, b0320, x0310, b0310);
|
||||
s0311: Sm port map(x0411, b0724, b0310, b0320, x0311, b0311);
|
||||
s0312: Sm port map(x0412, b0825, b0311, b0320, x0312, b0312);
|
||||
s0313: Sm port map(x0413, b0926, b0312, b0320, x0313, b0313);
|
||||
s0314: Sm port map(x0414, b1027, b0313, b0320, x0314, b0314);
|
||||
s0315: Sm port map(x0415, b1128, b0314, b0320, x0315, b0315);
|
||||
s0316: Sm port map(x0416, b1229, b0315, b0320, x0316, b0316);
|
||||
s0317: Sm port map(x0417, b1330, b0316, b0320, x0317, b0317);
|
||||
s0318: Sm port map(x0418, b1431, b0317, b0320, x0318, b0318);
|
||||
s0319: Sm port map(x0419, b1531, b0318, b0320, x0319, b0319);
|
||||
s0320: Sn port map(x0420, b0319, b0320);
|
||||
|
||||
s0204: S0 port map(P(4), b0219, x0204, b0204);
|
||||
s0205: S1 port map(P(5), b0204, b0219, x0205, b0205);
|
||||
s0206: Sm port map(x0306, b0320, b0205, b0219, x0206, b0206);
|
||||
s0207: Sm port map(x0307, b0421, b0206, b0219, x0207, b0207);
|
||||
s0208: Sm port map(x0308, b0522, b0207, b0219, x0208, b0208);
|
||||
s0209: Sm port map(x0309, b0623, b0208, b0219, x0209, b0209);
|
||||
s0210: Sm port map(x0310, b0724, b0209, b0219, x0210, b0210);
|
||||
s0211: Sm port map(x0311, b0825, b0210, b0219, x0211, b0211);
|
||||
s0212: Sm port map(x0312, b0926, b0211, b0219, x0212, b0212);
|
||||
s0213: Sm port map(x0313, b1027, b0212, b0219, x0213, b0213);
|
||||
s0214: Sm port map(x0314, b1128, b0213, b0219, x0214, b0214);
|
||||
s0215: Sm port map(x0315, b1229, b0214, b0219, x0215, b0215);
|
||||
s0216: Sm port map(x0316, b1330, b0215, b0219, x0216, b0216);
|
||||
s0217: Sm port map(x0317, b1431, b0216, b0219, x0217, b0217);
|
||||
s0218: Sm port map(x0318, b1531, b0217, b0219, x0218, b0218);
|
||||
s0219: Sn port map(x0319, b0218, b0219);
|
||||
|
||||
s0102: S0 port map(P(2), b0118, x0102, b0102);
|
||||
s0103: S1 port map(P(3), b0102, b0118, x0103, b0103);
|
||||
s0104: Sm port map(x0204, b0219, b0103, b0118, x0104, b0104);
|
||||
s0105: Sm port map(x0205, b0320, b0104, b0118, x0105, b0105);
|
||||
s0106: Sm port map(x0206, b0421, b0105, b0118, x0106, b0106);
|
||||
s0107: Sm port map(x0207, b0522, b0106, b0118, x0107, b0107);
|
||||
s0108: Sm port map(x0208, b0623, b0107, b0118, x0108, b0108);
|
||||
s0109: Sm port map(x0209, b0724, b0108, b0118, x0109, b0109);
|
||||
s0110: Sm port map(x0210, b0825, b0109, b0118, x0110, b0110);
|
||||
s0111: Sm port map(x0211, b0926, b0110, b0118, x0111, b0111);
|
||||
s0112: Sm port map(x0212, b1027, b0111, b0118, x0112, b0112);
|
||||
s0113: Sm port map(x0213, b1128, b0112, b0118, x0113, b0113);
|
||||
s0114: Sm port map(x0214, b1229, b0113, b0118, x0114, b0114);
|
||||
s0115: Sm port map(x0215, b1330, b0114, b0118, x0115, b0115);
|
||||
s0116: Sm port map(x0216, b1431, b0115, b0118, x0116, b0116);
|
||||
s0117: Sm port map(x0217, b1531, b0116, b0118, x0117, b0117);
|
||||
s0118: Sn port map(x0218, b0117, b0118);
|
||||
|
||||
s0000: S0b port map(P(0), b0000);
|
||||
s0001: S1b port map(P(1), b0000, b0001);
|
||||
s0002: Sb port map(x0102, b0118, b0001, b0002);
|
||||
s0003: Sb port map(x0103, b0219, b0002, b0003);
|
||||
s0004: Sb port map(x0104, b0320, b0003, b0004);
|
||||
s0005: Sb port map(x0105, b0421, b0004, b0005);
|
||||
s0006: Sb port map(x0106, b0522, b0005, b0006);
|
||||
s0007: Sb port map(x0107, b0623, b0006, b0007);
|
||||
s0008: Sb port map(x0108, b0724, b0007, b0008);
|
||||
s0009: Sb port map(x0109, b0825, b0008, b0009);
|
||||
s0010: Sb port map(x0110, b0926, b0009, b0010);
|
||||
s0011: Sb port map(x0111, b1027, b0010, b0011);
|
||||
s0012: Sb port map(x0112, b1128, b0011, b0012);
|
||||
s0013: Sb port map(x0113, b1229, b0012, b0013);
|
||||
s0014: Sb port map(x0114, b1330, b0013, b0014);
|
||||
s0015: Sb port map(x0115, b1431, b0014, b0015);
|
||||
s0016: Sb port map(x0116, b1531, b0015, b0016);
|
||||
s0017: Sn port map(x0117, b0016, b0017);
|
||||
|
||||
U(0) <= b0017; -- set output bits
|
||||
U(1) <= b0118;
|
||||
U(2) <= b0219;
|
||||
U(3) <= b0320;
|
||||
U(4) <= b0421;
|
||||
U(5) <= b0522;
|
||||
U(6) <= b0623;
|
||||
U(7) <= b0724;
|
||||
U(8) <= b0825;
|
||||
U(9) <= b0926;
|
||||
U(10) <= b1027;
|
||||
U(11) <= b1128;
|
||||
U(12) <= b1229;
|
||||
U(13) <= b1330;
|
||||
U(14) <= b1431;
|
||||
U(15) <= b1531;
|
||||
|
||||
end circuits; -- of sqrt32
|
||||
Loading…
Reference in New Issue