- Combinatorial 8 bits multiplier
- Synchronous greatest common divisor (with FSM)
This commit is contained in:
Ludovic Jacomme
parent
bcd0c009c6
commit
f0eebe930e
|
|
@ -29,7 +29,6 @@ COUGAR = $(ALLIANCE_BIN)/cougar
|
|||
LVX = $(ALLIANCE_BIN)/lvx
|
||||
DRUC = $(ALLIANCE_BIN)/druc
|
||||
S2R = $(ALLIANCE_BIN)/s2r
|
||||
BLAST = $(ALLIANCE_BIN)/sblast
|
||||
|
||||
DREAL = $(ALLIANCE_BIN)/dreal
|
||||
GRAAL = $(ALLIANCE_BIN)/graal
|
||||
|
|
|
|||
|
|
@ -29,7 +29,6 @@ COUGAR = $(ALLIANCE_BIN)/cougar
|
|||
LVX = $(ALLIANCE_BIN)/lvx
|
||||
DRUC = $(ALLIANCE_BIN)/druc
|
||||
S2R = $(ALLIANCE_BIN)/s2r
|
||||
BLAST = $(ALLIANCE_BIN)/sblast
|
||||
|
||||
DREAL = $(ALLIANCE_BIN)/dreal
|
||||
GRAAL = $(ALLIANCE_BIN)/graal
|
||||
|
|
|
|||
|
|
@ -29,7 +29,6 @@ COUGAR = $(ALLIANCE_BIN)/cougar
|
|||
LVX = $(ALLIANCE_BIN)/lvx
|
||||
DRUC = $(ALLIANCE_BIN)/druc
|
||||
S2R = $(ALLIANCE_BIN)/s2r
|
||||
BLAST = $(ALLIANCE_BIN)/sblast
|
||||
|
||||
DREAL = $(ALLIANCE_BIN)/dreal
|
||||
GRAAL = $(ALLIANCE_BIN)/graal
|
||||
|
|
|
|||
|
|
@ -1,15 +1,3 @@
|
|||
# Copyright (c) 1997 by Cadence. All rights reserved.
|
||||
###################################################################
|
||||
# In each of TOP()/BOTTOM()/LEFT()/RIGHT() section, there are #
|
||||
# placed IOs. In the IGNORE() section, the IOs are ignored #
|
||||
# by the IOPlacer. In every section, the IO syntax could be: #
|
||||
# for pin: (IOPIN iopinName.0 ); #
|
||||
# for pad: iopadName orientation ; #
|
||||
# for space: SPACE value; #
|
||||
# The capital words are keywords. orientation is not required. #
|
||||
# The value is the space between the IO above and the IO below it.#
|
||||
###################################################################
|
||||
|
||||
TOP ( # IOs are ordered from left to right
|
||||
(IOPIN x(3).0 );
|
||||
(IOPIN x(2).0 );
|
||||
|
|
|
|||
|
|
@ -344,6 +344,6 @@ realclean : clean
|
|||
|
||||
clean :
|
||||
$(RM) -f *.vst multi8_et.spi *.vbe res_*.pat *.boom *.done *.xsc *.gpl \
|
||||
*.ap *.drc *.dat *.gds blast.fin *.cif *.rep \
|
||||
*.ap *.drc *.dat *.gds *.cif *.rep \
|
||||
*.log *.out *.raw *.al
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,345 @@
|
|||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | File : Makefile |
|
||||
# | |
|
||||
# | Author : Jacomme Ludovic |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | Cells |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | Binary |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
|
||||
ALLIANCE_BIN=$(ALLIANCE_TOP)/bin
|
||||
|
||||
VASY = $(ALLIANCE_BIN)/vasy
|
||||
ASIMUT = $(ALLIANCE_BIN)/asimut
|
||||
BOOM = $(ALLIANCE_BIN)/boom
|
||||
BOOG = $(ALLIANCE_BIN)/boog
|
||||
LOON = $(ALLIANCE_BIN)/loon
|
||||
OCP = $(ALLIANCE_BIN)/ocp
|
||||
NERO = $(ALLIANCE_BIN)/nero
|
||||
COUGAR = $(ALLIANCE_BIN)/cougar
|
||||
LVX = $(ALLIANCE_BIN)/lvx
|
||||
DRUC = $(ALLIANCE_BIN)/druc
|
||||
S2R = $(ALLIANCE_BIN)/s2r
|
||||
|
||||
DREAL = $(ALLIANCE_BIN)/dreal
|
||||
GRAAL = $(ALLIANCE_BIN)/graal
|
||||
XSCH = $(ALLIANCE_BIN)/xsch
|
||||
XPAT = $(ALLIANCE_BIN)/xpat
|
||||
XFSM = $(ALLIANCE_BIN)/xfsm
|
||||
|
||||
TOUCH = touch
|
||||
|
||||
TARGET_LIB = $(ALLIANCE_TOP)/cells/sxlib
|
||||
RDS_TECHNO_SYMB = ../etc/techno-symb.rds
|
||||
RDS_TECHNO = ../etc/techno-035.rds
|
||||
SPI_MODEL = $(ALLIANCE_TOP)/etc/spimodel.cfg
|
||||
METAL_LEVEL = 2
|
||||
|
||||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | Environement |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
|
||||
ENV_VASY = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
|
||||
MBK_CATAL_NAME=NO_CATAL; export MBK_CATAL_NAME
|
||||
|
||||
ENV_BOOM = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
|
||||
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
|
||||
|
||||
ENV_BOOG = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
|
||||
MBK_IN_LO=vst; export MBK_IN_LO; \
|
||||
MBK_OUT_LO=vst; export MBK_OUT_LO; \
|
||||
MBK_TARGET_LIB=$(TARGET_LIB); export MBK_TARGET_LIB; \
|
||||
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
|
||||
|
||||
ENV_LOON = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
|
||||
MBK_IN_LO=vst; export MBK_IN_LO; \
|
||||
MBK_OUT_LO=vst; export MBK_OUT_LO; \
|
||||
MBK_TARGET_LIB=$(TARGET_LIB); export MBK_TARGET_LIB; \
|
||||
MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
|
||||
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
|
||||
|
||||
ENV_ASIMUT_VASY = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
|
||||
MBK_CATAL_NAME=CATAL_ASIMUT_VASY; export MBK_CATAL_NAME;\
|
||||
MBK_IN_LO=vst; export MBK_IN_LO;\
|
||||
MBK_OUT_LO=vst; export MBK_OUT_LO
|
||||
|
||||
ENV_ASIMUT_SYNTH = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
|
||||
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME;\
|
||||
MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
|
||||
MBK_IN_LO=vst; export MBK_IN_LO;\
|
||||
MBK_OUT_LO=vst; export MBK_OUT_LO
|
||||
|
||||
ENV_OCP = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
|
||||
MBK_IN_LO=vst; export MBK_IN_LO; \
|
||||
MBK_OUT_LO=vst; export MBK_OUT_LO; \
|
||||
MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
|
||||
MBK_IN_PH=ap; export MBK_IN_PH; \
|
||||
MBK_OUT_PH=ap; export MBK_OUT_PH; \
|
||||
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
|
||||
|
||||
ENV_NERO = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
|
||||
MBK_IN_LO=vst; export MBK_IN_LO; \
|
||||
MBK_OUT_LO=vst; export MBK_OUT_LO; \
|
||||
MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
|
||||
MBK_IN_PH=ap; export MBK_IN_PH; \
|
||||
MBK_OUT_PH=ap; export MBK_OUT_PH; \
|
||||
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
|
||||
|
||||
|
||||
|
||||
ENV_COUGAR_SPI = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
|
||||
MBK_IN_LO=spi; export MBK_IN_LO; \
|
||||
MBK_OUT_LO=spi; export MBK_OUT_LO; \
|
||||
MBK_SPI_MODEL=$(SPI_MODEL); export MBK_SPI_MODEL; \
|
||||
MBK_SPI_ONE_NODE_NORC="true"; export MBK_SPI_ONE_NODE_NORC; \
|
||||
MBK_SPI_NAMEDNODES="true"; export MBK_SPI_NAMEDNODES; \
|
||||
RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME; \
|
||||
RDS_IN=cif; export RDS_IN; \
|
||||
RDS_OUT=cif; export RDS_OUT; \
|
||||
MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
|
||||
MBK_IN_PH=ap; export MBK_IN_PH; \
|
||||
MBK_OUT_PH=ap; export MBK_OUT_PH; \
|
||||
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
|
||||
|
||||
ENV_COUGAR = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
|
||||
MBK_IN_LO=al; export MBK_IN_LO; \
|
||||
MBK_OUT_LO=al; export MBK_OUT_LO; \
|
||||
RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME; \
|
||||
RDS_IN=cif; export RDS_IN; \
|
||||
RDS_OUT=cif; export RDS_OUT; \
|
||||
MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
|
||||
MBK_IN_PH=ap; export MBK_IN_PH; \
|
||||
MBK_OUT_PH=ap; export MBK_OUT_PH; \
|
||||
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
|
||||
|
||||
ENV_LVX = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
|
||||
MBK_IN_LO=vst; export MBK_IN_LO; \
|
||||
MBK_OUT_LO=vst; export MBK_OUT_LO; \
|
||||
MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
|
||||
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
|
||||
|
||||
ENV_DRUC = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
|
||||
RDS_TECHNO_NAME=$(RDS_TECHNO_SYMB); export RDS_TECHNO_NAME; \
|
||||
MBK_IN_PH=ap; export MBK_IN_PH; \
|
||||
MBK_OUT_PH=ap; export MBK_OUT_PH; \
|
||||
MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
|
||||
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
|
||||
|
||||
ENV_S2R = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
|
||||
RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME; \
|
||||
RDS_IN=cif; export RDS_IN; \
|
||||
RDS_OUT=cif; export RDS_OUT; \
|
||||
MBK_IN_PH=ap; export MBK_IN_PH; \
|
||||
MBK_OUT_PH=ap; export MBK_OUT_PH; \
|
||||
MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
|
||||
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
|
||||
|
||||
|
||||
all : multi8.cif
|
||||
|
||||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | Vasy |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
|
||||
multi8.vbe : multi8.vhdl
|
||||
$(ENV_VASY); $(VASY) -a -B -o -p -I vhdl multi8
|
||||
|
||||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | Asimut |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
|
||||
res_vasy_1.pat : multi8.vbe
|
||||
$(ENV_ASIMUT_VASY); $(ASIMUT) -b multi8 multi8 res_vasy_1
|
||||
|
||||
res_synth_1.pat : multi8.vst
|
||||
$(ENV_ASIMUT_SYNTH); $(ASIMUT) multi8 multi8 res_synth_1
|
||||
|
||||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | Boom |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
|
||||
boom.done : multi8_o.vbe
|
||||
@$(TOUCH) boom.done
|
||||
|
||||
multi8_o.vbe : multi8.vbe multi8.boom res_vasy_1.pat
|
||||
$(ENV_BOOM); $(BOOM) -VP multi8 multi8_o
|
||||
|
||||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | Boog |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
|
||||
boog.done : multi8_o.vst
|
||||
@$(TOUCH) boog.done
|
||||
|
||||
multi8_o.vst : multi8_o.vbe
|
||||
$(ENV_BOOG); $(BOOG) multi8_o
|
||||
|
||||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | Loon |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
|
||||
loon.done : multi8.vst
|
||||
@$(TOUCH) loon.done
|
||||
|
||||
multi8.vst : multi8_o.vst
|
||||
$(ENV_LOON); $(LOON) multi8_o multi8
|
||||
|
||||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | OCP |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
|
||||
multi8_p.ap : res_synth_1.pat
|
||||
$(ENV_OCP); $(OCP) -v -gnuplot -ioc multi8 multi8 multi8_p
|
||||
|
||||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | NERO |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
|
||||
multi8.ap : multi8_p.ap multi8.vst
|
||||
$(ENV_NERO); $(NERO) -v -$(METAL_LEVEL) -p multi8_p multi8 multi8
|
||||
|
||||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | Cougar |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
|
||||
multi8_e.spi : multi8.ap
|
||||
$(ENV_COUGAR_SPI); $(COUGAR) -v -ac multi8 multi8_e
|
||||
|
||||
multi8_erc.spi : multi8.ap
|
||||
$(ENV_COUGAR_SPI); $(COUGAR) -v -ar multi8 multi8_erc
|
||||
|
||||
multi8_erc.al : multi8.ap
|
||||
$(ENV_COUGAR); $(COUGAR) -v -ar multi8 multi8_erc
|
||||
|
||||
multi8_e.al : multi8.ap
|
||||
$(ENV_COUGAR); $(COUGAR) -v -ac multi8 multi8_e
|
||||
|
||||
multi8_et.al : multi8.ap
|
||||
$(ENV_COUGAR); $(COUGAR) -v -ac -t multi8 multi8_et
|
||||
|
||||
multi8_et.spi : multi8.ap
|
||||
$(ENV_COUGAR_SPI); $(COUGAR) -v -ac -t multi8 multi8_et
|
||||
|
||||
multi8_er.al : multi8.cif
|
||||
$(ENV_COUGAR); $(COUGAR) -v -r -t multi8 multi8_er
|
||||
|
||||
multi8_real.al : multi8.ap
|
||||
$(ENV_COUGAR); $(ENV_S2R); $(COUGAR) -v -ac multi8 multi8_real
|
||||
|
||||
multi8_real_t.al : multi8.ap
|
||||
$(ENV_COUGAR); $(ENV_S2R); $(COUGAR) -v -t -ac multi8 multi8_real_t
|
||||
|
||||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | Lvx |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
|
||||
lvx.done : multi8.vst multi8_e.al multi8_e.spi
|
||||
$(ENV_LVX); $(LVX) vst al multi8 multi8_e -f
|
||||
$(TOUCH) lvx.done
|
||||
|
||||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | Druc |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
|
||||
druc.done : lvx.done multi8.ap
|
||||
$(ENV_DRUC); $(DRUC) multi8
|
||||
$(TOUCH) druc.done
|
||||
|
||||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | S2R |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
|
||||
multi8.cif : druc.done
|
||||
$(ENV_S2R); $(S2R) -v multi8
|
||||
|
||||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | TOOLS |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
|
||||
graal :
|
||||
$(ENV_S2R); $(GRAAL)
|
||||
|
||||
graal_multi8_p : multi8_p.ap
|
||||
$(ENV_S2R); $(GRAAL) -l multi8_p
|
||||
|
||||
graal_multi8 : multi8.ap
|
||||
$(ENV_S2R); $(GRAAL) -l multi8
|
||||
|
||||
xsch:
|
||||
$(ENV_LOON); $(XSCH)
|
||||
|
||||
xsch_multi8_o : multi8.vst
|
||||
$(ENV_LOON); $(XSCH) -l multi8_o
|
||||
|
||||
xsch_multi8 : multi8.vst
|
||||
$(ENV_LOON); $(XSCH) -l multi8
|
||||
|
||||
xsch_multi8_e: multi8_e.al
|
||||
$(ENV_COUGAR); $(XSCH) -l multi8_e
|
||||
|
||||
xsch_multi8_et: multi8_et.al
|
||||
$(ENV_COUGAR); $(XSCH) -l multi8_et
|
||||
|
||||
xpat:
|
||||
$(ENV_ASIMUT_SYNTH); $(XPAT)
|
||||
|
||||
xpat_synth: res_synth_1.pat
|
||||
$(ENV_ASIMUT_SYNTH); $(XPAT) -l res_synth_1
|
||||
|
||||
xpat_vasy : res_vasy_1.pat
|
||||
$(ENV_ASIMUT_SYNTH); $(XPAT) -l res_vasy_1
|
||||
|
||||
dreal:
|
||||
$(ENV_S2R); $(DREAL)
|
||||
|
||||
dreal_multi8 : multi8.cif
|
||||
$(ENV_S2R); $(DREAL) -l multi8
|
||||
|
||||
|
||||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | Clean |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
|
||||
realclean : clean
|
||||
|
||||
clean :
|
||||
$(RM) -f *.vst multi8_e.spi multi8_et.spi *.vbe res_*.pat *.boom *.done *.xsc *.gpl \
|
||||
*.ap *.drc *.dat *.gds *.cif *.rep \
|
||||
*.log *.out *.raw *.al
|
||||
|
|
@ -0,0 +1,118 @@
|
|||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | File : README |
|
||||
# | |
|
||||
# | Author : Jacomme Ludovic |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
|
||||
This directory contains the VHDL description of combinatorial 8 bits
|
||||
multiplier and the associated stimuli file, and also a configuration file for IO
|
||||
placement (used during the Place and Route step).
|
||||
|
||||
The Makefile set environement variables properly and run Alliance tools,
|
||||
following each step of the design flow from VHDL up to real layout in a
|
||||
pseudo 0.35 techno.
|
||||
|
||||
The environement variable ALLIANCE_TOP as to be set.
|
||||
|
||||
The main targets of the makefile are listed below (following the design flow).
|
||||
|
||||
#
|
||||
# RTL SYNTHESIS
|
||||
#
|
||||
|
||||
multi8.vbe : Run the VHDL analyzer (VASY) on the VHDL description
|
||||
(multi8.vhdl) and transform it into a boolean network (multi8.vbe).
|
||||
|
||||
res_vasy_1.pat : Run the VHDL simulator (ASIMUT) on multi8.vbe using the pattern/stimuli file
|
||||
multi8.pat. This step checks if the multi8.vbe description is working properly.
|
||||
|
||||
xpat_vasy : Run the graphical waveform viewer (XPAT) on the resulting file res_vasy_1.pat
|
||||
|
||||
multi8_o.vbe : Run the Boolean network optimizer (BOOM) on the multi8.vbe and
|
||||
factorize/minimize boolean equations, and generate a new description
|
||||
multi8_o.vbe.
|
||||
|
||||
multi8_o.vst : Run the boolean mapper (BOOG) on the optimized description multi8_o.vbe
|
||||
and using the sxlib standard cell library, map all boolean nodes to
|
||||
an equivalent set of standard cells.
|
||||
|
||||
xsch_multi8_o : Run the schematic viewer (XSCH) on the structural netlist multi8_o.vst
|
||||
|
||||
|
||||
multi8.vst : Run the net optimizer (LOON) on the structural description multi8_o.vst.
|
||||
It inserts buffers on the critical path using the sxlib standard cell library
|
||||
and generates a new structural netlist multi8.vst .
|
||||
|
||||
xsch_multi8 : Run the schematic viewer (XSCH) on the bufferized netlist multi8.vst .
|
||||
The critical path would be displayed in red color.
|
||||
|
||||
res_synth_1.pat : Run the VHDL simulator (ASIMUT) on the structural description multi8.vst using
|
||||
the pattern/stimuli file multi8.pat and the behavioral description (.VBE) of each
|
||||
cells of the standard cell library (sxlib).
|
||||
This step checks if the multi8.vst description is still working properly.
|
||||
|
||||
#
|
||||
# PLACE AND ROUTE
|
||||
#
|
||||
|
||||
multi8_p.ap : Run the placement tool (OCP) on the structural description multi8.vst.
|
||||
It generates a physical placement file (multi8_p.ap) that would be given
|
||||
to the router (NERO).
|
||||
|
||||
graal_multi8_p : Launch the physical layout editor (GRAAL) and display the result of the placement tool
|
||||
(multi8_p.ap).
|
||||
|
||||
multi8.ap : Run the router tool (NERO). Given the structural description multi8.vst, the
|
||||
placement file (multi8_p) and the position of external connectors (multi8.ioc)
|
||||
the router generates a physical view (multi8.ap) where all nets have been routed.
|
||||
|
||||
graal_multi8 : Launch the physical layout editor (GRAAL) and display the result of the router tool
|
||||
(multi8.ap).
|
||||
|
||||
#
|
||||
# Netlist / parasitics extraction
|
||||
#
|
||||
|
||||
multi8_e.al : Run the hierarchical netlist extractor (COUGAR) and extracts the netlist with parasitic
|
||||
informations (physical parameters are taken in the techno-035.rds file).
|
||||
This tool generates the extracted netlist multi8_e.al
|
||||
|
||||
xsch_multi8_e : Run the schematic viewer (XSCH) on the hierarchical extracted netlist (multi8_e.al).
|
||||
|
||||
multi8_et.al : Run the netlist extractor (COUGAR) and extracts the netlist at the transistor level
|
||||
with parasitics informations (multi8_et.al).
|
||||
|
||||
xsch_multi8_et : Run the schematic viewer (XSCH) on the extracted transistor netlist (multi8_et.al).
|
||||
|
||||
#
|
||||
# Netlists comparison
|
||||
#
|
||||
|
||||
lvx.done : Run the gate netlist comparator (LVX) and checks if the extracted netlist is the same as
|
||||
the structural structural netlist. This step checks if the place and route phases are ok.
|
||||
|
||||
#
|
||||
# Design rule checker
|
||||
#
|
||||
|
||||
druc.done : Launch the design rule checker on the layout generated by the router (multi8.ap). The design
|
||||
rules are specified in the RDS file (techno-symb.rds).
|
||||
|
||||
|
||||
#
|
||||
# Symbolic layout to real layout
|
||||
#
|
||||
|
||||
multi8.cif : Transforms the symbolic layout in lambda (multi8.ap) in a 0.35u real layout using the tool S2R.
|
||||
It generates a CIF file (multi8.cif).
|
||||
|
||||
dreal_multi8 : Launch the real layout editor (DREAL) and display the result of S2R
|
||||
(multi8.cif).
|
||||
|
||||
|
||||
#
|
||||
# Clean
|
||||
|
||||
The clean target remove all generated files ...
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
|
||||
TOP ( # IOs are ordered from left to right
|
||||
(IOPIN x(7).0 );
|
||||
(IOPIN x(6).0 );
|
||||
(IOPIN x(5).0 );
|
||||
(IOPIN x(4).0 );
|
||||
(IOPIN x(3).0 );
|
||||
(IOPIN x(2).0 );
|
||||
(IOPIN x(1).0 );
|
||||
(IOPIN x(0).0 );
|
||||
(IOPIN y(7).0 );
|
||||
(IOPIN y(6).0 );
|
||||
(IOPIN y(5).0 );
|
||||
(IOPIN y(4).0 );
|
||||
(IOPIN y(3).0 );
|
||||
(IOPIN y(2).0 );
|
||||
(IOPIN y(1).0 );
|
||||
(IOPIN y(0).0 );
|
||||
)
|
||||
BOTTOM ( # IOs are ordered from left to right
|
||||
(IOPIN r(15).0 );
|
||||
(IOPIN r(14).0 );
|
||||
(IOPIN r(13).0 );
|
||||
(IOPIN r(12).0 );
|
||||
(IOPIN r(11).0 );
|
||||
(IOPIN r(10).0 );
|
||||
(IOPIN r(9).0 );
|
||||
(IOPIN r(8).0 );
|
||||
(IOPIN r(7).0 );
|
||||
(IOPIN r(6).0 );
|
||||
(IOPIN r(5).0 );
|
||||
(IOPIN r(4).0 );
|
||||
(IOPIN r(3).0 );
|
||||
(IOPIN r(2).0 );
|
||||
(IOPIN r(1).0 );
|
||||
(IOPIN r(0).0 );
|
||||
)
|
||||
IGNORE ( # IOs are ignored(not placed) by IO Placer
|
||||
)
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
##
|
||||
## Generated by VASY
|
||||
##
|
||||
#S{
|
||||
rtlcarry_12_9;
|
||||
rtlcarry_12_8;
|
||||
rtlcarry_12_7;
|
||||
rtlcarry_12_6;
|
||||
rtlcarry_12_5;
|
||||
rtlcarry_12_4;
|
||||
rtlcarry_12_3;
|
||||
rtlcarry_12_2;
|
||||
rtlcarry_12_1;
|
||||
rtlcarry_11_9;
|
||||
rtlcarry_11_8;
|
||||
rtlcarry_11_7;
|
||||
rtlcarry_11_6;
|
||||
rtlcarry_11_5;
|
||||
rtlcarry_11_4;
|
||||
rtlcarry_11_3;
|
||||
rtlcarry_11_2;
|
||||
rtlcarry_11_1;
|
||||
rtlcarry_10_9;
|
||||
rtlcarry_10_8;
|
||||
rtlcarry_10_7;
|
||||
rtlcarry_10_6;
|
||||
rtlcarry_10_5;
|
||||
rtlcarry_10_4;
|
||||
rtlcarry_10_3;
|
||||
rtlcarry_10_2;
|
||||
rtlcarry_10_1;
|
||||
rtlcarry_9_9;
|
||||
rtlcarry_9_8;
|
||||
rtlcarry_9_7;
|
||||
rtlcarry_9_6;
|
||||
rtlcarry_9_5;
|
||||
rtlcarry_9_4;
|
||||
rtlcarry_9_3;
|
||||
rtlcarry_9_2;
|
||||
rtlcarry_9_1;
|
||||
rtlcarry_6_11;
|
||||
rtlcarry_6_10;
|
||||
rtlcarry_6_9;
|
||||
rtlcarry_6_8;
|
||||
rtlcarry_6_7;
|
||||
rtlcarry_6_6;
|
||||
rtlcarry_6_5;
|
||||
rtlcarry_6_4;
|
||||
rtlcarry_6_3;
|
||||
rtlcarry_6_2;
|
||||
rtlcarry_6_1;
|
||||
rtlcarry_3_11;
|
||||
rtlcarry_3_10;
|
||||
rtlcarry_3_9;
|
||||
rtlcarry_3_8;
|
||||
rtlcarry_3_7;
|
||||
rtlcarry_3_6;
|
||||
rtlcarry_3_5;
|
||||
rtlcarry_3_4;
|
||||
rtlcarry_3_3;
|
||||
rtlcarry_3_2;
|
||||
rtlcarry_3_1;
|
||||
rtlcarry_0_15;
|
||||
rtlcarry_0_14;
|
||||
rtlcarry_0_13;
|
||||
rtlcarry_0_12;
|
||||
rtlcarry_0_11;
|
||||
rtlcarry_0_10;
|
||||
rtlcarry_0_9;
|
||||
rtlcarry_0_8;
|
||||
rtlcarry_0_7;
|
||||
rtlcarry_0_6;
|
||||
rtlcarry_0_5;
|
||||
rtlcarry_0_4;
|
||||
rtlcarry_0_3;
|
||||
rtlcarry_0_2;
|
||||
rtlcarry_0_1;
|
||||
}
|
||||
|
|
@ -0,0 +1,470 @@
|
|||
|
||||
in x (7 downto 0) X;;;
|
||||
in y (7 downto 0) X;;;
|
||||
out r (15 downto 0) X;;;
|
||||
in vss B;;
|
||||
in vdd B;;
|
||||
|
||||
begin
|
||||
|
||||
-- Pattern description :
|
||||
-- A B Res V V
|
||||
|
||||
< +10ns>: f0 00 ?**** 0 1;
|
||||
< +10ns>: f0 00 ?**** 0 1;
|
||||
< +10ns>: f0 01 ?**** 0 1;
|
||||
< +10ns>: f0 01 ?**** 0 1;
|
||||
< +10ns>: f1 00 ?**** 0 1;
|
||||
< +10ns>: f1 00 ?**** 0 1;
|
||||
< +10ns>: f1 01 ?**** 0 1;
|
||||
< +10ns>: f1 01 ?**** 0 1;
|
||||
< +10ns>: f1 02 ?**** 0 1;
|
||||
< +10ns>: f1 02 ?**** 0 1;
|
||||
< +10ns>: f1 03 ?**** 0 1;
|
||||
< +10ns>: f1 03 ?**** 0 1;
|
||||
< +10ns>: f1 04 ?**** 0 1;
|
||||
< +10ns>: f1 04 ?**** 0 1;
|
||||
< +10ns>: f1 05 ?**** 0 1;
|
||||
< +10ns>: f1 05 ?**** 0 1;
|
||||
< +10ns>: f1 06 ?**** 0 1;
|
||||
< +10ns>: f1 06 ?**** 0 1;
|
||||
< +10ns>: f1 07 ?**** 0 1;
|
||||
< +10ns>: f1 07 ?**** 0 1;
|
||||
< +10ns>: f1 08 ?**** 0 1;
|
||||
< +10ns>: f1 08 ?**** 0 1;
|
||||
< +10ns>: f1 09 ?**** 0 1;
|
||||
< +10ns>: f1 09 ?**** 0 1;
|
||||
< +10ns>: f1 0a ?**** 0 1;
|
||||
< +10ns>: f1 0a ?**** 0 1;
|
||||
< +10ns>: f1 0b ?**** 0 1;
|
||||
< +10ns>: f1 0b ?**** 0 1;
|
||||
< +10ns>: f1 0c ?**** 0 1;
|
||||
< +10ns>: f1 0c ?**** 0 1;
|
||||
< +10ns>: f1 0d ?**** 0 1;
|
||||
< +10ns>: f1 0d ?**** 0 1;
|
||||
< +10ns>: f1 0e ?**** 0 1;
|
||||
< +10ns>: f1 0e ?**** 0 1;
|
||||
< +10ns>: f1 0f ?**** 0 1;
|
||||
< +10ns>: f1 0f ?**** 0 1;
|
||||
< +10ns>: f2 01 ?**** 0 1;
|
||||
< +10ns>: f2 01 ?**** 0 1;
|
||||
< +10ns>: f2 02 ?**** 0 1;
|
||||
< +10ns>: f2 02 ?**** 0 1;
|
||||
< +10ns>: f2 03 ?**** 0 1;
|
||||
< +10ns>: f2 03 ?**** 0 1;
|
||||
< +10ns>: f2 04 ?**** 0 1;
|
||||
< +10ns>: f2 04 ?**** 0 1;
|
||||
< +10ns>: f2 05 ?**** 0 1;
|
||||
< +10ns>: f2 05 ?**** 0 1;
|
||||
< +10ns>: f2 06 ?**** 0 1;
|
||||
< +10ns>: f2 06 ?**** 0 1;
|
||||
< +10ns>: f2 07 ?**** 0 1;
|
||||
< +10ns>: f2 07 ?**** 0 1;
|
||||
< +10ns>: f2 08 ?**** 0 1;
|
||||
< +10ns>: f2 08 ?**** 0 1;
|
||||
< +10ns>: f2 09 ?**** 0 1;
|
||||
< +10ns>: f2 09 ?**** 0 1;
|
||||
< +10ns>: f2 0a ?**** 0 1;
|
||||
< +10ns>: f2 0a ?**** 0 1;
|
||||
< +10ns>: f2 0b ?**** 0 1;
|
||||
< +10ns>: f2 0b ?**** 0 1;
|
||||
< +10ns>: f2 0c ?**** 0 1;
|
||||
< +10ns>: f2 0c ?**** 0 1;
|
||||
< +10ns>: f2 0d ?**** 0 1;
|
||||
< +10ns>: f2 0d ?**** 0 1;
|
||||
< +10ns>: f2 0e ?**** 0 1;
|
||||
< +10ns>: f2 0e ?**** 0 1;
|
||||
< +10ns>: f2 0f ?**** 0 1;
|
||||
< +10ns>: f2 0f ?**** 0 1;
|
||||
< +10ns>: f3 01 ?**** 0 1;
|
||||
< +10ns>: f3 01 ?**** 0 1;
|
||||
< +10ns>: f3 02 ?**** 0 1;
|
||||
< +10ns>: f3 02 ?**** 0 1;
|
||||
< +10ns>: f3 03 ?**** 0 1;
|
||||
< +10ns>: f3 03 ?**** 0 1;
|
||||
< +10ns>: f3 04 ?**** 0 1;
|
||||
< +10ns>: f3 04 ?**** 0 1;
|
||||
< +10ns>: f3 05 ?**** 0 1;
|
||||
< +10ns>: f3 05 ?**** 0 1;
|
||||
< +10ns>: f3 06 ?**** 0 1;
|
||||
< +10ns>: f3 06 ?**** 0 1;
|
||||
< +10ns>: f3 07 ?**** 0 1;
|
||||
< +10ns>: f3 07 ?**** 0 1;
|
||||
< +10ns>: f3 08 ?**** 0 1;
|
||||
< +10ns>: f3 08 ?**** 0 1;
|
||||
< +10ns>: f3 09 ?**** 0 1;
|
||||
< +10ns>: f3 09 ?**** 0 1;
|
||||
< +10ns>: f3 0a ?**** 0 1;
|
||||
< +10ns>: f3 0a ?**** 0 1;
|
||||
< +10ns>: f3 0b ?**** 0 1;
|
||||
< +10ns>: f3 0b ?**** 0 1;
|
||||
< +10ns>: f3 0c ?**** 0 1;
|
||||
< +10ns>: f3 0c ?**** 0 1;
|
||||
< +10ns>: f3 0d ?**** 0 1;
|
||||
< +10ns>: f3 0d ?**** 0 1;
|
||||
< +10ns>: f3 0e ?**** 0 1;
|
||||
< +10ns>: f3 0e ?**** 0 1;
|
||||
< +10ns>: f3 0f ?**** 0 1;
|
||||
< +10ns>: f3 0f ?**** 0 1;
|
||||
< +10ns>: f4 01 ?**** 0 1;
|
||||
< +10ns>: f4 01 ?**** 0 1;
|
||||
< +10ns>: f4 02 ?**** 0 1;
|
||||
< +10ns>: f4 02 ?**** 0 1;
|
||||
< +10ns>: f4 03 ?**** 0 1;
|
||||
< +10ns>: f4 03 ?**** 0 1;
|
||||
< +10ns>: f4 04 ?**** 0 1;
|
||||
< +10ns>: f4 04 ?**** 0 1;
|
||||
< +10ns>: f4 05 ?**** 0 1;
|
||||
< +10ns>: f4 05 ?**** 0 1;
|
||||
< +10ns>: f4 06 ?**** 0 1;
|
||||
< +10ns>: f4 06 ?**** 0 1;
|
||||
< +10ns>: f4 07 ?**** 0 1;
|
||||
< +10ns>: f4 07 ?**** 0 1;
|
||||
< +10ns>: f4 08 ?**** 0 1;
|
||||
< +10ns>: f4 08 ?**** 0 1;
|
||||
< +10ns>: f4 09 ?**** 0 1;
|
||||
< +10ns>: f4 09 ?**** 0 1;
|
||||
< +10ns>: f4 0a ?**** 0 1;
|
||||
< +10ns>: f4 0a ?**** 0 1;
|
||||
< +10ns>: f4 0b ?**** 0 1;
|
||||
< +10ns>: f4 0b ?**** 0 1;
|
||||
< +10ns>: f4 0c ?**** 0 1;
|
||||
< +10ns>: f4 0c ?**** 0 1;
|
||||
< +10ns>: f4 0d ?**** 0 1;
|
||||
< +10ns>: f4 0d ?**** 0 1;
|
||||
< +10ns>: f4 0e ?**** 0 1;
|
||||
< +10ns>: f4 0e ?**** 0 1;
|
||||
< +10ns>: f4 0f ?**** 0 1;
|
||||
< +10ns>: f4 0f ?**** 0 1;
|
||||
< +10ns>: f5 01 ?**** 0 1;
|
||||
< +10ns>: f5 01 ?**** 0 1;
|
||||
< +10ns>: f5 02 ?**** 0 1;
|
||||
< +10ns>: f5 02 ?**** 0 1;
|
||||
< +10ns>: f5 03 ?**** 0 1;
|
||||
< +10ns>: f5 03 ?**** 0 1;
|
||||
< +10ns>: f5 04 ?**** 0 1;
|
||||
< +10ns>: f5 04 ?**** 0 1;
|
||||
< +10ns>: f5 05 ?**** 0 1;
|
||||
< +10ns>: f5 05 ?**** 0 1;
|
||||
< +10ns>: f5 06 ?**** 0 1;
|
||||
< +10ns>: f5 06 ?**** 0 1;
|
||||
< +10ns>: f5 07 ?**** 0 1;
|
||||
< +10ns>: f5 07 ?**** 0 1;
|
||||
< +10ns>: f5 08 ?**** 0 1;
|
||||
< +10ns>: f5 08 ?**** 0 1;
|
||||
< +10ns>: f5 09 ?**** 0 1;
|
||||
< +10ns>: f5 09 ?**** 0 1;
|
||||
< +10ns>: f5 0a ?**** 0 1;
|
||||
< +10ns>: f5 0a ?**** 0 1;
|
||||
< +10ns>: f5 0b ?**** 0 1;
|
||||
< +10ns>: f5 0b ?**** 0 1;
|
||||
< +10ns>: f5 0c ?**** 0 1;
|
||||
< +10ns>: f5 0c ?**** 0 1;
|
||||
< +10ns>: f5 0d ?**** 0 1;
|
||||
< +10ns>: f5 0d ?**** 0 1;
|
||||
< +10ns>: f5 0e ?**** 0 1;
|
||||
< +10ns>: f5 0e ?**** 0 1;
|
||||
< +10ns>: f5 0f ?**** 0 1;
|
||||
< +10ns>: f5 0f ?**** 0 1;
|
||||
< +10ns>: f6 01 ?**** 0 1;
|
||||
< +10ns>: f6 01 ?**** 0 1;
|
||||
< +10ns>: f6 02 ?**** 0 1;
|
||||
< +10ns>: f6 02 ?**** 0 1;
|
||||
< +10ns>: f6 03 ?**** 0 1;
|
||||
< +10ns>: f6 03 ?**** 0 1;
|
||||
< +10ns>: f6 04 ?**** 0 1;
|
||||
< +10ns>: f6 04 ?**** 0 1;
|
||||
< +10ns>: f6 05 ?**** 0 1;
|
||||
< +10ns>: f6 05 ?**** 0 1;
|
||||
< +10ns>: f6 06 ?**** 0 1;
|
||||
< +10ns>: f6 06 ?**** 0 1;
|
||||
< +10ns>: f6 07 ?**** 0 1;
|
||||
< +10ns>: f6 07 ?**** 0 1;
|
||||
< +10ns>: f6 08 ?**** 0 1;
|
||||
< +10ns>: f6 08 ?**** 0 1;
|
||||
< +10ns>: f6 09 ?**** 0 1;
|
||||
< +10ns>: f6 09 ?**** 0 1;
|
||||
< +10ns>: f6 0a ?**** 0 1;
|
||||
< +10ns>: f6 0a ?**** 0 1;
|
||||
< +10ns>: f6 0b ?**** 0 1;
|
||||
< +10ns>: f6 0b ?**** 0 1;
|
||||
< +10ns>: f6 0c ?**** 0 1;
|
||||
< +10ns>: f6 0c ?**** 0 1;
|
||||
< +10ns>: f6 0d ?**** 0 1;
|
||||
< +10ns>: f6 0d ?**** 0 1;
|
||||
< +10ns>: f6 0e ?**** 0 1;
|
||||
< +10ns>: f6 0e ?**** 0 1;
|
||||
< +10ns>: f6 0f ?**** 0 1;
|
||||
< +10ns>: f6 0f ?**** 0 1;
|
||||
< +10ns>: f7 01 ?**** 0 1;
|
||||
< +10ns>: f7 01 ?**** 0 1;
|
||||
< +10ns>: f7 02 ?**** 0 1;
|
||||
< +10ns>: f7 02 ?**** 0 1;
|
||||
< +10ns>: f7 03 ?**** 0 1;
|
||||
< +10ns>: f7 03 ?**** 0 1;
|
||||
< +10ns>: f7 04 ?**** 0 1;
|
||||
< +10ns>: f7 04 ?**** 0 1;
|
||||
< +10ns>: f7 05 ?**** 0 1;
|
||||
< +10ns>: f7 05 ?**** 0 1;
|
||||
< +10ns>: f7 06 ?**** 0 1;
|
||||
< +10ns>: f7 06 ?**** 0 1;
|
||||
< +10ns>: f7 07 ?**** 0 1;
|
||||
< +10ns>: f7 07 ?**** 0 1;
|
||||
< +10ns>: f7 08 ?**** 0 1;
|
||||
< +10ns>: f7 08 ?**** 0 1;
|
||||
< +10ns>: f7 09 ?**** 0 1;
|
||||
< +10ns>: f7 09 ?**** 0 1;
|
||||
< +10ns>: f7 0a ?**** 0 1;
|
||||
< +10ns>: f7 0a ?**** 0 1;
|
||||
< +10ns>: f7 0b ?**** 0 1;
|
||||
< +10ns>: f7 0b ?**** 0 1;
|
||||
< +10ns>: f7 0c ?**** 0 1;
|
||||
< +10ns>: f7 0c ?**** 0 1;
|
||||
< +10ns>: f7 0d ?**** 0 1;
|
||||
< +10ns>: f7 0d ?**** 0 1;
|
||||
< +10ns>: f7 0e ?**** 0 1;
|
||||
< +10ns>: f7 0e ?**** 0 1;
|
||||
< +10ns>: f7 0f ?**** 0 1;
|
||||
< +10ns>: f7 0f ?**** 0 1;
|
||||
< +10ns>: f8 01 ?**** 0 1;
|
||||
< +10ns>: f8 01 ?**** 0 1;
|
||||
< +10ns>: f8 02 ?**** 0 1;
|
||||
< +10ns>: f8 02 ?**** 0 1;
|
||||
< +10ns>: f8 03 ?**** 0 1;
|
||||
< +10ns>: f8 03 ?**** 0 1;
|
||||
< +10ns>: f8 04 ?**** 0 1;
|
||||
< +10ns>: f8 04 ?**** 0 1;
|
||||
< +10ns>: f8 05 ?**** 0 1;
|
||||
< +10ns>: f8 05 ?**** 0 1;
|
||||
< +10ns>: f8 06 ?**** 0 1;
|
||||
< +10ns>: f8 06 ?**** 0 1;
|
||||
< +10ns>: f8 07 ?**** 0 1;
|
||||
< +10ns>: f8 07 ?**** 0 1;
|
||||
< +10ns>: f8 08 ?**** 0 1;
|
||||
< +10ns>: f8 08 ?**** 0 1;
|
||||
< +10ns>: f8 09 ?**** 0 1;
|
||||
< +10ns>: f8 09 ?**** 0 1;
|
||||
< +10ns>: f8 0a ?**** 0 1;
|
||||
< +10ns>: f8 0a ?**** 0 1;
|
||||
< +10ns>: f8 0b ?**** 0 1;
|
||||
< +10ns>: f8 0b ?**** 0 1;
|
||||
< +10ns>: f8 0c ?**** 0 1;
|
||||
< +10ns>: f8 0c ?**** 0 1;
|
||||
< +10ns>: f8 0d ?**** 0 1;
|
||||
< +10ns>: f8 0d ?**** 0 1;
|
||||
< +10ns>: f8 0e ?**** 0 1;
|
||||
< +10ns>: f8 0e ?**** 0 1;
|
||||
< +10ns>: f8 0f ?**** 0 1;
|
||||
< +10ns>: f8 0f ?**** 0 1;
|
||||
< +10ns>: f9 01 ?**** 0 1;
|
||||
< +10ns>: f9 01 ?**** 0 1;
|
||||
< +10ns>: f9 02 ?**** 0 1;
|
||||
< +10ns>: f9 02 ?**** 0 1;
|
||||
< +10ns>: f9 03 ?**** 0 1;
|
||||
< +10ns>: f9 03 ?**** 0 1;
|
||||
< +10ns>: f9 04 ?**** 0 1;
|
||||
< +10ns>: f9 04 ?**** 0 1;
|
||||
< +10ns>: f9 05 ?**** 0 1;
|
||||
< +10ns>: f9 05 ?**** 0 1;
|
||||
< +10ns>: f9 06 ?**** 0 1;
|
||||
< +10ns>: f9 06 ?**** 0 1;
|
||||
< +10ns>: f9 07 ?**** 0 1;
|
||||
< +10ns>: f9 07 ?**** 0 1;
|
||||
< +10ns>: f9 08 ?**** 0 1;
|
||||
< +10ns>: f9 08 ?**** 0 1;
|
||||
< +10ns>: f9 09 ?**** 0 1;
|
||||
< +10ns>: f9 09 ?**** 0 1;
|
||||
< +10ns>: f9 0a ?**** 0 1;
|
||||
< +10ns>: f9 0a ?**** 0 1;
|
||||
< +10ns>: f9 0b ?**** 0 1;
|
||||
< +10ns>: f9 0b ?**** 0 1;
|
||||
< +10ns>: f9 0c ?**** 0 1;
|
||||
< +10ns>: f9 0c ?**** 0 1;
|
||||
< +10ns>: f9 0d ?**** 0 1;
|
||||
< +10ns>: f9 0d ?**** 0 1;
|
||||
< +10ns>: f9 0e ?**** 0 1;
|
||||
< +10ns>: f9 0e ?**** 0 1;
|
||||
< +10ns>: f9 0f ?**** 0 1;
|
||||
< +10ns>: f9 0f ?**** 0 1;
|
||||
< +10ns>: fa 01 ?**** 0 1;
|
||||
< +10ns>: fa 01 ?**** 0 1;
|
||||
< +10ns>: fa 02 ?**** 0 1;
|
||||
< +10ns>: fa 02 ?**** 0 1;
|
||||
< +10ns>: fa 03 ?**** 0 1;
|
||||
< +10ns>: fa 03 ?**** 0 1;
|
||||
< +10ns>: fa 04 ?**** 0 1;
|
||||
< +10ns>: fa 04 ?**** 0 1;
|
||||
< +10ns>: fa 05 ?**** 0 1;
|
||||
< +10ns>: fa 05 ?**** 0 1;
|
||||
< +10ns>: fa 06 ?**** 0 1;
|
||||
< +10ns>: fa 06 ?**** 0 1;
|
||||
< +10ns>: fa 07 ?**** 0 1;
|
||||
< +10ns>: fa 07 ?**** 0 1;
|
||||
< +10ns>: fa 08 ?**** 0 1;
|
||||
< +10ns>: fa 08 ?**** 0 1;
|
||||
< +10ns>: fa 09 ?**** 0 1;
|
||||
< +10ns>: fa 09 ?**** 0 1;
|
||||
< +10ns>: fa 0a ?**** 0 1;
|
||||
< +10ns>: fa 0a ?**** 0 1;
|
||||
< +10ns>: fa 0b ?**** 0 1;
|
||||
< +10ns>: fa 0b ?**** 0 1;
|
||||
< +10ns>: fa 0c ?**** 0 1;
|
||||
< +10ns>: fa 0c ?**** 0 1;
|
||||
< +10ns>: fa 0d ?**** 0 1;
|
||||
< +10ns>: fa 0d ?**** 0 1;
|
||||
< +10ns>: fa 0e ?**** 0 1;
|
||||
< +10ns>: fa 0e ?**** 0 1;
|
||||
< +10ns>: fa 0f ?**** 0 1;
|
||||
< +10ns>: fa 0f ?**** 0 1;
|
||||
< +10ns>: fb 01 ?**** 0 1;
|
||||
< +10ns>: fb 01 ?**** 0 1;
|
||||
< +10ns>: fb 02 ?**** 0 1;
|
||||
< +10ns>: fb 02 ?**** 0 1;
|
||||
< +10ns>: fb 03 ?**** 0 1;
|
||||
< +10ns>: fb 03 ?**** 0 1;
|
||||
< +10ns>: fb 04 ?**** 0 1;
|
||||
< +10ns>: fb 04 ?**** 0 1;
|
||||
< +10ns>: fb 05 ?**** 0 1;
|
||||
< +10ns>: fb 05 ?**** 0 1;
|
||||
< +10ns>: fb 06 ?**** 0 1;
|
||||
< +10ns>: fb 06 ?**** 0 1;
|
||||
< +10ns>: fb 07 ?**** 0 1;
|
||||
< +10ns>: fb 07 ?**** 0 1;
|
||||
< +10ns>: fb 08 ?**** 0 1;
|
||||
< +10ns>: fb 08 ?**** 0 1;
|
||||
< +10ns>: fb 09 ?**** 0 1;
|
||||
< +10ns>: fb 09 ?**** 0 1;
|
||||
< +10ns>: fb 0a ?**** 0 1;
|
||||
< +10ns>: fb 0a ?**** 0 1;
|
||||
< +10ns>: fb 0b ?**** 0 1;
|
||||
< +10ns>: fb 0b ?**** 0 1;
|
||||
< +10ns>: fb 0c ?**** 0 1;
|
||||
< +10ns>: fb 0c ?**** 0 1;
|
||||
< +10ns>: fb 0d ?**** 0 1;
|
||||
< +10ns>: fb 0d ?**** 0 1;
|
||||
< +10ns>: fb 0e ?**** 0 1;
|
||||
< +10ns>: fb 0e ?**** 0 1;
|
||||
< +10ns>: fb 0f ?**** 0 1;
|
||||
< +10ns>: fb 0f ?**** 0 1;
|
||||
< +10ns>: fc 01 ?**** 0 1;
|
||||
< +10ns>: fc 01 ?**** 0 1;
|
||||
< +10ns>: fc 02 ?**** 0 1;
|
||||
< +10ns>: fc 02 ?**** 0 1;
|
||||
< +10ns>: fc 03 ?**** 0 1;
|
||||
< +10ns>: fc 03 ?**** 0 1;
|
||||
< +10ns>: fc 04 ?**** 0 1;
|
||||
< +10ns>: fc 04 ?**** 0 1;
|
||||
< +10ns>: fc 05 ?**** 0 1;
|
||||
< +10ns>: fc 05 ?**** 0 1;
|
||||
< +10ns>: fc 06 ?**** 0 1;
|
||||
< +10ns>: fc 06 ?**** 0 1;
|
||||
< +10ns>: fc 07 ?**** 0 1;
|
||||
< +10ns>: fc 07 ?**** 0 1;
|
||||
< +10ns>: fc 08 ?**** 0 1;
|
||||
< +10ns>: fc 08 ?**** 0 1;
|
||||
< +10ns>: fc 09 ?**** 0 1;
|
||||
< +10ns>: fc 09 ?**** 0 1;
|
||||
< +10ns>: fc 0a ?**** 0 1;
|
||||
< +10ns>: fc 0a ?**** 0 1;
|
||||
< +10ns>: fc 0b ?**** 0 1;
|
||||
< +10ns>: fc 0b ?**** 0 1;
|
||||
< +10ns>: fc 0c ?**** 0 1;
|
||||
< +10ns>: fc 0c ?**** 0 1;
|
||||
< +10ns>: fc 0d ?**** 0 1;
|
||||
< +10ns>: fc 0d ?**** 0 1;
|
||||
< +10ns>: fc 0e ?**** 0 1;
|
||||
< +10ns>: fc 0e ?**** 0 1;
|
||||
< +10ns>: fc 0f ?**** 0 1;
|
||||
< +10ns>: fc 0f ?**** 0 1;
|
||||
< +10ns>: fd 01 ?**** 0 1;
|
||||
< +10ns>: fd 01 ?**** 0 1;
|
||||
< +10ns>: fd 02 ?**** 0 1;
|
||||
< +10ns>: fd 02 ?**** 0 1;
|
||||
< +10ns>: fd 03 ?**** 0 1;
|
||||
< +10ns>: fd 03 ?**** 0 1;
|
||||
< +10ns>: fd 04 ?**** 0 1;
|
||||
< +10ns>: fd 04 ?**** 0 1;
|
||||
< +10ns>: fd 05 ?**** 0 1;
|
||||
< +10ns>: fd 05 ?**** 0 1;
|
||||
< +10ns>: fd 06 ?**** 0 1;
|
||||
< +10ns>: fd 06 ?**** 0 1;
|
||||
< +10ns>: fd 07 ?**** 0 1;
|
||||
< +10ns>: fd 07 ?**** 0 1;
|
||||
< +10ns>: fd 08 ?**** 0 1;
|
||||
< +10ns>: fd 08 ?**** 0 1;
|
||||
< +10ns>: fd 09 ?**** 0 1;
|
||||
< +10ns>: fd 09 ?**** 0 1;
|
||||
< +10ns>: fd 0a ?**** 0 1;
|
||||
< +10ns>: fd 0a ?**** 0 1;
|
||||
< +10ns>: fd 0b ?**** 0 1;
|
||||
< +10ns>: fd 0b ?**** 0 1;
|
||||
< +10ns>: fd 0c ?**** 0 1;
|
||||
< +10ns>: fd 0c ?**** 0 1;
|
||||
< +10ns>: fd 0d ?**** 0 1;
|
||||
< +10ns>: fd 0d ?**** 0 1;
|
||||
< +10ns>: fd 0e ?**** 0 1;
|
||||
< +10ns>: fd 0e ?**** 0 1;
|
||||
< +10ns>: fd 0f ?**** 0 1;
|
||||
< +10ns>: fd 0f ?**** 0 1;
|
||||
< +10ns>: fe 01 ?**** 0 1;
|
||||
< +10ns>: fe 01 ?**** 0 1;
|
||||
< +10ns>: fe 02 ?**** 0 1;
|
||||
< +10ns>: fe 02 ?**** 0 1;
|
||||
< +10ns>: fe 03 ?**** 0 1;
|
||||
< +10ns>: fe 03 ?**** 0 1;
|
||||
< +10ns>: fe 04 ?**** 0 1;
|
||||
< +10ns>: fe 04 ?**** 0 1;
|
||||
< +10ns>: fe 05 ?**** 0 1;
|
||||
< +10ns>: fe 05 ?**** 0 1;
|
||||
< +10ns>: fe 06 ?**** 0 1;
|
||||
< +10ns>: fe 06 ?**** 0 1;
|
||||
< +10ns>: fe 07 ?**** 0 1;
|
||||
< +10ns>: fe 07 ?**** 0 1;
|
||||
< +10ns>: fe 08 ?**** 0 1;
|
||||
< +10ns>: fe 08 ?**** 0 1;
|
||||
< +10ns>: fe 09 ?**** 0 1;
|
||||
< +10ns>: fe 09 ?**** 0 1;
|
||||
< +10ns>: fe 0a ?**** 0 1;
|
||||
< +10ns>: fe 0a ?**** 0 1;
|
||||
< +10ns>: fe 0b ?**** 0 1;
|
||||
< +10ns>: fe 0b ?**** 0 1;
|
||||
< +10ns>: fe 0c ?**** 0 1;
|
||||
< +10ns>: fe 0c ?**** 0 1;
|
||||
< +10ns>: fe 0d ?**** 0 1;
|
||||
< +10ns>: fe 0d ?**** 0 1;
|
||||
< +10ns>: fe 0e ?**** 0 1;
|
||||
< +10ns>: fe 0e ?**** 0 1;
|
||||
< +10ns>: fe 0f ?**** 0 1;
|
||||
< +10ns>: fe 0f ?**** 0 1;
|
||||
< +10ns>: ff 01 ?**** 0 1;
|
||||
< +10ns>: ff 01 ?**** 0 1;
|
||||
< +10ns>: ff 02 ?**** 0 1;
|
||||
< +10ns>: ff 02 ?**** 0 1;
|
||||
< +10ns>: ff 03 ?**** 0 1;
|
||||
< +10ns>: ff 03 ?**** 0 1;
|
||||
< +10ns>: ff 04 ?**** 0 1;
|
||||
< +10ns>: ff 04 ?**** 0 1;
|
||||
< +10ns>: ff 05 ?**** 0 1;
|
||||
< +10ns>: ff 05 ?**** 0 1;
|
||||
< +10ns>: ff 06 ?**** 0 1;
|
||||
< +10ns>: ff 06 ?**** 0 1;
|
||||
< +10ns>: ff 07 ?**** 0 1;
|
||||
< +10ns>: ff 07 ?**** 0 1;
|
||||
< +10ns>: ff 08 ?**** 0 1;
|
||||
< +10ns>: ff 08 ?**** 0 1;
|
||||
< +10ns>: ff 09 ?**** 0 1;
|
||||
< +10ns>: ff 09 ?**** 0 1;
|
||||
< +10ns>: ff 0a ?**** 0 1;
|
||||
< +10ns>: ff 0a ?**** 0 1;
|
||||
< +10ns>: ff 0b ?**** 0 1;
|
||||
< +10ns>: ff 0b ?**** 0 1;
|
||||
< +10ns>: ff 0c ?**** 0 1;
|
||||
< +10ns>: ff 0c ?**** 0 1;
|
||||
< +10ns>: ff 0d ?**** 0 1;
|
||||
< +10ns>: ff 0d ?**** 0 1;
|
||||
< +10ns>: ff 0e ?**** 0 1;
|
||||
< +10ns>: ff 0e ?**** 0 1;
|
||||
< +10ns>: ff 0f ?**** 0 1;
|
||||
< +10ns>: ff 0f ?**** 0 1;
|
||||
|
||||
end;
|
||||
|
|
@ -0,0 +1,124 @@
|
|||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity Multi8 is
|
||||
|
||||
|
||||
port ( X : in Std_Logic_Vector(7 downto 0) ;
|
||||
Y : in Std_Logic_Vector(7 downto 0) ;
|
||||
R : out Std_Logic_Vector(15 downto 0) );
|
||||
|
||||
end Multi8;
|
||||
|
||||
----------------------------------------------------------------------
|
||||
|
||||
architecture beh OF Multi8 is
|
||||
|
||||
signal PP1 : Std_Logic_Vector(8 downto 0);
|
||||
signal PP2 : Std_Logic_Vector(8 downto 0);
|
||||
signal PP3 : Std_Logic_Vector(8 downto 0);
|
||||
signal PP4 : Std_Logic_Vector(8 downto 0);
|
||||
signal PP5 : Std_Logic_Vector(8 downto 0);
|
||||
signal PP6 : Std_Logic_Vector(8 downto 0);
|
||||
signal PP7 : Std_Logic_Vector(8 downto 0);
|
||||
signal PP8 : Std_Logic_Vector(8 downto 0);
|
||||
|
||||
signal PP12 : Std_Logic_Vector(9 downto 0);
|
||||
signal PP34 : Std_Logic_Vector(9 downto 0);
|
||||
signal PP56 : Std_Logic_Vector(9 downto 0);
|
||||
signal PP78 : Std_Logic_Vector(9 downto 0);
|
||||
|
||||
signal R1, R2 : Std_Logic_Vector(11 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
PP1(0) <= Y(0) and X(0);
|
||||
PP1(1) <= Y(0) and X(1);
|
||||
PP1(2) <= Y(0) and X(2);
|
||||
PP1(3) <= Y(0) and X(3);
|
||||
PP1(4) <= Y(0) and X(4);
|
||||
PP1(5) <= Y(0) and X(5);
|
||||
PP1(6) <= Y(0) and X(6);
|
||||
PP1(7) <= Y(0) and X(7);
|
||||
PP1(8) <= '0';
|
||||
|
||||
PP2(0) <= '0';
|
||||
PP2(1) <= Y(1) and X(0);
|
||||
PP2(2) <= Y(1) and X(1);
|
||||
PP2(3) <= Y(1) and X(2);
|
||||
PP2(4) <= Y(1) and X(3);
|
||||
PP2(5) <= Y(1) and X(4);
|
||||
PP2(6) <= Y(1) and X(5);
|
||||
PP2(7) <= Y(1) and X(6);
|
||||
PP2(8) <= Y(1) and X(7);
|
||||
|
||||
PP3(0) <= Y(2) and X(0);
|
||||
PP3(1) <= Y(2) and X(1);
|
||||
PP3(2) <= Y(2) and X(2);
|
||||
PP3(3) <= Y(2) and X(3);
|
||||
PP3(4) <= Y(2) and X(4);
|
||||
PP3(5) <= Y(2) and X(5);
|
||||
PP3(6) <= Y(2) and X(6);
|
||||
PP3(7) <= Y(2) and X(7);
|
||||
PP3(8) <= '0';
|
||||
|
||||
PP4(0) <= '0';
|
||||
PP4(1) <= Y(3) and X(0);
|
||||
PP4(2) <= Y(3) and X(1);
|
||||
PP4(3) <= Y(3) and X(2);
|
||||
PP4(4) <= Y(3) and X(3);
|
||||
PP4(5) <= Y(3) and X(4);
|
||||
PP4(6) <= Y(3) and X(5);
|
||||
PP4(7) <= Y(3) and X(6);
|
||||
PP4(8) <= Y(3) and X(7);
|
||||
|
||||
PP5(0) <= Y(4) and X(0);
|
||||
PP5(1) <= Y(4) and X(1);
|
||||
PP5(2) <= Y(4) and X(2);
|
||||
PP5(3) <= Y(4) and X(3);
|
||||
PP5(4) <= Y(4) and X(4);
|
||||
PP5(5) <= Y(4) and X(5);
|
||||
PP5(6) <= Y(4) and X(6);
|
||||
PP5(7) <= Y(4) and X(7);
|
||||
PP5(8) <= '0';
|
||||
|
||||
PP6(0) <= '0';
|
||||
PP6(1) <= Y(5) and X(0);
|
||||
PP6(2) <= Y(5) and X(1);
|
||||
PP6(3) <= Y(5) and X(2);
|
||||
PP6(4) <= Y(5) and X(3);
|
||||
PP6(5) <= Y(5) and X(4);
|
||||
PP6(6) <= Y(5) and X(5);
|
||||
PP6(7) <= Y(5) and X(6);
|
||||
PP6(8) <= Y(5) and X(7);
|
||||
|
||||
PP7(0) <= Y(6) and X(0);
|
||||
PP7(1) <= Y(6) and X(1);
|
||||
PP7(2) <= Y(6) and X(2);
|
||||
PP7(3) <= Y(6) and X(3);
|
||||
PP7(4) <= Y(6) and X(4);
|
||||
PP7(5) <= Y(6) and X(5);
|
||||
PP7(6) <= Y(6) and X(6);
|
||||
PP7(7) <= Y(6) and X(7);
|
||||
PP7(8) <= '0';
|
||||
|
||||
PP8(0) <= '0';
|
||||
PP8(1) <= Y(7) and X(0);
|
||||
PP8(2) <= Y(7) and X(1);
|
||||
PP8(3) <= Y(7) and X(2);
|
||||
PP8(4) <= Y(7) and X(3);
|
||||
PP8(5) <= Y(7) and X(4);
|
||||
PP8(6) <= Y(7) and X(5);
|
||||
PP8(7) <= Y(7) and X(6);
|
||||
PP8(8) <= Y(7) and X(7);
|
||||
|
||||
PP12 <= PP1 + PP2;
|
||||
PP34 <= PP3 + PP4;
|
||||
PP56 <= PP5 + PP6;
|
||||
PP78 <= PP7 + PP8;
|
||||
|
||||
R1 <= ("00" & PP12) + (PP34 & "00");
|
||||
R2 <= ("00" & PP56) + (PP78 & "00");
|
||||
R <= ("0000" & R1) + (R2 & "0000");
|
||||
|
||||
end beh;
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
calcul C
|
||||
pgcd_model C
|
||||
sequenceur C
|
||||
|
|
@ -0,0 +1,330 @@
|
|||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | File : Makefile |
|
||||
# | |
|
||||
# | Author : Jacomme Ludovic |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | Cells |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | Binary |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
|
||||
ALLIANCE_BIN=$(ALLIANCE_TOP)/bin
|
||||
|
||||
VASY = $(ALLIANCE_BIN)/vasy
|
||||
ASIMUT = $(ALLIANCE_BIN)/asimut
|
||||
BOOM = $(ALLIANCE_BIN)/boom
|
||||
BOOG = $(ALLIANCE_BIN)/boog
|
||||
LOON = $(ALLIANCE_BIN)/loon
|
||||
OCP = $(ALLIANCE_BIN)/ocp
|
||||
NERO = $(ALLIANCE_BIN)/nero
|
||||
COUGAR = $(ALLIANCE_BIN)/cougar
|
||||
LVX = $(ALLIANCE_BIN)/lvx
|
||||
DRUC = $(ALLIANCE_BIN)/druc
|
||||
S2R = $(ALLIANCE_BIN)/s2r
|
||||
|
||||
DREAL = $(ALLIANCE_BIN)/dreal
|
||||
GRAAL = $(ALLIANCE_BIN)/graal
|
||||
XSCH = $(ALLIANCE_BIN)/xsch
|
||||
XPAT = $(ALLIANCE_BIN)/xpat
|
||||
XFSM = $(ALLIANCE_BIN)/xfsm
|
||||
|
||||
TOUCH = touch
|
||||
|
||||
TARGET_LIB = $(ALLIANCE_TOP)/cells/sxlib
|
||||
RDS_TECHNO_SYMB = ../etc/techno-symb.rds
|
||||
RDS_TECHNO = ../etc/techno-035.rds
|
||||
SPI_MODEL = $(ALLIANCE_TOP)/etc/spimodel.cfg
|
||||
METAL_LEVEL = 2
|
||||
|
||||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | Environement |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
|
||||
ENV_VASY = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
|
||||
MBK_CATAL_NAME=NO_CATAL; export MBK_CATAL_NAME
|
||||
|
||||
ENV_BOOM = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
|
||||
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
|
||||
|
||||
ENV_BOOG = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
|
||||
MBK_IN_LO=vst; export MBK_IN_LO; \
|
||||
MBK_OUT_LO=vst; export MBK_OUT_LO; \
|
||||
MBK_TARGET_LIB=$(TARGET_LIB); export MBK_TARGET_LIB; \
|
||||
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
|
||||
|
||||
ENV_LOON = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
|
||||
MBK_IN_LO=vst; export MBK_IN_LO; \
|
||||
MBK_OUT_LO=vst; export MBK_OUT_LO; \
|
||||
MBK_TARGET_LIB=$(TARGET_LIB); export MBK_TARGET_LIB; \
|
||||
MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
|
||||
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
|
||||
|
||||
ENV_ASIMUT_VASY = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
|
||||
MBK_CATAL_NAME=CATAL_ASIMUT_VASY; export MBK_CATAL_NAME;\
|
||||
MBK_IN_LO=vst; export MBK_IN_LO;\
|
||||
MBK_OUT_LO=vst; export MBK_OUT_LO
|
||||
|
||||
ENV_ASIMUT_SYNTH = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
|
||||
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME;\
|
||||
MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
|
||||
MBK_IN_LO=vst; export MBK_IN_LO;\
|
||||
MBK_OUT_LO=vst; export MBK_OUT_LO
|
||||
|
||||
ENV_OCP = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
|
||||
MBK_IN_LO=vst; export MBK_IN_LO; \
|
||||
MBK_OUT_LO=vst; export MBK_OUT_LO; \
|
||||
MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
|
||||
MBK_IN_PH=ap; export MBK_IN_PH; \
|
||||
MBK_OUT_PH=ap; export MBK_OUT_PH; \
|
||||
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
|
||||
|
||||
ENV_NERO = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
|
||||
MBK_IN_LO=vst; export MBK_IN_LO; \
|
||||
MBK_OUT_LO=vst; export MBK_OUT_LO; \
|
||||
MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
|
||||
MBK_IN_PH=ap; export MBK_IN_PH; \
|
||||
MBK_OUT_PH=ap; export MBK_OUT_PH; \
|
||||
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
|
||||
|
||||
ENV_COUGAR_SPI = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
|
||||
MBK_IN_LO=spi; export MBK_IN_LO; \
|
||||
MBK_OUT_LO=spi; export MBK_OUT_LO; \
|
||||
MBK_SPI_NAMEDNODES="true"; export MBK_SPI_NAMEDNODES; \
|
||||
MBK_SPI_MODEL=$(SPI_MODEL); export MBK_SPI_MODEL; \
|
||||
RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME; \
|
||||
RDS_IN=cif; export RDS_IN; \
|
||||
RDS_OUT=cif; export RDS_OUT; \
|
||||
MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
|
||||
MBK_IN_PH=ap; export MBK_IN_PH; \
|
||||
MBK_OUT_PH=ap; export MBK_OUT_PH; \
|
||||
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
|
||||
|
||||
ENV_COUGAR = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
|
||||
MBK_IN_LO=al; export MBK_IN_LO; \
|
||||
MBK_OUT_LO=al; export MBK_OUT_LO; \
|
||||
RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME; \
|
||||
RDS_IN=cif; export RDS_IN; \
|
||||
RDS_OUT=cif; export RDS_OUT; \
|
||||
MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
|
||||
MBK_IN_PH=ap; export MBK_IN_PH; \
|
||||
MBK_OUT_PH=ap; export MBK_OUT_PH; \
|
||||
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
|
||||
|
||||
ENV_LVX = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
|
||||
MBK_IN_LO=vst; export MBK_IN_LO; \
|
||||
MBK_OUT_LO=vst; export MBK_OUT_LO; \
|
||||
MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
|
||||
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
|
||||
|
||||
ENV_DRUC = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
|
||||
RDS_TECHNO_NAME=$(RDS_TECHNO_SYMB); export RDS_TECHNO_NAME; \
|
||||
MBK_IN_PH=ap; export MBK_IN_PH; \
|
||||
MBK_OUT_PH=ap; export MBK_OUT_PH; \
|
||||
MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
|
||||
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
|
||||
|
||||
ENV_S2R = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
|
||||
RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME; \
|
||||
RDS_IN=cif; export RDS_IN; \
|
||||
RDS_OUT=cif; export RDS_OUT; \
|
||||
MBK_IN_PH=ap; export MBK_IN_PH; \
|
||||
MBK_OUT_PH=ap; export MBK_OUT_PH; \
|
||||
MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
|
||||
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
|
||||
|
||||
|
||||
all : pgcd.cif
|
||||
|
||||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | Vasy |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
|
||||
pgcd.vst calcul.vbe sequenceur.vbe pgcd_model.vbe : pgcd.vhdl calcul.vhdl \
|
||||
sequenceur.vhdl pgcd.vhdl
|
||||
$(ENV_VASY); $(VASY) -a -B -o -p -I vhdl -H pgcd
|
||||
|
||||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | Asimut |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
|
||||
res_vasy_1.pat : pgcd.vst calcul.vbe \
|
||||
sequenceur.vbe pgcd_model.vbe
|
||||
$(ENV_ASIMUT_VASY); $(ASIMUT) pgcd pgcd res_vasy_1
|
||||
|
||||
res_synth_1.pat : pgcd.vst calcul.vst \
|
||||
sequenceur.vst pgcd_model.vst
|
||||
$(ENV_ASIMUT_SYNTH); $(ASIMUT) pgcd pgcd res_synth_1
|
||||
|
||||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | Boom |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
|
||||
boom.done : calcul_o.vbe sequenceur_o.vbe \
|
||||
pgcd_model_o.vbe
|
||||
@$(TOUCH) boom.done
|
||||
|
||||
calcul_o.vbe : calcul.vbe calcul.boom res_vasy_1.pat
|
||||
$(ENV_BOOM); $(BOOM) -VPA calcul calcul_o
|
||||
|
||||
sequenceur_o.vbe : sequenceur.vbe sequenceur.boom res_vasy_1.pat
|
||||
$(ENV_BOOM); $(BOOM) -VP sequenceur sequenceur_o
|
||||
|
||||
pgcd_model_o.vbe : pgcd_model.vbe pgcd_model.boom res_vasy_1.pat
|
||||
$(ENV_BOOM); $(BOOM) -VP pgcd_model pgcd_model_o
|
||||
|
||||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | Boog |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
|
||||
boog.done : calcul_o.vst sequenceur_o.vst \
|
||||
pgcd_model_o.vst
|
||||
@$(TOUCH) boog.done
|
||||
|
||||
calcul_o.vst : calcul_o.vbe
|
||||
$(ENV_BOOG); $(BOOG) calcul_o
|
||||
|
||||
sequenceur_o.vst : sequenceur_o.vbe
|
||||
$(ENV_BOOG); $(BOOG) sequenceur_o
|
||||
|
||||
pgcd_model_o.vst : pgcd_model_o.vbe
|
||||
$(ENV_BOOG); $(BOOG) pgcd_model_o
|
||||
|
||||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | Loon |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
|
||||
loon.done : calcul.vst sequenceur.vst \
|
||||
pgcd_model.vst
|
||||
@$(TOUCH) loon.done
|
||||
|
||||
calcul.vst : calcul_o.vst
|
||||
$(ENV_LOON); $(LOON) calcul_o calcul
|
||||
|
||||
sequenceur.vst : sequenceur_o.vst
|
||||
$(ENV_LOON); $(LOON) sequenceur_o sequenceur
|
||||
|
||||
pgcd_model.vst : pgcd_model_o.vst
|
||||
$(ENV_LOON); $(LOON) pgcd_model_o pgcd_model
|
||||
|
||||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | OCP |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
|
||||
pgcd_p.ap : res_synth_1.pat
|
||||
$(ENV_OCP); $(OCP) -v -ioc pgcd -gnuplot pgcd pgcd_p
|
||||
|
||||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | NERO |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
|
||||
pgcd.ap : pgcd_p.ap pgcd.vst
|
||||
$(ENV_NERO); $(NERO) -v -$(METAL_LEVEL) -p pgcd_p pgcd pgcd
|
||||
|
||||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | Cougar |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
|
||||
pgcd_e.spi : pgcd.ap
|
||||
$(ENV_COUGAR_SPI); $(COUGAR) -v -ac pgcd pgcd_e
|
||||
|
||||
pgcd_e.al : pgcd.ap
|
||||
$(ENV_COUGAR); $(COUGAR) -v -ac pgcd pgcd_e
|
||||
|
||||
pgcd_et.al : pgcd.ap
|
||||
$(ENV_COUGAR); $(COUGAR) -v -t -ac pgcd pgcd_et
|
||||
|
||||
pgcd_et.spi : pgcd.ap
|
||||
$(ENV_COUGAR_SPI); $(COUGAR) -v -ac -t pgcd pgcd_et
|
||||
|
||||
pgcd_er.spi : pgcd.cif
|
||||
$(ENV_COUGAR); $(COUGAR) -v -r -t pgcd pgcd_er
|
||||
|
||||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | Lvx |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
|
||||
lvx.done : pgcd.vst pgcd_e.al pgcd_e.spi
|
||||
$(ENV_LVX); $(LVX) vst al pgcd pgcd_e -f
|
||||
$(TOUCH) lvx.done
|
||||
|
||||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | Druc |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
|
||||
druc.done : lvx.done pgcd.ap
|
||||
$(ENV_DRUC); $(DRUC) pgcd
|
||||
$(TOUCH) druc.done
|
||||
|
||||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | S2R |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
|
||||
pgcd.cif : druc.done
|
||||
$(ENV_S2R); $(S2R) -v -t pgcd
|
||||
|
||||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | TOOLS |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
|
||||
graal: pgcd.ap
|
||||
$(ENV_S2R); $(GRAAL) -l pgcd
|
||||
|
||||
xsch: pgcd.vst
|
||||
$(ENV_LOON); $(XSCH) -l pgcd
|
||||
|
||||
xscht: pgcd_et.al
|
||||
$(ENV_COUGAR); $(XSCH) -l pgcd_et
|
||||
|
||||
xpat: res_synth_1.pat
|
||||
$(ENV_ASIMUT_SYNTH); $(XPAT) -l res_synth_1
|
||||
|
||||
dreal: pgcd.cif
|
||||
$(ENV_S2R); $(DREAL) -l pgcd
|
||||
|
||||
|
||||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | Clean |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
|
||||
realclean : clean
|
||||
|
||||
clean :
|
||||
$(RM) -f *.vst pgcd_e.spi *.vbe res_*.pat *.boom *.done *.xsc *.gpl \
|
||||
*.ap *.drc *.dat *.gds *.cif *.rep *.stm-data *.stm-plot \
|
||||
*.log *.out *.raw *.al
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
# /*------------------------------------------------------------\
|
||||
# | |
|
||||
# | File : README |
|
||||
# | |
|
||||
# | Author : Jacomme Ludovic |
|
||||
# | |
|
||||
# \------------------------------------------------------------*/
|
||||
|
||||
This directory contains hierarchical VHDL descriptions of a synchronous 8 bits
|
||||
greatest common divisor (with a finite state machine and a data part).
|
||||
It contains also the associated stimuli file, and configuration file for IO
|
||||
placement (used during the Place and Route step).
|
||||
|
||||
The Makefile set environement variables properly and run Alliance tools,
|
||||
following each step of the design flow from VHDL up to real layout in a
|
||||
pseudo 0.35 techno.
|
||||
|
||||
The environement variable ALLIANCE_TOP as to be set.
|
||||
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity calcul is
|
||||
port ( ck : in std_logic;
|
||||
a : in std_logic_vector(7 downto 0);
|
||||
b : in std_logic_vector(7 downto 0);
|
||||
res : out std_logic_vector(7 downto 0);
|
||||
ra_eq_rb : out std_logic;
|
||||
ra_inf_rb : out std_logic;
|
||||
wres_ra : in std_logic;
|
||||
wres_rb : in std_logic;
|
||||
ra_sub_rb : in std_logic;
|
||||
s_read : in std_logic );
|
||||
end calcul;
|
||||
|
||||
|
||||
|
||||
architecture behavioral of calcul is
|
||||
|
||||
signal RA : std_logic_vector(7 downto 0);
|
||||
signal RB : std_logic_vector(7 downto 0);
|
||||
signal RES_int : std_logic_vector(7 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
process( ck )
|
||||
begin
|
||||
if ( rising_edge( ck ) )
|
||||
then if ( s_read = '1' ) then RA <= A;
|
||||
elsif ( wres_ra = '1' ) then RA <= RES_int;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process( ck )
|
||||
begin
|
||||
if ( rising_edge( ck ) )
|
||||
then if ( s_read = '1' ) then RB <= B;
|
||||
elsif ( wres_rb = '1' ) then RB <= RES_int;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process( RA, RB, ra_sub_rb )
|
||||
begin
|
||||
if ( ra_sub_rb = '1' )
|
||||
then RES_int <= std_logic_vector(unsigned(RA) - unsigned(RB));
|
||||
else RES_int <= std_logic_vector(unsigned(RB) - unsigned(RA));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
RES <= RA;
|
||||
|
||||
process( RA, RB )
|
||||
begin
|
||||
if ( unsigned(RA) < unsigned( RB ) )
|
||||
then ra_inf_rb <= '1';
|
||||
else ra_inf_rb <= '0';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process( RA, RB )
|
||||
begin
|
||||
if ( RA = RB )
|
||||
then ra_eq_rb <= '1';
|
||||
else ra_eq_rb <= '0';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end behavioral;
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
|
||||
TOP ( # IOs are ordered from left to right
|
||||
(IOPIN ck.0 );
|
||||
(IOPIN reset.0 );
|
||||
(IOPIN empty.0 );
|
||||
(IOPIN full.0 );
|
||||
(IOPIN a(7).0 );
|
||||
(IOPIN a(6).0 );
|
||||
(IOPIN a(5).0 );
|
||||
(IOPIN a(4).0 );
|
||||
(IOPIN a(3).0 );
|
||||
(IOPIN a(2).0 );
|
||||
(IOPIN a(1).0 );
|
||||
(IOPIN a(0).0 );
|
||||
(IOPIN b(7).0 );
|
||||
(IOPIN b(6).0 );
|
||||
(IOPIN b(5).0 );
|
||||
(IOPIN b(4).0 );
|
||||
(IOPIN b(3).0 );
|
||||
(IOPIN b(2).0 );
|
||||
(IOPIN b(1).0 );
|
||||
(IOPIN b(0).0 );
|
||||
)
|
||||
BOTTOM ( # IOs are ordered from left to right
|
||||
(IOPIN res(7).0 );
|
||||
(IOPIN res(6).0 );
|
||||
(IOPIN res(5).0 );
|
||||
(IOPIN res(4).0 );
|
||||
(IOPIN res(3).0 );
|
||||
(IOPIN res(2).0 );
|
||||
(IOPIN res(1).0 );
|
||||
(IOPIN res(0).0 );
|
||||
(IOPIN s_read.0 );
|
||||
(IOPIN s_write.0 );
|
||||
)
|
||||
IGNORE ( # IOs are ignored(not placed) by IO Placer
|
||||
)
|
||||
|
|
@ -0,0 +1,116 @@
|
|||
--
|
||||
-- Patterns for pgcd
|
||||
--
|
||||
in ck B;
|
||||
in reset B;
|
||||
in empty B;
|
||||
in full B;;
|
||||
in a (7 downto 0) X;;
|
||||
in b (7 downto 0) X;;
|
||||
out res (7 downto 0) X;;
|
||||
out s_read B;
|
||||
out s_write B;
|
||||
|
||||
begin
|
||||
|
||||
|
||||
-- Reset
|
||||
|
||||
< 0ns> : 0 1 0 0 0c 04 ?** ?* ?*;
|
||||
< +3ns> : 0 1 0 0 0c 04 ?** ?* ?*;
|
||||
< +3ns> : 1 1 0 0 0c 04 ?** ?* ?*;
|
||||
< +3ns> : 1 1 0 0 0c 04 ?** ?* ?*;
|
||||
< +3ns> : 0 0 0 0 0c 04 ?** ?* ?*;
|
||||
< +3ns> : 0 0 0 0 0c 04 ?** ?* ?*;
|
||||
< +3ns> : 1 0 0 0 0c 04 ?** ?* ?*;
|
||||
< +3ns> : 1 0 0 0 0c 04 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 0 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
< +3ns> : 1 0 1 0 00 00 ?** ?* ?*;
|
||||
|
||||
end;
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity pgcd is
|
||||
port ( ck : in std_logic;
|
||||
a : in std_logic_vector (7 downto 0);
|
||||
b : in std_logic_vector (7 downto 0);
|
||||
empty : in std_logic;
|
||||
full : in std_logic;
|
||||
reset : in std_logic;
|
||||
res : out std_logic_vector (7 downto 0);
|
||||
s_read : out std_logic;
|
||||
s_write : out std_logic );
|
||||
end pgcd;
|
||||
|
||||
architecture pgcd of pgcd is
|
||||
|
||||
component sequenceur
|
||||
port ( ck : in std_logic;
|
||||
empty : in std_logic;
|
||||
full : in std_logic;
|
||||
reset : in std_logic;
|
||||
ra_eq_rb : in std_logic;
|
||||
ra_inf_rb : in std_logic;
|
||||
wres_ra : out std_logic;
|
||||
wres_rb : out std_logic;
|
||||
ra_sub_rb : out std_logic;
|
||||
s_write : out std_logic;
|
||||
s_read : out std_logic );
|
||||
end component;
|
||||
|
||||
component calcul
|
||||
port ( ck : in std_logic;
|
||||
a : in std_logic_vector(7 downto 0);
|
||||
b : in std_logic_vector(7 downto 0);
|
||||
res : out std_logic_vector(7 downto 0);
|
||||
ra_eq_rb : out std_logic;
|
||||
ra_inf_rb : out std_logic;
|
||||
wres_ra : in std_logic;
|
||||
wres_rb : in std_logic;
|
||||
ra_sub_rb : in std_logic;
|
||||
s_read : in std_logic );
|
||||
end component;
|
||||
|
||||
signal ra_eq_rb, ra_inf_rb, wres_ra, wres_rb, ra_sub_rb, int_s_read : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
s_read <= int_s_read;
|
||||
|
||||
e_sequenceur : sequenceur
|
||||
port map( ck => ck
|
||||
, empty => empty
|
||||
, full => full
|
||||
, reset => reset
|
||||
, ra_eq_rb => ra_eq_rb
|
||||
, ra_inf_rb => ra_inf_rb
|
||||
, wres_ra => wres_ra
|
||||
, wres_rb => wres_rb
|
||||
, ra_sub_rb => ra_sub_rb
|
||||
, s_read => int_s_read
|
||||
, s_write => s_write );
|
||||
|
||||
e_calcul : calcul
|
||||
port map( ck => ck
|
||||
, a => a
|
||||
, b => b
|
||||
, res => res
|
||||
, ra_eq_rb => ra_eq_rb
|
||||
, ra_inf_rb => ra_inf_rb
|
||||
, wres_ra => wres_ra
|
||||
, wres_rb => wres_rb
|
||||
, ra_sub_rb => ra_sub_rb
|
||||
, s_read => int_s_read );
|
||||
|
||||
end pgcd;
|
||||
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity sequenceur is
|
||||
port ( ck : in std_logic;
|
||||
empty : in std_logic;
|
||||
full : in std_logic;
|
||||
reset : in std_logic;
|
||||
ra_eq_rb : in std_logic;
|
||||
ra_inf_rb : in std_logic;
|
||||
wres_ra : out std_logic;
|
||||
wres_rb : out std_logic;
|
||||
ra_sub_rb : out std_logic;
|
||||
s_write : out std_logic;
|
||||
s_read : out std_logic );
|
||||
end sequenceur;
|
||||
|
||||
|
||||
architecture behavioral of sequenceur is
|
||||
type t_etat is (E1, E2, E3, E4);
|
||||
signal ec, ef : t_etat;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
process(ck)
|
||||
begin
|
||||
if(rising_edge(ck)) then
|
||||
if(reset = '1') then ec <= E1;
|
||||
else ec <= ef;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
process(ec, ra_eq_rb, ra_inf_rb, empty, full)
|
||||
begin
|
||||
wres_ra <= '0';
|
||||
wres_rb <= '0';
|
||||
ra_sub_rb <= '0';
|
||||
s_write <= '0';
|
||||
s_read <= '0';
|
||||
|
||||
case(ec) is
|
||||
when E1 =>
|
||||
if(empty = '1') then ef <= E1;
|
||||
else ef <= E2;
|
||||
end if;
|
||||
s_read <= '1';
|
||||
when E2 =>
|
||||
if( ra_eq_rb = '1') then ef <= E4;
|
||||
else ef <= E3;
|
||||
end if;
|
||||
when E3 =>
|
||||
wres_rb <= ra_inf_rb;
|
||||
wres_ra <= not(ra_inf_rb);
|
||||
ra_sub_rb <= not(ra_inf_rb);
|
||||
ef <= E2;
|
||||
when E4 =>
|
||||
if(full = '1') then ef <= E4;
|
||||
else ef <= E1;
|
||||
end if;
|
||||
s_write <= '1';
|
||||
end case;
|
||||
end process;
|
||||
|
||||
end behavioral;
|
||||
|
||||
Loading…
Reference in New Issue