- full working AMD2901
This commit is contained in:
Ludovic Jacomme
parent
aedeaf17b0
commit
42b008a67e
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#
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# /------------------------------------------------------------------\
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# | Macros definitions |
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# \------------------------------------------------------------------/
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#
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# Standart System binary access paths.
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STANDART_BIN = /usr/local/bin:/usr/bin:/bin
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STANDART_PATH = PATH=$(STANDART_BIN); export PATH
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# Standart Alliance binary access paths.
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ALLIANCE_BIN = $(ALLIANCE_TOP)/bin
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# --------------------------------------------------------------------
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# Standarts binaries.
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LS = /bin/ls
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CD = PATH=$(STANDART_BIN); cd
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CP = PATH=$(STANDART_BIN); cp
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LN = PATH=$(STANDART_BIN); ln
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MV = PATH=$(STANDART_BIN); mv
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RM = PATH=$(STANDART_BIN); rm
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SED = PATH=$(STANDART_BIN); sed
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AWK = PATH=$(STANDART_BIN); gawk
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CAT = PATH=$(STANDART_BIN); cat
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MAKE = PATH=$(STANDART_BIN); make
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TOUCH = PATH=$(STANDART_BIN); touch
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GREP = PATH=$(STANDART_BIN); grep
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ECHO = /bin/echo
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# Alliance paths and formats settings.
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GENERAT_LO = vst
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EXTRACT_LO = al
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GENERAT_PH = ap
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EXTRACT_PH = ap
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GENERAT_SP = .
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EXTRACT_SP = .
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CATA_LIB0 = $(ALLIANCE_TOP)/cells/sxlib
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CATA_LIB1 = $(ALLIANCE_TOP)/cells/dp_sxlib
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CATA_LIB2 = $(ALLIANCE_TOP)/cells/padlib
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CATA_LIB = .:$(CATA_LIB0):$(CATA_LIB1):$(CATA_LIB2)
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TARGET_LIB = $(ALLIANCE_TOP)/cells/sxlib
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RDS_TECHNO = ../etc/techno-symb.rds
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REAL_RDS_TECHNO = ../etc/techno-035.rds
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GRAAL_TECHNO = $(ALLIANCE_TOP)/etc/cmos.graal
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MBK_GENERAT_ENV = MBK_TARGET_LIB=$(TARGET_LIB); export MBK_TARGET_LIB; \
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MBK_WORK_LIB=.; export MBK_WORK_LIB; \
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MBK_CATA_LIB=$(CATA_LIB); export MBK_CATA_LIB; \
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME; \
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MBK_OUT_LO=$(GENERAT_LO); export MBK_OUT_LO; \
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MBK_OUT_PH=$(GENERAT_PH); export MBK_OUT_PH; \
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MBK_IN_LO=$(GENERAT_LO); export MBK_IN_LO; \
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MBK_IN_PH=$(GENERAT_PH); export MBK_IN_PH; \
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MBK_SEPAR=$(GENERAT_SP); export MBK_SEPAR; \
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MBK_VDD=vdd; export MBK_VDD; \
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MBK_VSS=vss; export MBK_VSS; \
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RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME; \
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GRAAL_TECHNO_NAME=$(GRAAL_TECHNO); export GRAAL_TECHNO_NAME
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# MBK extracting environment.
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MBK_EXTRACT_ENV = MBK_TARGET_LIB=$(TARGET_LIB); export MBK_TARGET_LIB; \
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MBK_WORK_LIB=.; export MBK_WORK_LIB; \
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MBK_CATA_LIB=$(CATA_LIB); export MBK_CATA_LIB; \
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME; \
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MBK_OUT_LO=$(EXTRACT_LO); export MBK_OUT_LO; \
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MBK_OUT_PH=$(EXTRACT_PH); export MBK_OUT_PH; \
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MBK_IN_LO=$(EXTRACT_LO); export MBK_IN_LO; \
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MBK_IN_PH=$(EXTRACT_PH); export MBK_IN_PH; \
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MBK_SEPAR=$(EXTRACT_SP); export MBK_SEPAR; \
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MBK_VDD=vdd; export MBK_VDD; \
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MBK_VSS=vss; export MBK_VSS; \
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RDS_TECHNO_NAME=$(REAL_RDS_TECHNO); export RDS_TECHNO_NAME;\
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GRAAL_TECHNO_NAME=$(GRAAL_TECHNO); export GRAAL_TECHNO_NAME
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MBK_EXTRACT_ENV_SPI = MBK_TARGET_LIB=$(TARGET_LIB); export MBK_TARGET_LIB; \
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MBK_WORK_LIB=.; export MBK_WORK_LIB; \
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MBK_CATA_LIB=$(CATA_LIB); export MBK_CATA_LIB; \
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME; \
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MBK_OUT_LO=spi; export MBK_OUT_LO; \
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MBK_OUT_PH=$(EXTRACT_PH); export MBK_OUT_PH; \
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MBK_IN_LO=spi; export MBK_IN_LO; \
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MBK_IN_PH=$(EXTRACT_PH); export MBK_IN_PH; \
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MBK_SEPAR=$(EXTRACT_SP); export MBK_SEPAR; \
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MBK_VDD=vdd; export MBK_VDD; \
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MBK_VSS=vss; export MBK_VSS; \
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RDS_TECHNO_NAME=$(REAL_RDS_TECHNO); export RDS_TECHNO_NAME;\
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GRAAL_TECHNO_NAME=$(GRAAL_TECHNO); export GRAAL_TECHNO_NAME
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# --------------------------------------------------------------------
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# Alliance binaries & environment.
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BOOM = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/boom -V
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BOOG = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/boog
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LOON = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/loon
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ASIMUT1 = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/asimut
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ASIMUT2 = $(MBK_EXTRACT_ENV); $(ALLIANCE_BIN)/asimut
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COUGAR = $(ALLIANCE_BIN)/cougar
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DRUC = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/druc
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LVX = $(MBK_EXTRACT_ENV); $(ALLIANCE_BIN)/lvx
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PROOF = $(MBK_EXTRACT_ENV); $(ALLIANCE_BIN)/proof
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GENLIB = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/genlib
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GENPAT = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/genpat
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OCP = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/ocp
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NERO = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/nero
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OCR = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/ocr
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RING = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/ring
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GRAAL = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/graal
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DREAL = $(MBK_EXTRACT_ENV); $(ALLIANCE_BIN)/dreal
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XSCH = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/xsch
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XPAT = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/xpat
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# /------------------------------------------------------------------\
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# | Rules |
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# \------------------------------------------------------------------/
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#
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all: nb_transistors
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ctl_part: amd2901_ctl.vst
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view_ctl_logic: amd2901_ctl.vst
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$(XSCH) -l amd2901_ctl
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dpt_part: amd2901_dpt.ap amd2901_dpt.vst
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view_dpt_physic: amd2901_dpt.ap
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$(GRAAL) -l amd2901_dpt
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chip_part: amd2901_chip.ap
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view_chip_physic: amd2901_chip.ap
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$(GRAAL) -l amd2901_chip
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chip_verification: druc_chip lvx_chip test_chip_final.pat
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view_chip_simulation: test_chip_final.pat
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$(XPAT) -l test_chip_final
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amd2901_core.vst amd2901_core_place.ap: amd2901_core.c amd2901_ctl.vst amd2901_ctl.vbe amd2901_dpt.vst amd2901_dpt.ap
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$(GENLIB) -v amd2901_core
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amd2901_chip.vst: amd2901_core.vst
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$(GENLIB) -v amd2901_chip
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test_chip.pat: amd2901_chip.vst pattern.pat
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$(ASIMUT1) -zd amd2901_chip pattern test_chip
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test_core.pat: amd2901_core.vst amd2901_core.pat
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$(ASIMUT1) -zd amd2901_core amd2901_core test_core
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# LUDO
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# pattern.pat: pattern.c
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# $(GENPAT) -v pattern
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amd2901_dpt.ap amd2901_dpt.vst: amd2901_dpt.c
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$(GENLIB) -v amd2901_dpt
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amd2901_ctl_boom.vbe : amd2901_ctl.vbe
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$(BOOM) amd2901_ctl amd2901_ctl_boom
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amd2901_ctl_boog.vst : amd2901_ctl_boom.vbe amd2901_ctl.lax
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$(BOOG) amd2901_ctl_boom amd2901_ctl_boog amd2901_ctl
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amd2901_ctl.vst : amd2901_ctl_boog.vst
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$(LOON) amd2901_ctl_boog amd2901_ctl
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amd2901_core_p.ap: amd2901_core.vst amd2901_core_place.ap amd2901_core.ioc
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$(OCP) -v -gnuplot -partial amd2901_core_place -ioc amd2901_core amd2901_core amd2901_core_p
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# $(OCP) -v -gnuplot -partial amd2901_core_place -ring amd2901_core amd2901_core_p
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druc_ocp: amd2901_core_p.ap
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$(DRUC) amd2901_core_p
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$(TOUCH) druc_ocp
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amd2901_core.ap: druc_ocp
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$(NERO) -2 -p amd2901_core_p amd2901_core amd2901_core
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# amd2901_core.ap: druc_ocp
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# $(OCR) -v -l 2 -L amd2901_core -P amd2901_core_p -O amd2901_core
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amd2901_core.al: amd2901_core.ap
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$(MBK_EXTRACT_ENV); $(COUGAR) -v -f amd2901_core amd2901_core
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amd2901_core.spi: amd2901_core.ap
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$(MBK_EXTRACT_ENV_SPI); $(COUGAR) -v -ac -t amd2901_core amd2901_core
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lvx_core: amd2901_core.al amd2901_core.vst
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$(LVX) al vst amd2901_core amd2901_core -f
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$(TOUCH) lvx_core
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druc_core: amd2901_core.ap
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$(DRUC) amd2901_core
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$(TOUCH) druc_core
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amd2901_chip.ap: test_chip.pat amd2901_core.ap amd2901_chip.rin druc_core lvx_core
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$(MBK_GENERAT_ENV); $(RING) amd2901_chip amd2901_chip
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amd2901_chip.al: amd2901_chip.ap
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$(MBK_EXTRACT_ENV); $(COUGAR) -v -f amd2901_chip amd2901_chip
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lvx_chip: amd2901_chip.al amd2901_chip.vst
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$(LVX) al vst amd2901_chip amd2901_chip -f
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$(TOUCH) lvx_chip
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druc_chip: amd2901_chip.ap
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$(DRUC) amd2901_chip
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$(TOUCH) druc_chip
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test_chip_final.pat: pattern.pat druc_chip lvx_chip
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$(ASIMUT2) -zd amd2901_chip pattern test_chip_final
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nb_transistors: amd2901_chip_tr.al amd2901_core_tr.al
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@echo "Number of transistors for the core: ";\
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$(GREP) -c "^T" amd2901_core_tr.al
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@echo "Number of transistors for the chip: ";\
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$(GREP) -c "^T" amd2901_chip_tr.al
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amd2901_chip_tr.al: test_chip_final.pat
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$(MBK_EXTRACT_ENV); $(COUGAR) -v -t amd2901_chip amd2901_chip_tr
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amd2901_core_tr.al: lvx_core druc_core
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$(MBK_EXTRACT_ENV); $(COUGAR) -v -t amd2901_core amd2901_core_tr
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# /*------------------------------------------------------------\
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# | |
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# | TOOLS |
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# | |
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# \------------------------------------------------------------*/
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graal: amd2901_chip.ap
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$(GRAAL) -l amd2901_chip
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xsch: amd2901_ctl.vst
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$(XSCH) -l amd2901_ctl
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xpat: test_chip_final.pat
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$(XPAT) -l test_chip_final
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dreal: amd2901_chip.cif
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$(DREAL) -l amd2901_chip
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# /*------------------------------------------------------------\
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# | |
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# | CLEAN |
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# | |
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# \------------------------------------------------------------*/
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clean :
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rm -f Makefile-* \
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amd2901_core.vst \
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amd2901_chip.vst \
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amd2901_ctl.vst \
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amd2901_dpt.vst \
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amd2901_ctl_boog.vst \
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amd2901_ctl_boom.vbe \
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*.ap \
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res.pat \
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*.frr \
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*.log \
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*.drc \
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*.gds \
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*.def \
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*.gpl \
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*.xsc \
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*.al \
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test_*.pat \
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*~ \
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*cif \
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lvx_core druc_core \
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lvx_chip druc_chip \
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druc_ocp alldata.dat \
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model_*
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@ -0,0 +1,134 @@
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#include <genlib.h>
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#define POWER "vdde","vdd","vsse","vss",0
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int main ()
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{
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int i;
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GENLIB_DEF_LOFIG("amd2901_chip");
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GENLIB_LOCON("ck", IN ,"ck");
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GENLIB_LOCON( "cin", IN, "cin");
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GENLIB_LOCON( "cout", OUT, "cout");
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GENLIB_LOCON( "np", OUT , "np");
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GENLIB_LOCON( "ng", OUT , "ng");
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GENLIB_LOCON( "ovr", OUT , "ovr");
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GENLIB_LOCON( "zero", OUT , "zero");
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GENLIB_LOCON("signe", UNKNOWN,"signe");
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GENLIB_LOCON("r0", UNKNOWN, "r0");
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GENLIB_LOCON("r3", UNKNOWN, "r3");
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GENLIB_LOCON("q0", UNKNOWN, "q0");
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GENLIB_LOCON("q3", UNKNOWN, "q3");
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GENLIB_LOCON( "fonc", IN , "fonc");
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GENLIB_LOCON( "test", IN , "test");
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GENLIB_LOCON( "scin", IN , "scin");
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GENLIB_LOCON("scout", OUT ,"scout");
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GENLIB_LOCON("a[3:0]", IN , "a[3:0]");
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GENLIB_LOCON("b[3:0]", IN , "b[3:0]");
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GENLIB_LOCON("d[3:0]", IN , "d[3:0]");
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GENLIB_LOCON("i[8:0]", IN , "i[8:0]");
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GENLIB_LOCON("noe" , IN , "noe" );
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GENLIB_LOCON("y[3:0]", UNKNOWN, "y[3:0]");
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GENLIB_LOCON("vdd" , IN , "vdd" );
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GENLIB_LOCON("vss" , IN , "vss" );
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GENLIB_LOCON("vdde", IN , "vdde");
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GENLIB_LOCON("vsse", IN , "vsse");
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GENLIB_LOINSE ( "amd2901_core", "core",
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"cin => cin_i",
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"cout => cout_i",
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"np => np_i",
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"ng => ng_i",
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"over => ovr_i",
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"zero => zero_i",
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"sh_right => sh_right",
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"sh_left => sh_left",
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"ram_o_down => ram_o_down",
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"ram_o_up => ram_o_up",
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"ram_i_down => ram_i_down",
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"ram_i_up => ram_i_up",
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"acc_o_down => acc_o_down",
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"acc_o_up => acc_o_up",
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"acc_i_down => acc_i_down",
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"acc_i_up => acc_i_up",
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"fonc => fonc_i",
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"test => test_i",
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"scin => scin_i",
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"ck => ckc",
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"a[3:0] => a_i[3:0]",
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"b[3:0] => b_i[3:0]",
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"d[3:0] => d_i[3:0]",
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"i[8:0] => i_i[8:0]",
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"y[3:0] => y_i[3:0]",
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"noe => noe_i",
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"oe => oe",
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"vdd => vdd",
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"vss => vss",
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0);
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GENLIB_LOINS("pck_sp","p_ck","ck","cki", POWER);
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GENLIB_LOINS("pi_sp","p_fonc","fonc","fonc_i","cki", POWER );
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GENLIB_LOINS("pi_sp","p_test","test","test_i","cki", POWER );
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GENLIB_LOINS("pi_sp","p_scin","scin","scin_i","cki", POWER );
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GENLIB_LOINS("pi_sp","p_cin","cin","cin_i","cki", POWER );
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GENLIB_LOINS("pi_sp","p_noe","noe","noe_i","cki", POWER );
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for (i=0;i<4;i++)
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{
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GENLIB_LOINS("pi_sp",GENLIB_NAME("p_a%d",i), GENLIB_ELM("a",i), GENLIB_ELM("a_i",i), "cki", POWER );
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GENLIB_LOINS("pi_sp",GENLIB_NAME("p_b%d",i), GENLIB_ELM("b",i), GENLIB_ELM("b_i",i), "cki", POWER );
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GENLIB_LOINS("pi_sp",GENLIB_NAME("p_d%d",i), GENLIB_ELM("d",i), GENLIB_ELM("d_i",i), "cki", POWER );
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}
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for (i=0;i<9;i++)
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GENLIB_LOINS("pi_sp",GENLIB_NAME("p_i%d",i), GENLIB_ELM("i",i), GENLIB_ELM("i_i",i), "cki", POWER );
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GENLIB_LOINS("po_sp","p_cout","cout_i","cout","cki", POWER );
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GENLIB_LOINS("po_sp","p_np","np_i","np","cki", POWER );
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GENLIB_LOINS("po_sp","p_ng","ng_i","ng","cki", POWER );
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GENLIB_LOINS("po_sp","p_ovr","ovr_i","ovr","cki", POWER );
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GENLIB_LOINS("po_sp","p_zero","zero_i","zero","cki", POWER );
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GENLIB_LOINS("po_sp","p_signe","ram_o_up","signe","cki", POWER );
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GENLIB_LOINS("po_sp","p_scout","acc_o_up","scout","cki", POWER );
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||||
|
||||
for (i=0;i<4;i++)
|
||||
GENLIB_LOINS ("pot_sp",GENLIB_NAME("p_y%d",i),
|
||||
GENLIB_ELM("y_i",i), "oe", GENLIB_ELM("y",i), "cki", POWER );
|
||||
|
||||
GENLIB_LOINS ("piot_sp","p_q0",
|
||||
"acc_o_down","sh_right","acc_i_down","q0","cki", POWER );
|
||||
GENLIB_LOINS ("piot_sp","p_q3",
|
||||
"acc_o_up","sh_left","acc_i_up","q3","cki", POWER );
|
||||
GENLIB_LOINS ("piot_sp","p_r0",
|
||||
"ram_o_down","sh_right","ram_i_down","r0","cki", POWER );
|
||||
GENLIB_LOINS ("piot_sp","p_r3",
|
||||
"ram_o_up","sh_left","ram_i_up","r3","cki", POWER );
|
||||
|
||||
GENLIB_LOINS("pvddick_sp","p_vddick0","ckc","cki","vdde","vdd","vsse","vss",0);
|
||||
GENLIB_LOINS("pvssick_sp","p_vssick0","ckc","cki","vdde","vdd","vsse","vss",0);
|
||||
|
||||
GENLIB_LOINS("pvddeck_sp","p_vddeck0","ckc","cki","vdde","vdd","vsse","vss",0);
|
||||
GENLIB_LOINS("pvddeck_sp","p_vddeck1","ckc","cki","vdde","vdd","vsse","vss",0);
|
||||
GENLIB_LOINS("pvsseck_sp","p_vsseck0","ckc","cki","vdde","vdd","vsse","vss",0);
|
||||
GENLIB_LOINS("pvsseck_sp","p_vsseck1","ckc","cki","vdde","vdd","vsse","vss",0);
|
||||
|
||||
GENLIB_SAVE_LOFIG();
|
||||
|
||||
exit (0);
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
east (p_q0 p_q3 p_b0 p_b1 p_b2 p_vddeck0 p_vsseck0 p_zero p_scout p_signe p_y2 p_y3 )
|
||||
west (p_b3 p_cin p_ck p_cout p_vddick0 p_vssick0 p_vddeck1 p_vsseck1 p_i3 p_i4 p_i5 p_i6 )
|
||||
north ( p_d0 p_d1 p_d2 p_d3 p_fonc p_i0 p_i1 p_i2 p_a0 p_a1 p_a2 p_a3 )
|
||||
south ( p_i7 p_i8 p_ng p_noe p_np p_ovr p_r0 p_r3 p_scin p_test p_y0 p_y1 )
|
||||
|
|
@ -0,0 +1,173 @@
|
|||
#include <genlib.h>
|
||||
|
||||
main()
|
||||
{
|
||||
GENLIB_DEF_LOFIG ("amd2901_core");
|
||||
GENLIB_DEF_PHFIG ("amd2901_core_place");
|
||||
|
||||
|
||||
/* ***************** Terminal Declarations ****************** */
|
||||
|
||||
|
||||
/* Pin terminals associated with ALU. */
|
||||
GENLIB_LOCON("cin", UNKNOWN, "cin" );
|
||||
GENLIB_LOCON("cout", UNKNOWN, "cout");
|
||||
GENLIB_LOCON("np", OUT , "np" );
|
||||
GENLIB_LOCON("ng", OUT , "ng" );
|
||||
GENLIB_LOCON("over", OUT , "over");
|
||||
GENLIB_LOCON("zero", OUT , "zero");
|
||||
|
||||
/* Pin terminals associated with the RAM and ACCU shifter. */
|
||||
/* RAM and ACCU I/O plots controls. */
|
||||
GENLIB_LOCON( "sh_right", OUT, "sh_right");
|
||||
GENLIB_LOCON( "sh_left" , OUT, "sh_left" );
|
||||
/* RAM shifter I/O. */
|
||||
GENLIB_LOCON("ram_o_down" ,UNKNOWN, "alu_f[0]" );
|
||||
GENLIB_LOCON("ram_o_up" ,UNKNOWN, "alu_f[3]" );
|
||||
GENLIB_LOCON("ram_i_down" , IN , "ram_i_down" );
|
||||
GENLIB_LOCON("ram_i_up" , IN , "ram_i_up" );
|
||||
/* ACC shifter I/O. */
|
||||
GENLIB_LOCON("acc_o_down" ,UNKNOWN, "acc_o_down" );
|
||||
GENLIB_LOCON("acc_o_up" ,UNKNOWN, "acc_scout" );
|
||||
GENLIB_LOCON("acc_i_down" , IN , "acc_i_down" );
|
||||
GENLIB_LOCON("acc_i_up" , IN , "acc_i_up" );
|
||||
|
||||
/* ACCU controls terminals. */
|
||||
GENLIB_LOCON( "fonc", IN , "fonc");
|
||||
GENLIB_LOCON( "test", IN , "test");
|
||||
GENLIB_LOCON( "scin", IN , "scin");
|
||||
GENLIB_LOCON( "ck", IN , "ck");
|
||||
|
||||
/* Data bus terminals. */
|
||||
GENLIB_LOCON( "a[3:0]", IN , "a[3:0]");
|
||||
GENLIB_LOCON( "b[3:0]", IN , "b[3:0]");
|
||||
GENLIB_LOCON( "d[3:0]", IN , "d[3:0]");
|
||||
GENLIB_LOCON( "i[8:0]", IN , "i[8:0]");
|
||||
GENLIB_LOCON( "y[3:0]", OUT , "y[3:0]");
|
||||
|
||||
GENLIB_LOCON( "noe", IN, "noe");
|
||||
GENLIB_LOCON( "oe", OUT, "oe");
|
||||
|
||||
/* Power suplies terminals. */
|
||||
GENLIB_LOCON("vdd", IN ,"vdd");
|
||||
GENLIB_LOCON("vss", IN ,"vss");
|
||||
|
||||
|
||||
/* **************** Data-Path Instanciation ***************** */
|
||||
|
||||
|
||||
GENLIB_LOINSE("amd2901_dpt", "amd2901_dpt",
|
||||
/* ck */
|
||||
"ram_ck[0] => ck",
|
||||
"ram_ck[1] => ck",
|
||||
"ram_ck[2] => ck",
|
||||
"ram_ck[3] => ck",
|
||||
"ram_ck[4] => ck",
|
||||
"ram_ck[5] => ck",
|
||||
"ram_ck[6] => ck",
|
||||
"ram_ck[7] => ck",
|
||||
"ram_ck[8] => ck",
|
||||
"ram_ck[9] => ck",
|
||||
"ram_ck[10] => ck",
|
||||
"ram_ck[11] => ck",
|
||||
"ram_ck[12] => ck",
|
||||
"ram_ck[13] => ck",
|
||||
"ram_ck[14] => ck",
|
||||
"ram_ck[15] => ck",
|
||||
"ops_mx[2:0] => ops_mx[2:0]",
|
||||
"opr_mx[1:0] => opr_mx[1:0]",
|
||||
"alu_k[4:0] => alu_k[4:0]",
|
||||
"alu_cin => cin", /* plot */
|
||||
"alu_cout => cout",
|
||||
"alu_over => alu_over",
|
||||
|
||||
"ram_sh[1:0] => ram_sh[1:0]",
|
||||
"acc_sh[1:0] => ram_sh[1:0]",
|
||||
"ram_i_up => ram_i_up",
|
||||
"ram_i_down => ram_i_down",
|
||||
"acc_i_up => acc_i_up",
|
||||
"acc_i_down => acc_i_down",
|
||||
"acc_q_down => acc_o_down",
|
||||
|
||||
"out_mx => out_mx",
|
||||
|
||||
"acc_ck => ck",
|
||||
"acc_wen => acc_wen",
|
||||
"acc_test => test", /* plot */
|
||||
"acc_scin => scin", /* plot */
|
||||
"acc_scout => acc_scout",
|
||||
|
||||
"a[15:0] => deca[15:0]",
|
||||
"b[15:0] => decb[15:0]",
|
||||
"b_w[15:0] => decwb[15:0]",
|
||||
|
||||
|
||||
"opr_d[3:0] => d[3:0]",
|
||||
"alu_f[3:0] => alu_f[3:0]",
|
||||
"alu_np[3:0] => alu_np[3:0]",
|
||||
"alu_ng[3:0] => alu_ng[3:0]",
|
||||
"out_x[3:0] => y[3:0]",
|
||||
|
||||
"vdd => vdd",
|
||||
"vss => vss", 0);
|
||||
|
||||
|
||||
/* ***************** Control Instanciation ****************** */
|
||||
|
||||
|
||||
GENLIB_LOINSE("amd2901_ctl", "ctl",
|
||||
|
||||
"ops_mx[2:0] => ops_mx[2:0]",
|
||||
"opr_mx[1:0] => opr_mx[1:0]",
|
||||
|
||||
"alu_k[4:0] => alu_k[4:0]",
|
||||
"alu_cout => cout",
|
||||
"alu_over => alu_over",
|
||||
|
||||
/******************************/
|
||||
"deca[15:0] => deca[15:0]",
|
||||
"decb[15:0] => decb[15:0]",
|
||||
"decwb[15:0] => decwb[15:0]",
|
||||
|
||||
"a[3:0] => a[3:0]",
|
||||
"b[3:0] => b[3:0]",
|
||||
|
||||
/**********************************/
|
||||
"ram_sh[1:0] => ram_sh[1:0]",
|
||||
|
||||
"out_mx => out_mx",
|
||||
|
||||
"acc_wen => acc_wen",
|
||||
|
||||
"alu_f[3:0] => alu_f[3:0]",
|
||||
"alu_np[3:0] => alu_np[3:0]",
|
||||
"alu_ng[3:0] => alu_ng[3:0]",
|
||||
|
||||
"core_test => test", /* plot */
|
||||
"core_fonc => fonc", /* plot */
|
||||
|
||||
"core_np => np", /* plot */
|
||||
"core_ng => ng", /* plot */
|
||||
"core_over => over", /* plot */
|
||||
"core_zero => zero", /* plot */
|
||||
|
||||
"core_sh_right => sh_right",
|
||||
"core_sh_left => sh_left",
|
||||
|
||||
"i[8:0] => i[8:0]",
|
||||
|
||||
|
||||
"noe => noe",
|
||||
"oe => oe",
|
||||
|
||||
"vdd => vdd",
|
||||
"vss => vss", 0);
|
||||
|
||||
GENLIB_PLACE ("amd2901_dpt", "amd2901_dpt", NOSYM, 0, 0);
|
||||
GENLIB_DEF_AB (0, 0, 0, 100);
|
||||
GENLIB_SAVE_LOFIG();
|
||||
GENLIB_SAVE_PHFIG();
|
||||
|
||||
|
||||
exit(0);
|
||||
}
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
# Copyright (c) 1997 by Cadence. All rights reserved.
|
||||
###################################################################
|
||||
# In each of TOP()/BOTTOM()/LEFT()/RIGHT() section, there are #
|
||||
# placed IOs. In the IGNORE() section, the IOs are ignored #
|
||||
# by the IOPlacer. In every section, the IO syntax could be: #
|
||||
# for pin: (IOPIN iopinName.0 ); #
|
||||
# for pad: iopadName orientation ; #
|
||||
# for space: SPACE value; #
|
||||
# The capital words are keywords. orientation is not required. #
|
||||
# The value is the space between the IO above and the IO below it.#
|
||||
###################################################################
|
||||
|
||||
TOP ( # IOs are ordered from left to right
|
||||
(IOPIN b(3).0 );
|
||||
(IOPIN cin.0 );
|
||||
(IOPIN ck.0 );
|
||||
(IOPIN cout.0 );
|
||||
(IOPIN d(0).0 );
|
||||
(IOPIN d(1).0 );
|
||||
(IOPIN d(2).0 );
|
||||
(IOPIN d(3).0 );
|
||||
(IOPIN fonc.0 );
|
||||
(IOPIN i(0).0 );
|
||||
(IOPIN i(1).0 );
|
||||
(IOPIN i(2).0 );
|
||||
(IOPIN a(0).0 );
|
||||
(IOPIN a(1).0 );
|
||||
(IOPIN a(2).0 );
|
||||
(IOPIN a(3).0 );
|
||||
(IOPIN ng.0 );
|
||||
(IOPIN acc_i_down.0 );
|
||||
(IOPIN acc_i_up.0 );
|
||||
(IOPIN acc_o_down.0 );
|
||||
(IOPIN acc_o_up.0 );
|
||||
(IOPIN b(0).0 );
|
||||
(IOPIN b(1).0 );
|
||||
(IOPIN b(2).0 );
|
||||
|
||||
)
|
||||
BOTTOM ( # IOs are ordered from left to right
|
||||
(IOPIN i(3).0 );
|
||||
(IOPIN i(4).0 );
|
||||
(IOPIN i(5).0 );
|
||||
(IOPIN i(6).0 );
|
||||
(IOPIN i(7).0 );
|
||||
(IOPIN i(8).0 );
|
||||
(IOPIN noe.0 );
|
||||
(IOPIN np.0 );
|
||||
(IOPIN oe.0 );
|
||||
(IOPIN over.0 );
|
||||
(IOPIN ram_i_down.0 );
|
||||
(IOPIN ram_i_up.0 );
|
||||
(IOPIN ram_o_down.0 );
|
||||
(IOPIN ram_o_up.0 );
|
||||
(IOPIN scin.0 );
|
||||
(IOPIN sh_left.0 );
|
||||
(IOPIN sh_right.0 );
|
||||
(IOPIN test.0 );
|
||||
(IOPIN y(0).0 );
|
||||
(IOPIN y(1).0 );
|
||||
(IOPIN y(2).0 );
|
||||
(IOPIN y(3).0 );
|
||||
(IOPIN zero.0 );
|
||||
)
|
||||
IGNORE ( # IOs are ignored(not placed) by IO Placer
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
##Used by boog and loon
|
||||
#M{4}
|
||||
## Set the Optimisation Level (1..5)
|
||||
## 1 : poor optimisation - small computation time
|
||||
## 5 : best optimisation - long computation time
|
||||
#L{5}
|
||||
|
|
@ -0,0 +1,249 @@
|
|||
ENTITY amd2901_ctl IS
|
||||
|
||||
PORT(
|
||||
-- Input/Output from and to the data-path.
|
||||
|
||||
|
||||
-- Command for selecting operands R and S.
|
||||
ops_mx : out BIT_VECTOR(2 downto 0);
|
||||
opr_mx : out BIT_VECTOR(1 downto 0);
|
||||
|
||||
-- ALU commands and auxiliary terminals.
|
||||
alu_k : out BIT_VECTOR(4 downto 0);
|
||||
alu_cout : in BIT;
|
||||
alu_over : in BIT;
|
||||
|
||||
-- RAM, ACCU shifter commands and auxiliary terminals.
|
||||
-- ("acc_sh" is same as "ram_sh")
|
||||
ram_sh : out BIT_VECTOR(1 downto 0);
|
||||
|
||||
-- Output multiplexer commnand (for X bus).
|
||||
out_mx : out BIT;
|
||||
|
||||
-- ACCU controls terminals.
|
||||
-- ("acc_ck", "acc_test" and "acc_scin" directly comes from the plots)
|
||||
acc_wen : out BIT;
|
||||
|
||||
-- Data bus terminals.
|
||||
alu_f : in BIT_VECTOR(3 downto 0);
|
||||
alu_np : in BIT_VECTOR(3 downto 0);
|
||||
alu_ng : in BIT_VECTOR(3 downto 0);
|
||||
|
||||
|
||||
-- Input/Output from and to the plots.
|
||||
|
||||
|
||||
-- Test terminals from/to plots.
|
||||
core_test : in BIT;
|
||||
core_fonc : in BIT;
|
||||
|
||||
-- ALU terminals from/to plots.
|
||||
-- core_ncout : out BIT;
|
||||
core_np : out BIT;
|
||||
core_ng : out BIT;
|
||||
core_over : out BIT;
|
||||
core_zero : out BIT;
|
||||
-- core_nsign : out BIT;
|
||||
|
||||
-- RAM, ACCU shifter terminals from/to plots.
|
||||
-- RAM and ACCU I/O plots controls.
|
||||
core_sh_right : out BIT;
|
||||
core_sh_left : out BIT;
|
||||
|
||||
-- Data bus terminals from/to the plots.
|
||||
i : in BIT_VECTOR(8 downto 0);
|
||||
|
||||
noe : in BIT;
|
||||
oe : out BIT;
|
||||
-- -
|
||||
-- ram_wri : out BIT;
|
||||
|
||||
-- +
|
||||
a : in BIT_VECTOR(3 downto 0);
|
||||
b : in BIT_VECTOR(3 downto 0);
|
||||
|
||||
deca : out BIT_VECTOR(15 downto 0);
|
||||
decb : out BIT_VECTOR(15 downto 0);
|
||||
decwb : out BIT_VECTOR(15 downto 0);
|
||||
|
||||
-- Power supply connectors.
|
||||
vdd : in BIT;
|
||||
vss : in BIT
|
||||
|
||||
-- -
|
||||
|
||||
);
|
||||
|
||||
END amd2901_ctl;
|
||||
|
||||
|
||||
ARCHITECTURE behavior_data_flow OF amd2901_ctl IS
|
||||
|
||||
-- Internals bus.
|
||||
SIGNAL alu_p : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL alu_g : BIT_VECTOR(3 downto 0);
|
||||
-- Internals signals.
|
||||
SIGNAL fonc_mode : BIT;
|
||||
SIGNAL ram_wri : BIT;
|
||||
SIGNAL interm : BIT_VECTOR (15 downto 0);
|
||||
BEGIN
|
||||
|
||||
|
||||
-- ******************** Miscellaneous controls *******************
|
||||
|
||||
|
||||
-- Select between normal and test mode.
|
||||
fonc_mode <= core_fonc and (not core_test);
|
||||
|
||||
|
||||
-- *************** ACCU and RAM multiplexer control **************
|
||||
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
ram_sh <= "00" WHEN B"110"
|
||||
| B"111",
|
||||
"01" WHEN B"100"
|
||||
| B"101",
|
||||
"11" WHEN OTHERS;
|
||||
|
||||
|
||||
-- ******************** S multiplexer control ********************
|
||||
|
||||
WITH i(2 downto 0) SELECT
|
||||
ops_mx <= "000" WHEN B"110",
|
||||
"000" WHEN B"010",
|
||||
"000" WHEN B"000",
|
||||
"010" WHEN B"101"
|
||||
| B"100",
|
||||
"001" WHEN B"001",
|
||||
"001" WHEN B"011",
|
||||
"100" WHEN B"111";
|
||||
|
||||
|
||||
-- ******************** R multiplexer control ********************
|
||||
|
||||
WITH i(2 downto 0) SELECT
|
||||
opr_mx <= "11" WHEN B"100"
|
||||
| B"010"
|
||||
| B"011",
|
||||
"01" WHEN B"101"
|
||||
| B"110"
|
||||
| B"111",
|
||||
"00" WHEN B"000"
|
||||
| B"001";
|
||||
|
||||
|
||||
-- ******************** X multiplexer control ********************
|
||||
|
||||
WITH i(8 downto 6) SELECT
|
||||
out_mx <= "1" WHEN B"010",
|
||||
"0" WHEN OTHERS;
|
||||
|
||||
|
||||
-- ************************* ALU control *************************
|
||||
|
||||
-- ALU commands.
|
||||
alu_k(4) <= ( i(5) or ( i(4) and i(3)));
|
||||
alu_k(3) <= (not i(5) and ( i(4) and i(3)));
|
||||
alu_k(2) <= ( i(5) and not i(4)) ;
|
||||
alu_k(1) <= i(5) xor i(4);
|
||||
alu_k(0) <= i(5) xor i(3);
|
||||
|
||||
-- Compute of ALU flags.
|
||||
-- Propagate.
|
||||
alu_p(3 downto 0) <= not alu_np(3 downto 0);
|
||||
core_np <= not ( alu_p(0)
|
||||
and alu_p(1)
|
||||
and alu_p(2)
|
||||
and alu_p(3));
|
||||
|
||||
-- Generate.
|
||||
alu_g(3 downto 0) <= not alu_ng(3 downto 0);
|
||||
core_ng <= not ( alu_g(3)
|
||||
or (alu_p(3) and alu_g(2))
|
||||
or (alu_p(3) and alu_p(2) and alu_g(1))
|
||||
or (alu_p(3) and alu_p(2) and alu_p(1) and alu_g(0)));
|
||||
|
||||
-- Sign, zero, overflow and carry out.
|
||||
-- core_nsign <= not alu_f(3);
|
||||
core_zero <= not ( alu_f(3)
|
||||
or alu_f(2)
|
||||
or alu_f(1)
|
||||
or alu_f(0));
|
||||
core_over <= alu_cout xor alu_over;
|
||||
|
||||
|
||||
-- ************************* ACCU control ************************
|
||||
|
||||
-- Compute of ACCU write enable.
|
||||
acc_wen <= (not i(6)) and ((not i(7)) or i(8));
|
||||
|
||||
-- ACCU shifter I/O.
|
||||
-- acc_i_up <= not core_acc_i_nup;
|
||||
-- acc_i_down <= not core_acc_i_ndown;
|
||||
-- core_acc_o_nup <= not acc_scout;
|
||||
-- core_acc_o_ndown <= not acc_q_down;
|
||||
|
||||
|
||||
-- ************************** RAM control ************************
|
||||
|
||||
|
||||
-- Compute of RAM write enable.
|
||||
ram_wri <= fonc_mode and (i(8) or i(7));
|
||||
|
||||
-- RAM and ACCU I/O plots controls.
|
||||
core_sh_right <= i(8) and (not i(7));
|
||||
core_sh_left <= i(8) and i(7) ;
|
||||
-- RAM shifter I/O.
|
||||
-- ram_i_up <= not core_ram_i_nup;
|
||||
-- ram_i_down <= not core_ram_i_ndown;
|
||||
-- core_ram_o_ndown <= not alu_f(0);
|
||||
-- core_ram_o_nup <= not alu_f(3);
|
||||
|
||||
oe <= not noe;
|
||||
|
||||
-- +
|
||||
|
||||
WITH a(3 downto 0) SELECT
|
||||
deca<= B"0000000000000001" WHEN X"0",
|
||||
B"0000000000000010" WHEN X"1",
|
||||
B"0000000000000100" WHEN X"2",
|
||||
B"0000000000001000" WHEN X"3",
|
||||
B"0000000000010000" WHEN X"4",
|
||||
B"0000000000100000" WHEN X"5",
|
||||
B"0000000001000000" WHEN X"6",
|
||||
B"0000000010000000" WHEN X"7",
|
||||
B"0000000100000000" WHEN X"8",
|
||||
B"0000001000000000" WHEN X"9",
|
||||
B"0000010000000000" WHEN X"A",
|
||||
B"0000100000000000" WHEN X"B",
|
||||
B"0001000000000000" WHEN X"C",
|
||||
B"0010000000000000" WHEN X"D",
|
||||
B"0100000000000000" WHEN X"E",
|
||||
B"1000000000000000" WHEN OTHERS;
|
||||
WITH b(3 downto 0) SELECT
|
||||
interm<= B"0000000000000001" WHEN X"0",
|
||||
B"0000000000000010" WHEN X"1",
|
||||
B"0000000000000100" WHEN X"2",
|
||||
B"0000000000001000" WHEN X"3",
|
||||
B"0000000000010000" WHEN X"4",
|
||||
B"0000000000100000" WHEN X"5",
|
||||
B"0000000001000000" WHEN X"6",
|
||||
B"0000000010000000" WHEN X"7",
|
||||
B"0000000100000000" WHEN X"8",
|
||||
B"0000001000000000" WHEN X"9",
|
||||
B"0000010000000000" WHEN X"A",
|
||||
B"0000100000000000" WHEN X"B",
|
||||
B"0001000000000000" WHEN X"C",
|
||||
B"0010000000000000" WHEN X"D",
|
||||
B"0100000000000000" WHEN X"E",
|
||||
B"1000000000000000" WHEN OTHERS;
|
||||
|
||||
decb <= interm;
|
||||
|
||||
WITH ram_wri SELECT
|
||||
decwb<= interm WHEN B"1",
|
||||
B"0000000000000000" WHEN OTHERS;
|
||||
|
||||
END behavior_data_flow;
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,387 @@
|
|||
|
||||
|
||||
# include <genlib.h>
|
||||
|
||||
|
||||
#define getbit(val,bit) (((val) >> (bit))%2)
|
||||
|
||||
|
||||
extern int main()
|
||||
{
|
||||
long i;
|
||||
|
||||
|
||||
/* Generate all the operators required for the register file. */
|
||||
GENLIB_MACRO (DPGEN_INV , "model_inv_x8", F_PLACE, 4, 8);
|
||||
GENLIB_MACRO (DPGEN_DFF , "model_dff" , F_PLACE, 4);
|
||||
GENLIB_MACRO (DPGEN_NBUSE, "model_nbuse" , F_PLACE, 4);
|
||||
|
||||
/* Generate all the operators required */
|
||||
|
||||
GENLIB_MACRO (DPGEN_MUX2 , "model_mux2", F_PLACE, 4, 2);
|
||||
GENLIB_MACRO (DPGEN_NAND2MASK, "model_nand2mask_0000", F_PLACE, 4,"0b0000");
|
||||
GENLIB_MACRO (DPGEN_XNOR2MASK, "model_xnor2mask_1111", F_PLACE, 4, "0b1111");
|
||||
GENLIB_MACRO (DPGEN_NAND2 , "model_nand2", F_PLACE, 4, 4); /* 1 ou 4 */
|
||||
GENLIB_MACRO (DPGEN_NOR2MASK , "model_nor2mask_1111", F_PLACE, 4,"0b1111");
|
||||
GENLIB_MACRO (DPGEN_NMUX2 , "model_nmux2", F_PLACE, 4,2);
|
||||
GENLIB_MACRO (DPGEN_INV , "model_inv", F_PLACE, 4,1);
|
||||
GENLIB_MACRO (DPGEN_NOR2 , "model_nor2", F_PLACE, 4, 4); /* 1 ou 4 */
|
||||
GENLIB_MACRO (DPGEN_XOR2 , "model_xor2", F_PLACE, 4, 4); /* 1 ou 4 */
|
||||
GENLIB_MACRO (DPGEN_XNOR2 , "model_xnor2", F_PLACE, 4, 4); /* 1 ou 4 */
|
||||
GENLIB_MACRO (DPGEN_DFFT , "model_dfft", F_PLACE, 4); /* 1 ou 4 */
|
||||
|
||||
|
||||
/* Netlist description. */
|
||||
GENLIB_DEF_LOFIG ("amd2901_dpt");
|
||||
|
||||
/* Command for selecting operands R and S.*/
|
||||
GENLIB_LOCON ("ops_mx[2:0]" , IN , "ops_mx[2:0]");
|
||||
GENLIB_LOCON ("opr_mx[1:0]" , IN , "opr_mx[1:0]");
|
||||
|
||||
/* ALU commands and auxiliary terminals. */
|
||||
GENLIB_LOCON ("alu_k[4:0]" , IN , "alu_k[4:0]");
|
||||
GENLIB_LOCON ("alu_cin" , IN , "alu_cin") ;
|
||||
GENLIB_LOCON ("alu_cout", OUT , "alu_cout") ;
|
||||
GENLIB_LOCON ("alu_over" , INOUT , "alu_over");
|
||||
|
||||
/* RAM, ACCU shifter commands and auxiliary terminals.*/
|
||||
GENLIB_LOCON ("ram_sh[1:0]" , IN , "ram_sh[1:0]") ;
|
||||
GENLIB_LOCON ("acc_sh[1:0]" , IN , "acc_sh[1:0]") ;
|
||||
|
||||
/* RAM shifter inputs.*/
|
||||
GENLIB_LOCON ("ram_i_up" , IN , "ram_i_up");
|
||||
GENLIB_LOCON ("ram_i_down" , IN , "ram_i_down");
|
||||
|
||||
/* ACCU shifter inputs.*/
|
||||
GENLIB_LOCON ("acc_i_up" , IN , "acc_i_up" ) ;
|
||||
GENLIB_LOCON ("acc_i_down" , IN , "acc_i_down") ;
|
||||
|
||||
/* ACCU shifter outputs ("acc_scout" is "acc_q_up").*/
|
||||
GENLIB_LOCON ("acc_q_down" , OUT , "acc_q_down");
|
||||
|
||||
/* Output multiplexer commnand (for X bus).*/
|
||||
GENLIB_LOCON ("out_mx" , IN , "out_mx");
|
||||
|
||||
/* ACCU controls terminals.*/
|
||||
GENLIB_LOCON ("acc_ck" , IN , "acc_ck" );
|
||||
GENLIB_LOCON ("acc_wen" , IN , "acc_wen" );
|
||||
GENLIB_LOCON ("acc_test" , IN , "acc_test" );
|
||||
GENLIB_LOCON ("acc_scin" , IN , "acc_scin") ; /* Scan-Path input.*/
|
||||
GENLIB_LOCON ("acc_scout", INOUT ,"acc_scout"); /* Scan-Path output.*/
|
||||
|
||||
/* Register file controls terminals.*/
|
||||
GENLIB_LOCON ("ram_ck[15:0]", IN ,"ram_ck[15:0]") ; /* Register clocks (ck) */
|
||||
GENLIB_LOCON ("b_w[15:0]" , IN , "b_w[15:0]") ; /* Write enable */
|
||||
GENLIB_LOCON ("a[15:0]" , IN , "a[15:0]") ; /* Register A address. */
|
||||
GENLIB_LOCON ("b[15:0]" , IN , "b[15:0]") ; /* Register B address. */
|
||||
|
||||
/* Data buses terminals.*/
|
||||
GENLIB_LOCON ("opr_d[3:0]" , IN ,"opr_d[3:0]");
|
||||
GENLIB_LOCON ("alu_f[3:0]" , INOUT ,"alu_f[3:0]");
|
||||
GENLIB_LOCON ("alu_np[3:0]" , OUT ,"alu_np[3:0]");
|
||||
GENLIB_LOCON ("alu_ng[3:0]" , OUT , "alu_ng[3:0]");
|
||||
GENLIB_LOCON ("out_x[3:0]" ,OUT , "out_x[3:0]");
|
||||
|
||||
/* Power supply connectors. */
|
||||
GENLIB_LOCON ("vdd", IN , "vdd");
|
||||
GENLIB_LOCON ("vss", IN , "vss");
|
||||
|
||||
|
||||
/* Register file description. */
|
||||
for (i = 0; i < 16; i++)
|
||||
{
|
||||
/* Register part. */
|
||||
GENLIB_LOINS ("model_dff", GENLIB_NAME("ram_reg%ld",i),
|
||||
GENLIB_ELM ("b_w", i),
|
||||
GENLIB_ELM ("ram_ck" , i),
|
||||
"ram_d[3:0]",
|
||||
GENLIB_NAME ("ram_q%ld[3:0]", i),
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
/* Tristate for A output. */
|
||||
GENLIB_LOINS ("model_nbuse", GENLIB_NAME ("ram_ntsa%ld",i),
|
||||
GENLIB_ELM ("a", i),
|
||||
GENLIB_NAME ("ram_q%ld[3:0]", i),
|
||||
"ram_nra[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
/* Tristate for B output. */
|
||||
GENLIB_LOINS ("model_nbuse", GENLIB_NAME("ram_ntsb%ld",i),
|
||||
GENLIB_ELM ("b", i),
|
||||
GENLIB_NAME ("ram_q%ld[3:0]", i),
|
||||
"ram_nrb[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
}
|
||||
|
||||
|
||||
/* Output drivers for A & B output. */
|
||||
GENLIB_LOINS ("model_inv_x8", "inv_ra",
|
||||
"ram_nra[3:0]",
|
||||
"ram_ra[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
GENLIB_LOINS ("model_inv_x8", "inv_rb",
|
||||
"ram_nrb[3:0]",
|
||||
"ram_rb[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
/* --------------------------------------------------------------
|
||||
* RAM shifter.
|
||||
*/
|
||||
|
||||
GENLIB_LOINS ("model_nmux2", "ram_nmux_0",
|
||||
"ram_sh[0]",
|
||||
"ram_i_up", "alu_f[3:1]", /* i1 */
|
||||
"alu_f[2:0]", "ram_i_down", /* i0 */
|
||||
"ram_nmux_0[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_inv", "ram_inv_1",
|
||||
"alu_f[3:0]", /* i2 */
|
||||
"ram_inv_1[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_nmux2", "ram_nmux_1",
|
||||
"ram_sh[1]",
|
||||
"ram_inv_1[3:0]",
|
||||
"ram_nmux_0[3:0]",
|
||||
"ram_d[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
|
||||
|
||||
/* *********************** Operand S ************************ */
|
||||
|
||||
GENLIB_LOINS ("model_nmux2", "ops_nmux_0",
|
||||
"ops_mx[0]",
|
||||
"ram_rb[3:0]", /* i1 */
|
||||
"acc_scout", "acc_q[2:1]", "acc_q_down", /* i0 */
|
||||
"ops_nmux_0[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_inv", "ops_inv_1",
|
||||
"ram_ra[3:0]", /* i2 */
|
||||
"ops_inv_1[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_nmux2", "ops_nmux_1",
|
||||
"ops_mx[1]",
|
||||
"ops_inv_1[3:0]",
|
||||
"ops_nmux_0[3:0]",
|
||||
"ops_it[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_nand2mask_0000", "ops_na2mask_0b0000",
|
||||
"ops_mx[2]" ,
|
||||
"ops_it[3:0]",
|
||||
"ops_ns[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
|
||||
/* *********************** Operand R ************************ */
|
||||
|
||||
|
||||
GENLIB_LOINS ("model_mux2", "opr_mux",
|
||||
"opr_mx[0]",
|
||||
"opr_d[3:0]", /* i1 */
|
||||
"ram_ra[3:0]", /* i0 */
|
||||
"opr_it[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_nand2mask_0000", "opr_na2mask_0b0000",
|
||||
"opr_mx[1]" ,
|
||||
"opr_it[3:0]",
|
||||
"opr_nr[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
/* *********************** ALU Description ****************** */
|
||||
|
||||
GENLIB_LOINS ("model_xnor2mask_1111", "alu_xr2_opnr",
|
||||
"alu_k[0]" ,
|
||||
"opr_nr[3:0]",
|
||||
"alu_xr[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_xnor2mask_1111", "alu_xr2_opns",
|
||||
"alu_k[1]" ,
|
||||
"ops_ns[3:0]",
|
||||
"alu_xs[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
|
||||
/* Compute of "generate". */
|
||||
GENLIB_LOINS ("model_nand2", "alu_na2_ng",
|
||||
"alu_xr[3:0]",
|
||||
"alu_xs[3:0]",
|
||||
"alu_ng[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
/* Compute of "propagate". */
|
||||
GENLIB_LOINS ("model_nor2", "alu_no2_np",
|
||||
"alu_xr[3:0]",
|
||||
"alu_xs[3:0]",
|
||||
"alu_np[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_inv", "alu_n1_p" ,
|
||||
"alu_np[3:0]",
|
||||
"alu_p[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
/* Compute of carry. */
|
||||
GENLIB_LOINS ("model_nand2", "alu_na2_npc" ,
|
||||
"alu_p[3:0]",
|
||||
"alu_over", "alu_carry[2:1]", "alu_cin",
|
||||
"alu_npc[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_nand2", "alu_na2_carry",
|
||||
"alu_ng[3:0]",
|
||||
"alu_npc[3:0]",
|
||||
"alu_cout", "alu_over", "alu_carry[2:1]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
/* Logical and arithmetical operators. */
|
||||
GENLIB_LOINS ("model_nor2mask_1111", "alu_no2_and",
|
||||
"alu_k[2]" ,
|
||||
"alu_ng[3:0]",
|
||||
"alu_r_and_s[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_nor2mask_1111", "alu_no2_or" ,
|
||||
"alu_k[3]" ,
|
||||
"alu_np[3:0]",
|
||||
"alu_r_or_s[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_nor2mask_1111", "alu_no2_add",
|
||||
"alu_k[4]" ,
|
||||
"alu_over", "alu_carry[2:1]", "alu_cin",
|
||||
"alu_r_add_s[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
/* Output. */
|
||||
GENLIB_LOINS ("model_xor2", "alu_nxr2_op",
|
||||
"alu_r_and_s[3:0]",
|
||||
"alu_r_or_s[3:0]",
|
||||
"alu_r_op_s[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_xnor2", "alu_nxr2_f" ,
|
||||
"alu_r_op_s[3:0]",
|
||||
"alu_r_add_s[3:0]",
|
||||
"alu_f[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
/* ******************** ACCU Description ******************** */
|
||||
|
||||
GENLIB_LOINS ("model_nmux2", "accu_nmux_0",
|
||||
"acc_sh[0]",
|
||||
"acc_i_up", "acc_scout", "acc_q[2:1]", /* i1 : down */
|
||||
"acc_q[2:1]", "acc_q_down", "acc_i_down", /* i0 : up */
|
||||
"accu_nmux_0[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_inv", "accu_inv_1",
|
||||
"alu_f[3:0]", /* i2: no */
|
||||
"accu_inv_1[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_nmux2", "accu_nmux_1",
|
||||
"acc_sh[1]",
|
||||
"accu_inv_1[3:0]",
|
||||
"accu_nmux_0[3:0]",
|
||||
"acc_d[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_dfft", "acc_reg",
|
||||
"acc_test" ,
|
||||
"acc_scin" ,
|
||||
"acc_wen",
|
||||
"acc_ck" ,
|
||||
"acc_d[3:0]",
|
||||
"acc_scout", "acc_q[2:1]", "acc_q_down",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
/* ******************* Output Multiplexer ******************* */
|
||||
|
||||
GENLIB_LOINS ("model_mux2", "out_mx",
|
||||
"out_mx" ,
|
||||
"ram_ra[3:0]", /* i1 */
|
||||
"alu_f[3:0]", /* i0 */
|
||||
"out_x[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
|
||||
/* End of netlist description. */
|
||||
GENLIB_SAVE_LOFIG ();
|
||||
|
||||
/* Partial placement description. */
|
||||
GENLIB_DEF_PHFIG ("amd2901_dpt");
|
||||
|
||||
|
||||
for (i = 0; i < 16; i++)
|
||||
{
|
||||
/* Register part. */
|
||||
if (!(i % 8)) {
|
||||
if (!i) {
|
||||
GENLIB_PLACE ("model_dff", GENLIB_NAME ("ram_reg%ld",i), NOSYM, 0, 0);
|
||||
} else {
|
||||
GENLIB_DEF_PHINS (GENLIB_NAME ("ram_reg%ld", i - 8));
|
||||
GENLIB_PLACE_TOP ("model_dff", GENLIB_NAME ("ram_reg%ld",i), NOSYM);
|
||||
}
|
||||
} else {
|
||||
GENLIB_PLACE_RIGHT ("model_dff", GENLIB_NAME ("ram_reg%ld",i), NOSYM);
|
||||
}
|
||||
|
||||
GENLIB_PLACE_RIGHT ("model_nbuse", GENLIB_NAME ("ram_ntsa%ld",i), NOSYM);
|
||||
GENLIB_PLACE_RIGHT ("model_nbuse", GENLIB_NAME ("ram_ntsb%ld",i), NOSYM);
|
||||
}
|
||||
|
||||
|
||||
GENLIB_PLACE("model_nmux2","ram_nmux_0",NOSYM, 500,700);
|
||||
GENLIB_PLACE_RIGHT ("model_nmux2", "ram_nmux_1", NOSYM);
|
||||
GENLIB_PLACE_RIGHT ("model_nmux2", "ops_nmux_0", NOSYM);
|
||||
GENLIB_PLACE_RIGHT ("model_nmux2", "ops_nmux_1", NOSYM);
|
||||
GENLIB_PLACE_RIGHT ("model_mux2", "opr_mux", NOSYM);
|
||||
#if 0
|
||||
GENLIB_PLACE_RIGHT ("model_inv", "ram_inv_1", NOSYM);
|
||||
|
||||
|
||||
/* *********************** Operand S ************************ */
|
||||
GENLIB_PLACE_RIGHT ("model_inv", "ops_inv_1", NOSYM);
|
||||
GENLIB_PLACE_RIGHT ("model_nand2mask_0000", "ops_na2mask_0b0000", NOSYM);
|
||||
|
||||
/* *********************** Operand R ************************ */
|
||||
GENLIB_PLACE_RIGHT ("model_nand2mask_0000", "opr_na2mask_0b0000", NOSYM);
|
||||
|
||||
/* *********************** ALU Description ****************** */
|
||||
GENLIB_PLACE_RIGHT ("model_xnor2mask_1111", "alu_xr2_opnr", NOSYM);
|
||||
GENLIB_PLACE_RIGHT ("model_xnor2mask_1111", "alu_xr2_opns", NOSYM);
|
||||
|
||||
/* Compute of "generate". */
|
||||
|
||||
/* Compute of "propagate". */
|
||||
|
||||
/* Compute of carry. */
|
||||
/* Logical and arithmetical operators. */
|
||||
/* Output. */
|
||||
GENLIB_PLACE_RIGHT ("model_xor2", "alu_nxr2_op", NOSYM);
|
||||
GENLIB_PLACE_RIGHT ("model_xnor2", "alu_nxr2_f" , NOSYM);
|
||||
|
||||
/* ******************** ACCU Description ******************** */
|
||||
#endif
|
||||
GENLIB_PLACE_RIGHT ("model_nmux2", "accu_nmux_0", NOSYM);
|
||||
GENLIB_PLACE_RIGHT ("model_nmux2", "accu_nmux_1", NOSYM);
|
||||
GENLIB_PLACE_RIGHT ("model_dfft", "acc_reg", NOSYM);
|
||||
|
||||
/* ******************* Output Multiplexer ******************* */
|
||||
GENLIB_PLACE_RIGHT ("model_mux2", "out_mx", NOSYM);
|
||||
|
||||
GENLIB_DEF_AB (0, 0, 0, 0);
|
||||
|
||||
|
||||
/* End of placement description. */
|
||||
GENLIB_SAVE_PHFIG ();
|
||||
|
||||
/* A good C program must always terminate by an "exit(0)". */
|
||||
exit(0);
|
||||
}
|
||||
|
|
@ -0,0 +1,566 @@
|
|||
ENTITY amd2901_dpt IS
|
||||
|
||||
PORT(
|
||||
-- Command for selecting operands R and S.
|
||||
ops_mx : in BIT_VECTOR(2 downto 0);
|
||||
opr_mx : in BIT_VECTOR(1 downto 0);
|
||||
|
||||
-- ALU commands and auxiliary terminals.
|
||||
alu_k : in BIT_VECTOR(4 downto 0);
|
||||
alu_cin : in BIT;
|
||||
alu_cout : out BIT;
|
||||
alu_over : inout BIT;
|
||||
|
||||
-- RAM, ACCU shifter commands and auxiliary terminals.
|
||||
ram_sh : in BIT_VECTOR(1 downto 0);
|
||||
acc_sh : in BIT_VECTOR(1 downto 0);
|
||||
-- RAM shifter inputs.
|
||||
ram_i_up : in BIT;
|
||||
ram_i_down : in BIT;
|
||||
-- ACCU shifter inputs.
|
||||
acc_i_up : in BIT;
|
||||
acc_i_down : in BIT;
|
||||
-- ACCU shifter outputs ("acc_scout" is "acc_q_up").
|
||||
acc_q_down : out BIT;
|
||||
|
||||
-- Output multiplexer commnand (for X bus).
|
||||
out_mx : in BIT;
|
||||
|
||||
-- ACCU controls terminals.
|
||||
acc_ck : in BIT;
|
||||
acc_wen : in BIT;
|
||||
acc_test : in BIT;
|
||||
acc_scin : in BIT; -- Scan-Path input.
|
||||
acc_scout : inout BIT; -- Scan-Path output.
|
||||
|
||||
-- Register file controls terminals.
|
||||
ram_ck : in BIT_VECTOR(15 downto 0) ; -- Register clocks (ck).
|
||||
b_w : in BIT_VECTOR(15 downto 0) ; -- Write enable
|
||||
a : in BIT_VECTOR(15 downto 0) ; -- Register A address.
|
||||
b : in BIT_VECTOR(15 downto 0) ; -- Register B address.
|
||||
|
||||
-- register_file_test : IN BIT_VECTOR(15 downto 0) ; -- register_file_test[15:0]
|
||||
-- register_file_scout : OUT BIT_VECTOR(15 downto 0) ; -- Scan path for ram
|
||||
-- register_file_scin : IN BIT_VECTOR(15 downto 0) ; -- Scan path for ram
|
||||
|
||||
-- Data buses terminals.
|
||||
opr_d : in BIT_VECTOR(3 downto 0);
|
||||
alu_f : inout BIT_VECTOR(3 downto 0);
|
||||
alu_np : out BIT_VECTOR(3 downto 0);
|
||||
alu_ng : out BIT_VECTOR(3 downto 0);
|
||||
out_x : out BIT_VECTOR(3 downto 0);
|
||||
|
||||
-- Power supply connectors.
|
||||
vdd : in BIT;
|
||||
vss : in BIT
|
||||
);
|
||||
|
||||
END amd2901_dpt;
|
||||
|
||||
|
||||
ARCHITECTURE behavior_data_flow OF amd2901_dpt IS
|
||||
|
||||
-- Internals bus.
|
||||
SIGNAL ops_ns : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL opr_nr : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL ram_d : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL acc_d : BIT_VECTOR(3 downto 0);
|
||||
|
||||
-- Internal registers.
|
||||
-- ACCU master/slave.
|
||||
-- SIGNAL acc_m_q : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL acc_s_q : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL acc_m_q : REG_VECTOR(3 downto 0) REGISTER;
|
||||
-- Internal ACCU clock signals.
|
||||
SIGNAL acc_wmd : BIT;
|
||||
SIGNAL acc_wmt : BIT;
|
||||
SIGNAL acc_ws : BIT;
|
||||
-- RAM SIGNALS
|
||||
SIGNAL ram_adra : BIT_VECTOR(15 DOWNTO 0);
|
||||
SIGNAL ram_adrb : BIT_VECTOR(15 DOWNTO 0);
|
||||
-- RAM masters.
|
||||
SIGNAL ram_m_r0 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r1 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r2 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r3 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r4 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r5 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r6 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r7 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r8 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r9 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r10 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r11 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r12 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r13 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r14 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r15 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
-- RAM slaves.
|
||||
SIGNAL ram_s_r0 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r1 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r2 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r3 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r4 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r5 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r6 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r7 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r8 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r9 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r10 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r11 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r12 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r13 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r14 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r15 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
-- Internal RAM clocks signals.
|
||||
-- Masters write enable.
|
||||
SIGNAL ram_wmd0 :BIT;
|
||||
SIGNAL ram_wmd1 :BIT;
|
||||
SIGNAL ram_wmd2 :BIT;
|
||||
SIGNAL ram_wmd3 :BIT;
|
||||
SIGNAL ram_wmd4 :BIT;
|
||||
SIGNAL ram_wmd5 :BIT;
|
||||
SIGNAL ram_wmd6 :BIT;
|
||||
SIGNAL ram_wmd7 :BIT;
|
||||
SIGNAL ram_wmd8 :BIT;
|
||||
SIGNAL ram_wmd9 :BIT;
|
||||
SIGNAL ram_wmd10 :BIT;
|
||||
SIGNAL ram_wmd11 :BIT;
|
||||
SIGNAL ram_wmd12 :BIT;
|
||||
SIGNAL ram_wmd13 :BIT;
|
||||
SIGNAL ram_wmd14 :BIT;
|
||||
SIGNAL ram_wmd15 :BIT;
|
||||
-- Slaves write enable.
|
||||
SIGNAL ram_ws0 :BIT;
|
||||
SIGNAL ram_ws1 :BIT;
|
||||
SIGNAL ram_ws2 :BIT;
|
||||
SIGNAL ram_ws3 :BIT;
|
||||
SIGNAL ram_ws4 :BIT;
|
||||
SIGNAL ram_ws5 :BIT;
|
||||
SIGNAL ram_ws6 :BIT;
|
||||
SIGNAL ram_ws7 :BIT;
|
||||
SIGNAL ram_ws8 :BIT;
|
||||
SIGNAL ram_ws9 :BIT;
|
||||
SIGNAL ram_ws10 :BIT;
|
||||
SIGNAL ram_ws11 :BIT;
|
||||
SIGNAL ram_ws12 :BIT;
|
||||
SIGNAL ram_ws13 :BIT;
|
||||
SIGNAL ram_ws14 :BIT;
|
||||
SIGNAL ram_ws15 :BIT;
|
||||
-- Output mux bus RA and RB.
|
||||
SIGNAL ram_ra : MUX_VECTOR(3 downto 0) BUS;
|
||||
SIGNAL ram_rb : MUX_VECTOR(3 downto 0) BUS;
|
||||
-- Internal ALU signals.
|
||||
SIGNAL alu_cry : BIT_VECTOR(4 downto 0);
|
||||
SIGNAL alu_s : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL alu_r : BIT_VECTOR(3 downto 0);
|
||||
|
||||
|
||||
|
||||
SIGNAL sel_acc : BIT_VECTOR(1 downto 0);
|
||||
SIGNAL sig_acc : BIT_VECTOR(3 downto 0);
|
||||
|
||||
SIGNAL sig_ram0 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram1 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram2 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram3 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram4 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram5 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram6 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram7 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram8 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram9 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram10 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram11 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram12 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram13 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram14 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram15 : BIT_VECTOR(3 downto 0);
|
||||
|
||||
SIGNAL ram_ck0 :BIT;
|
||||
SIGNAL ram_ck1 :BIT;
|
||||
SIGNAL ram_ck2 :BIT;
|
||||
SIGNAL ram_ck3 :BIT;
|
||||
SIGNAL ram_ck4 :BIT;
|
||||
SIGNAL ram_ck5 :BIT;
|
||||
SIGNAL ram_ck6 :BIT;
|
||||
SIGNAL ram_ck7 :BIT;
|
||||
SIGNAL ram_ck8 :BIT;
|
||||
SIGNAL ram_ck9 :BIT;
|
||||
SIGNAL ram_ck10 :BIT;
|
||||
SIGNAL ram_ck11 :BIT;
|
||||
SIGNAL ram_ck12 :BIT;
|
||||
SIGNAL ram_ck13 :BIT;
|
||||
SIGNAL ram_ck14 :BIT;
|
||||
SIGNAL ram_ck15 :BIT;
|
||||
|
||||
BEGIN
|
||||
|
||||
|
||||
-- ******************* RAM shifter description *******************
|
||||
|
||||
-- RAM shifter control code :
|
||||
-- 1) "00" : UP shift.
|
||||
-- 2) "01" : DOWN shift.
|
||||
-- 3) either "10" or "11" : NO shift.
|
||||
WITH ram_sh(1 downto 0) SELECT
|
||||
ram_d <= alu_f(2 downto 0)&ram_i_down WHEN B"00",
|
||||
ram_i_up&alu_f(3 downto 1) WHEN B"01",
|
||||
alu_f(3 downto 0) WHEN B"10"
|
||||
| B"11";
|
||||
|
||||
|
||||
-- ****************** ACCU shifter description *******************
|
||||
|
||||
acc_q_down <= acc_s_q(0);
|
||||
|
||||
-- ACCU shifter control code :
|
||||
-- 1) "00" : UP shift accu.
|
||||
-- 2) "01" : DOWN shift accu.
|
||||
-- 3) either "10" or "11" : write accu with no shift.
|
||||
WITH acc_sh(1 downto 0) SELECT
|
||||
acc_d <= acc_s_q(2 downto 0)&acc_i_down WHEN B"00",
|
||||
acc_i_up&acc_s_q(3 downto 1) WHEN B"01",
|
||||
alu_f(3 downto 0) WHEN B"10"
|
||||
| B"11";
|
||||
|
||||
|
||||
-- ****************** S multiplexer description ******************
|
||||
|
||||
WITH ops_mx(2 downto 0) SELECT
|
||||
ops_ns <= not acc_s_q WHEN B"000",
|
||||
not ram_rb WHEN B"001",
|
||||
not ram_ra WHEN B"010"
|
||||
| B"011",
|
||||
"1111" WHEN B"100"
|
||||
| B"101"
|
||||
| B"110"
|
||||
| B"111";
|
||||
|
||||
|
||||
-- ****************** R multiplexer description ******************
|
||||
|
||||
WITH opr_mx(1 downto 0) SELECT
|
||||
opr_nr <= not ram_ra WHEN B"00",
|
||||
not opr_d WHEN B"01",
|
||||
"1111" WHEN B"10"
|
||||
| B"11";
|
||||
|
||||
|
||||
-- ****************** X multiplexer description ******************
|
||||
|
||||
WITH out_mx SELECT
|
||||
out_x <= alu_f WHEN B"0",
|
||||
ram_ra WHEN B"1";
|
||||
|
||||
|
||||
-- *********************** ALU description ***********************
|
||||
|
||||
alu_cry(0) <= alu_cin;
|
||||
alu_cout <= alu_cry(4);
|
||||
alu_over <= alu_cry(3);
|
||||
|
||||
-- Inversion of R and S operands.
|
||||
alu_s <= not ops_ns WHEN alu_k(1) = '0' ELSE ops_ns;
|
||||
alu_r <= not opr_nr WHEN alu_k(0) = '0' ELSE opr_nr;
|
||||
|
||||
-- Compute of nP and nG.
|
||||
alu_np <= not (alu_s or alu_r);
|
||||
alu_ng <= not (alu_s and alu_r);
|
||||
|
||||
-- Arithmetic adder description.
|
||||
alu_cry(4 downto 1) <= (alu_s and alu_r )
|
||||
or (alu_s and alu_cry(3 downto 0))
|
||||
or (alu_cry(3 downto 0) and alu_r );
|
||||
|
||||
-- Select the ALU output.
|
||||
WITH alu_k(4 downto 2) SELECT
|
||||
alu_f <= alu_s xor alu_r xor alu_cry(3 downto 0) WHEN B"000",
|
||||
(alu_s or alu_r) xor alu_cry(3 downto 0) WHEN B"001",
|
||||
(alu_s and alu_r) xor alu_cry(3 downto 0) WHEN B"010",
|
||||
alu_cry(3 downto 0) WHEN B"011",
|
||||
not (alu_s xor alu_r) WHEN B"100",
|
||||
not (alu_s or alu_r) WHEN B"101",
|
||||
not (alu_s and alu_r) WHEN B"110",
|
||||
B"1111" WHEN B"111";
|
||||
|
||||
|
||||
|
||||
-- ********************** ACCU description ************************
|
||||
-- Modification tenant compte du front montant de l'horloge
|
||||
|
||||
acc_wmt <= acc_test;
|
||||
acc_wmd <= (not acc_test) and acc_wen;
|
||||
acc_ws <= not acc_ck;
|
||||
acc_scout <= acc_s_q(3);
|
||||
|
||||
sel_acc <= acc_wmt & acc_wmd ;
|
||||
|
||||
WITH sel_acc SELECT
|
||||
sig_acc <= acc_s_q(2 downto 0) & acc_scin WHEN B"10" , -- Mode chemin de tests
|
||||
acc_d WHEN B"01" , -- Mode normal
|
||||
acc_s_q WHEN OTHERS ; -- Reprise du registre
|
||||
|
||||
-- A chaque cycle, on ecrit dans acc_s_q
|
||||
|
||||
-- Echantillonnage lorsque ck=0 et memorisation sur front montant
|
||||
acc_ck:BLOCK(acc_ws = '1')
|
||||
BEGIN
|
||||
acc_m_q <= GUARDED sig_acc;
|
||||
END BLOCK acc_ck;
|
||||
|
||||
-- Slave register write.
|
||||
-- Echantillonnage lorsque ck=1 et memorisation sur front descendant
|
||||
acc_ws:BLOCK(acc_ck = '1')
|
||||
BEGIN
|
||||
acc_s_q <= GUARDED acc_m_q;
|
||||
END BLOCK acc_ws;
|
||||
|
||||
-- *********************** RAM description ***********************
|
||||
|
||||
-- Select B register.
|
||||
ram_adrb(0 ) <= b(0 ) ;
|
||||
ram_adrb(1 ) <= b(1 ) ;
|
||||
ram_adrb(2 ) <= b(2 ) ;
|
||||
ram_adrb(3 ) <= b(3 ) ;
|
||||
ram_adrb(4 ) <= b(4 ) ;
|
||||
ram_adrb(5 ) <= b(5 ) ;
|
||||
ram_adrb(6 ) <= b(6 ) ;
|
||||
ram_adrb(7 ) <= b(7 ) ;
|
||||
ram_adrb(8 ) <= b(8 ) ;
|
||||
ram_adrb(9 ) <= b(9 ) ;
|
||||
ram_adrb(10) <= b(10) ;
|
||||
ram_adrb(11) <= b(11) ;
|
||||
ram_adrb(12) <= b(12) ;
|
||||
ram_adrb(13) <= b(13) ;
|
||||
ram_adrb(14) <= b(14) ;
|
||||
ram_adrb(15) <= b(15) ;
|
||||
|
||||
-- Select A register.
|
||||
ram_adra(0 ) <= a(0 ) ;
|
||||
ram_adra(1 ) <= a(1 ) ;
|
||||
ram_adra(2 ) <= a(2 ) ;
|
||||
ram_adra(3 ) <= a(3 ) ;
|
||||
ram_adra(4 ) <= a(4 ) ;
|
||||
ram_adra(5 ) <= a(5 ) ;
|
||||
ram_adra(6 ) <= a(6 ) ;
|
||||
ram_adra(7 ) <= a(7 ) ;
|
||||
ram_adra(8 ) <= a(8 ) ;
|
||||
ram_adra(9 ) <= a(9 ) ;
|
||||
ram_adra(10) <= a(10) ;
|
||||
ram_adra(11) <= a(11) ;
|
||||
ram_adra(12) <= a(12) ;
|
||||
ram_adra(13) <= a(13) ;
|
||||
ram_adra(14) <= a(14) ;
|
||||
ram_adra(15) <= a(15) ;
|
||||
|
||||
|
||||
-- Write master enable signals for b
|
||||
ram_wmd0 <= b_w(0 );
|
||||
ram_wmd1 <= b_w(1 );
|
||||
ram_wmd2 <= b_w(2 );
|
||||
ram_wmd3 <= b_w(3 );
|
||||
ram_wmd4 <= b_w(4 );
|
||||
ram_wmd5 <= b_w(5 );
|
||||
ram_wmd6 <= b_w(6 );
|
||||
ram_wmd7 <= b_w(7 );
|
||||
ram_wmd8 <= b_w(8 );
|
||||
ram_wmd9 <= b_w(9 );
|
||||
ram_wmd10 <= b_w(10);
|
||||
ram_wmd11 <= b_w(11);
|
||||
ram_wmd12 <= b_w(12);
|
||||
ram_wmd13 <= b_w(13);
|
||||
ram_wmd14 <= b_w(14);
|
||||
ram_wmd15 <= b_w(15);
|
||||
|
||||
-- Write slave enable signals.
|
||||
ram_ws0 <= not ram_ck(0 ) ;
|
||||
ram_ws1 <= not ram_ck(1 ) ;
|
||||
ram_ws2 <= not ram_ck(2 ) ;
|
||||
ram_ws3 <= not ram_ck(3 ) ;
|
||||
ram_ws4 <= not ram_ck(4 ) ;
|
||||
ram_ws5 <= not ram_ck(5 ) ;
|
||||
ram_ws6 <= not ram_ck(6 ) ;
|
||||
ram_ws7 <= not ram_ck(7 ) ;
|
||||
ram_ws8 <= not ram_ck(8 ) ;
|
||||
ram_ws9 <= not ram_ck(9 ) ;
|
||||
ram_ws10 <= not ram_ck(10) ;
|
||||
ram_ws11 <= not ram_ck(11) ;
|
||||
ram_ws12 <= not ram_ck(12) ;
|
||||
ram_ws13 <= not ram_ck(13) ;
|
||||
ram_ws14 <= not ram_ck(14) ;
|
||||
ram_ws15 <= not ram_ck(15) ;
|
||||
|
||||
ram_ck0 <= ram_ck(0 ) ;
|
||||
ram_ck1 <= ram_ck(1 ) ;
|
||||
ram_ck2 <= ram_ck(2 ) ;
|
||||
ram_ck3 <= ram_ck(3 ) ;
|
||||
ram_ck4 <= ram_ck(4 ) ;
|
||||
ram_ck5 <= ram_ck(5 ) ;
|
||||
ram_ck6 <= ram_ck(6 ) ;
|
||||
ram_ck7 <= ram_ck(7 ) ;
|
||||
ram_ck8 <= ram_ck(8 ) ;
|
||||
ram_ck9 <= ram_ck(9 ) ;
|
||||
ram_ck10 <= ram_ck(10) ;
|
||||
ram_ck11 <= ram_ck(11) ;
|
||||
ram_ck12 <= ram_ck(12) ;
|
||||
ram_ck13 <= ram_ck(13) ;
|
||||
ram_ck14 <= ram_ck(14) ;
|
||||
ram_ck15 <= ram_ck(15) ;
|
||||
|
||||
|
||||
WITH ram_wmd0 SELECT
|
||||
sig_ram0 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r0 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd1 SELECT
|
||||
sig_ram1 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r1 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd2 SELECT
|
||||
sig_ram2 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r2 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd3 SELECT
|
||||
sig_ram3 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r3 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd4 SELECT
|
||||
sig_ram4 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r4 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd5 SELECT
|
||||
sig_ram5 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r5 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd6 SELECT
|
||||
sig_ram6 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r6 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd7 SELECT
|
||||
sig_ram7 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r7 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd8 SELECT
|
||||
sig_ram8 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r8 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd9 SELECT
|
||||
sig_ram9 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r9 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd10 SELECT
|
||||
sig_ram10 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r10 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd11 SELECT
|
||||
sig_ram11 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r11 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd12 SELECT
|
||||
sig_ram12 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r12 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd13 SELECT
|
||||
sig_ram13 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r13 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd14 SELECT
|
||||
sig_ram14 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r14 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd15 SELECT
|
||||
sig_ram15 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r15 WHEN OTHERS ;
|
||||
|
||||
|
||||
-- Write registers description.
|
||||
|
||||
-- Echantillonnage lorsque ck=0 et memorisation sur front montant
|
||||
wm0 :BLOCK(ram_ws0 = '1') BEGIN ram_m_r0 <= GUARDED sig_ram0 ; END BLOCK wm0 ;
|
||||
wm1 :BLOCK(ram_ws1 = '1') BEGIN ram_m_r1 <= GUARDED sig_ram1 ; END BLOCK wm1 ;
|
||||
wm2 :BLOCK(ram_ws2 = '1') BEGIN ram_m_r2 <= GUARDED sig_ram2 ; END BLOCK wm2 ;
|
||||
wm3 :BLOCK(ram_ws3 = '1') BEGIN ram_m_r3 <= GUARDED sig_ram3 ; END BLOCK wm3 ;
|
||||
wm4 :BLOCK(ram_ws4 = '1') BEGIN ram_m_r4 <= GUARDED sig_ram4 ; END BLOCK wm4 ;
|
||||
wm5 :BLOCK(ram_ws5 = '1') BEGIN ram_m_r5 <= GUARDED sig_ram5 ; END BLOCK wm5 ;
|
||||
wm6 :BLOCK(ram_ws6 = '1') BEGIN ram_m_r6 <= GUARDED sig_ram6 ; END BLOCK wm6 ;
|
||||
wm7 :BLOCK(ram_ws7 = '1') BEGIN ram_m_r7 <= GUARDED sig_ram7 ; END BLOCK wm7 ;
|
||||
wm8 :BLOCK(ram_ws8 = '1') BEGIN ram_m_r8 <= GUARDED sig_ram8 ; END BLOCK wm8 ;
|
||||
wm9 :BLOCK(ram_ws9 = '1') BEGIN ram_m_r9 <= GUARDED sig_ram9 ; END BLOCK wm9 ;
|
||||
wm10:BLOCK(ram_ws10 = '1') BEGIN ram_m_r10 <= GUARDED sig_ram10 ; END BLOCK wm10;
|
||||
wm11:BLOCK(ram_ws11 = '1') BEGIN ram_m_r11 <= GUARDED sig_ram11 ; END BLOCK wm11;
|
||||
wm12:BLOCK(ram_ws12 = '1') BEGIN ram_m_r12 <= GUARDED sig_ram12 ; END BLOCK wm12;
|
||||
wm13:BLOCK(ram_ws13 = '1') BEGIN ram_m_r13 <= GUARDED sig_ram13 ; END BLOCK wm13;
|
||||
wm14:BLOCK(ram_ws14 = '1') BEGIN ram_m_r14 <= GUARDED sig_ram14 ; END BLOCK wm14;
|
||||
wm15:BLOCK(ram_ws15 = '1') BEGIN ram_m_r15 <= GUARDED sig_ram15 ; END BLOCK wm15;
|
||||
|
||||
-- Write slave registers description.
|
||||
-- Echantillonnage lorsque ck=1 et memorisation sur front descendant
|
||||
ws0 :BLOCK(ram_ck0 = '1') BEGIN ram_s_r0 <= GUARDED ram_m_r0 ; END BLOCK ws0 ;
|
||||
ws1 :BLOCK(ram_ck1 = '1') BEGIN ram_s_r1 <= GUARDED ram_m_r1 ; END BLOCK ws1 ;
|
||||
ws2 :BLOCK(ram_ck2 = '1') BEGIN ram_s_r2 <= GUARDED ram_m_r2 ; END BLOCK ws2 ;
|
||||
ws3 :BLOCK(ram_ck3 = '1') BEGIN ram_s_r3 <= GUARDED ram_m_r3 ; END BLOCK ws3 ;
|
||||
ws4 :BLOCK(ram_ck4 = '1') BEGIN ram_s_r4 <= GUARDED ram_m_r4 ; END BLOCK ws4 ;
|
||||
ws5 :BLOCK(ram_ck5 = '1') BEGIN ram_s_r5 <= GUARDED ram_m_r5 ; END BLOCK ws5 ;
|
||||
ws6 :BLOCK(ram_ck6 = '1') BEGIN ram_s_r6 <= GUARDED ram_m_r6 ; END BLOCK ws6 ;
|
||||
ws7 :BLOCK(ram_ck7 = '1') BEGIN ram_s_r7 <= GUARDED ram_m_r7 ; END BLOCK ws7 ;
|
||||
ws8 :BLOCK(ram_ck8 = '1') BEGIN ram_s_r8 <= GUARDED ram_m_r8 ; END BLOCK ws8 ;
|
||||
ws9 :BLOCK(ram_ck9 = '1') BEGIN ram_s_r9 <= GUARDED ram_m_r9 ; END BLOCK ws9 ;
|
||||
ws10:BLOCK(ram_ck10 = '1') BEGIN ram_s_r10 <= GUARDED ram_m_r10; END BLOCK ws10;
|
||||
ws11:BLOCK(ram_ck11 = '1') BEGIN ram_s_r11 <= GUARDED ram_m_r11; END BLOCK ws11;
|
||||
ws12:BLOCK(ram_ck12 = '1') BEGIN ram_s_r12 <= GUARDED ram_m_r12; END BLOCK ws12;
|
||||
ws13:BLOCK(ram_ck13 = '1') BEGIN ram_s_r13 <= GUARDED ram_m_r13; END BLOCK ws13;
|
||||
ws14:BLOCK(ram_ck14 = '1') BEGIN ram_s_r14 <= GUARDED ram_m_r14; END BLOCK ws14;
|
||||
ws15:BLOCK(ram_ck15 = '1') BEGIN ram_s_r15 <= GUARDED ram_m_r15; END BLOCK ws15;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
-- Select register to write on tristate bus RA.
|
||||
wa0 :BLOCK(ram_adra(0 )) BEGIN ram_ra <= GUARDED ram_s_r0 ; END BLOCK wa0 ;
|
||||
wa1 :BLOCK(ram_adra(1 )) BEGIN ram_ra <= GUARDED ram_s_r1 ; END BLOCK wa1 ;
|
||||
wa2 :BLOCK(ram_adra(2 )) BEGIN ram_ra <= GUARDED ram_s_r2 ; END BLOCK wa2 ;
|
||||
wa3 :BLOCK(ram_adra(3 )) BEGIN ram_ra <= GUARDED ram_s_r3 ; END BLOCK wa3 ;
|
||||
wa4 :BLOCK(ram_adra(4 )) BEGIN ram_ra <= GUARDED ram_s_r4 ; END BLOCK wa4 ;
|
||||
wa5 :BLOCK(ram_adra(5 )) BEGIN ram_ra <= GUARDED ram_s_r5 ; END BLOCK wa5 ;
|
||||
wa6 :BLOCK(ram_adra(6 )) BEGIN ram_ra <= GUARDED ram_s_r6 ; END BLOCK wa6 ;
|
||||
wa7 :BLOCK(ram_adra(7 )) BEGIN ram_ra <= GUARDED ram_s_r7 ; END BLOCK wa7 ;
|
||||
wa8 :BLOCK(ram_adra(8 )) BEGIN ram_ra <= GUARDED ram_s_r8 ; END BLOCK wa8 ;
|
||||
wa9 :BLOCK(ram_adra(9 )) BEGIN ram_ra <= GUARDED ram_s_r9 ; END BLOCK wa9 ;
|
||||
wa10:BLOCK(ram_adra(10)) BEGIN ram_ra <= GUARDED ram_s_r10; END BLOCK wa10;
|
||||
wa11:BLOCK(ram_adra(11)) BEGIN ram_ra <= GUARDED ram_s_r11; END BLOCK wa11;
|
||||
wa12:BLOCK(ram_adra(12)) BEGIN ram_ra <= GUARDED ram_s_r12; END BLOCK wa12;
|
||||
wa13:BLOCK(ram_adra(13)) BEGIN ram_ra <= GUARDED ram_s_r13; END BLOCK wa13;
|
||||
wa14:BLOCK(ram_adra(14)) BEGIN ram_ra <= GUARDED ram_s_r14; END BLOCK wa14;
|
||||
wa15:BLOCK(ram_adra(15)) BEGIN ram_ra <= GUARDED ram_s_r15; END BLOCK wa15;
|
||||
|
||||
-- Select register to write on tristate bus RB.
|
||||
wb0 :BLOCK(ram_adrb(0 )) BEGIN ram_rb <= GUARDED ram_s_r0 ; END BLOCK wb0 ;
|
||||
wb1 :BLOCK(ram_adrb(1 )) BEGIN ram_rb <= GUARDED ram_s_r1 ; END BLOCK wb1 ;
|
||||
wb2 :BLOCK(ram_adrb(2 )) BEGIN ram_rb <= GUARDED ram_s_r2 ; END BLOCK wb2 ;
|
||||
wb3 :BLOCK(ram_adrb(3 )) BEGIN ram_rb <= GUARDED ram_s_r3 ; END BLOCK wb3 ;
|
||||
wb4 :BLOCK(ram_adrb(4 )) BEGIN ram_rb <= GUARDED ram_s_r4 ; END BLOCK wb4 ;
|
||||
wb5 :BLOCK(ram_adrb(5 )) BEGIN ram_rb <= GUARDED ram_s_r5 ; END BLOCK wb5 ;
|
||||
wb6 :BLOCK(ram_adrb(6 )) BEGIN ram_rb <= GUARDED ram_s_r6 ; END BLOCK wb6 ;
|
||||
wb7 :BLOCK(ram_adrb(7 )) BEGIN ram_rb <= GUARDED ram_s_r7 ; END BLOCK wb7 ;
|
||||
wb8 :BLOCK(ram_adrb(8 )) BEGIN ram_rb <= GUARDED ram_s_r8 ; END BLOCK wb8 ;
|
||||
wb9 :BLOCK(ram_adrb(9 )) BEGIN ram_rb <= GUARDED ram_s_r9 ; END BLOCK wb9 ;
|
||||
wb10:BLOCK(ram_adrb(10)) BEGIN ram_rb <= GUARDED ram_s_r10; END BLOCK wb10;
|
||||
wb11:BLOCK(ram_adrb(11)) BEGIN ram_rb <= GUARDED ram_s_r11; END BLOCK wb11;
|
||||
wb12:BLOCK(ram_adrb(12)) BEGIN ram_rb <= GUARDED ram_s_r12; END BLOCK wb12;
|
||||
wb13:BLOCK(ram_adrb(13)) BEGIN ram_rb <= GUARDED ram_s_r13; END BLOCK wb13;
|
||||
wb14:BLOCK(ram_adrb(14)) BEGIN ram_rb <= GUARDED ram_s_r14; END BLOCK wb14;
|
||||
wb15:BLOCK(ram_adrb(15)) BEGIN ram_rb <= GUARDED ram_s_r15; END BLOCK wb15;
|
||||
|
||||
|
||||
|
||||
-- ********************* Power supply check **********************
|
||||
|
||||
ASSERT(vss = '0')
|
||||
REPORT "Power supply VSS badly connected." SEVERITY WARNING;
|
||||
ASSERT(vdd = '1')
|
||||
REPORT "Power supply VDD badly connected." SEVERITY WARNING;
|
||||
|
||||
|
||||
END behavior_data_flow;
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,593 @@
|
|||
|
||||
-- description generated by Pat driver
|
||||
|
||||
-- date : Tue Mar 4 09:45:36 2003
|
||||
-- revision : v109
|
||||
|
||||
-- sequence : pattern
|
||||
|
||||
-- input / output list :
|
||||
in a (3 downto 0) X;;
|
||||
in b (3 downto 0) X;;
|
||||
in d (3 downto 0) X;;
|
||||
in i (8 downto 0) O;;
|
||||
in fonc B;;
|
||||
in test B;;
|
||||
in scin B;;
|
||||
in noe B;;
|
||||
in ck B;;
|
||||
in cin B;;
|
||||
inout r0 B;;
|
||||
inout r3 B;;
|
||||
inout q0 B;;
|
||||
inout q3 B;;
|
||||
out y (3 downto 0) X;;
|
||||
out zero B;;
|
||||
out signe B;;
|
||||
out scout B;;
|
||||
out ovr B;;
|
||||
out np B;;
|
||||
out ng B;;
|
||||
out cout B;;
|
||||
in vdd B;;
|
||||
in vss B;;
|
||||
in vdde B;;
|
||||
in vsse B;;
|
||||
|
||||
begin
|
||||
|
||||
-- Pattern description :
|
||||
|
||||
-- a b d i f t s n c c r r q q y z s s o n n c v v v v
|
||||
-- o e c o k i 0 3 0 3 e i c v p g o d s d s
|
||||
-- n s i e n r g o r u d s d s
|
||||
-- c t n o n u t e e
|
||||
-- e t
|
||||
|
||||
|
||||
-- Beware : unprocessed patterns
|
||||
|
||||
< 0 ps> : 0 0 a 007 1 0 0 0 0 0 ?* ?* ?* ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 100 ps> : 0 0 a 007 1 0 0 0 1 0 ?* ?* ?* ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 200 ps> : 0 0 5 007 1 0 0 0 0 0 ?* ?* ?* ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 300 ps> : 0 0 5 007 1 0 0 0 1 0 ?* ?* ?* ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 400 ps> : 0 0 a 032 1 0 0 0 0 0 ?* ?* ?* ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 500 ps> : 0 0 a 032 1 0 0 0 1 0 ?* ?* ?* ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 600 ps> : 0 0 a 462 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 700 ps> : 0 0 a 462 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 800 ps> : 0 1 a 462 1 0 0 0 0 0 ?* 0 ?* 0 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 900 ps> : 0 1 a 462 1 0 0 0 1 0 ?* 0 ?* 0 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 1000 ps> : 0 2 a 462 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 1100 ps> : 0 2 a 462 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 1200 ps> : 0 3 a 462 1 0 0 0 0 0 ?* 0 ?* 0 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 1300 ps> : 0 3 a 462 1 0 0 0 1 0 ?* 0 ?* 0 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 1400 ps> : 0 4 a 462 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 1500 ps> : 0 4 a 462 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 1600 ps> : 0 5 a 462 1 0 0 0 0 0 ?* 0 ?* 0 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 1700 ps> : 0 5 a 462 1 0 0 0 1 0 ?* 0 ?* 0 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 1800 ps> : 0 6 a 462 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 1900 ps> : 0 6 a 462 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 2000 ps> : 0 7 a 462 1 0 0 0 0 0 ?* 0 ?* 0 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 2100 ps> : 0 7 a 462 1 0 0 0 1 0 ?* 0 ?* 0 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 2200 ps> : 0 8 a 462 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 2300 ps> : 0 8 a 462 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 2400 ps> : 0 0 a 163 1 0 0 0 0 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 2500 ps> : 0 0 a 163 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 2600 ps> : 0 1 a 163 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 2700 ps> : 0 1 a 163 1 0 0 0 1 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 2800 ps> : 0 2 a 163 1 0 0 0 0 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 2900 ps> : 0 2 a 163 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 3000 ps> : 0 3 a 163 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 3100 ps> : 0 3 a 163 1 0 0 0 1 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 3200 ps> : 0 4 a 163 1 0 0 0 0 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 3300 ps> : 0 4 a 163 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 3400 ps> : 0 5 a 163 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 3500 ps> : 0 5 a 163 1 0 0 0 1 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 3600 ps> : 0 6 a 163 1 0 0 0 0 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 3700 ps> : 0 6 a 163 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 3800 ps> : 0 7 a 163 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 3900 ps> : 0 7 a 163 1 0 0 0 1 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 4000 ps> : 0 7 a 007 1 0 0 0 0 0 ?* ?* ?* ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 4100 ps> : 0 7 a 007 1 0 0 0 1 0 ?* ?* ?* ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 4200 ps> : 0 7 5 007 1 0 0 0 0 0 ?* ?* ?* ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 4300 ps> : 0 7 5 007 1 0 0 0 1 0 ?* ?* ?* ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 4400 ps> : 0 7 a 032 1 0 0 0 0 0 ?* ?* ?* ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 4500 ps> : 0 7 a 032 1 0 0 0 1 0 ?* ?* ?* ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 4600 ps> : 0 0 a 662 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 4700 ps> : 0 0 a 662 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 4800 ps> : 0 1 a 662 1 0 0 0 0 0 1 ?* 1 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 4900 ps> : 0 1 a 662 1 0 0 0 1 0 1 ?* 1 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 5000 ps> : 0 2 a 662 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 5100 ps> : 0 2 a 662 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 5200 ps> : 0 3 a 662 1 0 0 0 0 0 1 ?* 1 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 5300 ps> : 0 3 a 662 1 0 0 0 1 0 1 ?* 1 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 5400 ps> : 0 4 a 662 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 5500 ps> : 0 4 a 662 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 5600 ps> : 0 5 a 662 1 0 0 0 0 0 1 ?* 1 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 5700 ps> : 0 5 a 662 1 0 0 0 1 0 1 ?* 1 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 5800 ps> : 0 6 a 662 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 5900 ps> : 0 6 a 662 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 6000 ps> : 0 7 a 662 1 0 0 0 0 0 1 ?* 1 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 6100 ps> : 0 7 a 662 1 0 0 0 1 0 1 ?* 1 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 6200 ps> : 0 8 a 662 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 6300 ps> : 0 8 a 662 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 6400 ps> : 0 0 a 163 1 0 0 0 0 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 6500 ps> : 0 0 a 163 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 6600 ps> : 0 1 a 163 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 6700 ps> : 0 1 a 163 1 0 0 0 1 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 6800 ps> : 0 2 a 163 1 0 0 0 0 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 6900 ps> : 0 2 a 163 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 7000 ps> : 0 3 a 163 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 7100 ps> : 0 3 a 163 1 0 0 0 1 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 7200 ps> : 0 4 a 163 1 0 0 0 0 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 7300 ps> : 0 4 a 163 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 7400 ps> : 0 5 a 163 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 7500 ps> : 0 5 a 163 1 0 0 0 1 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 7600 ps> : 0 6 a 163 1 0 0 0 0 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 7700 ps> : 0 6 a 163 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 7800 ps> : 0 7 a 163 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 7900 ps> : 0 7 a 163 1 0 0 0 1 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 8000 ps> : 0 0 0 337 1 0 0 0 0 0 0 ?* 0 ?* ?0 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 8100 ps> : 0 0 0 337 1 0 0 0 1 0 0 ?* 0 ?* ?0 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 8200 ps> : 1 1 1 337 1 0 0 0 0 0 0 ?* 0 ?* ?1 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 8300 ps> : 1 1 1 337 1 0 0 0 1 0 0 ?* 0 ?* ?1 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 8400 ps> : 2 2 2 337 1 0 0 0 0 0 0 ?* 0 ?* ?2 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 8500 ps> : 2 2 2 337 1 0 0 0 1 0 0 ?* 0 ?* ?2 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 8600 ps> : 3 3 3 337 1 0 0 0 0 0 0 ?* 0 ?* ?3 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 8700 ps> : 3 3 3 337 1 0 0 0 1 0 0 ?* 0 ?* ?3 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 8800 ps> : 4 4 4 337 1 0 0 0 0 0 0 ?* 0 ?* ?4 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 8900 ps> : 4 4 4 337 1 0 0 0 1 0 0 ?* 0 ?* ?4 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 9000 ps> : 5 5 5 337 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 9100 ps> : 5 5 5 337 1 0 0 0 1 0 0 ?* 0 ?* ?5 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 9200 ps> : 6 6 6 337 1 0 0 0 0 0 0 ?* 0 ?* ?6 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 9300 ps> : 6 6 6 337 1 0 0 0 1 0 0 ?* 0 ?* ?6 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 9400 ps> : 7 7 7 337 1 0 0 0 0 0 0 ?* 0 ?* ?7 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 9500 ps> : 7 7 7 337 1 0 0 0 1 0 0 ?* 0 ?* ?7 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 9600 ps> : 8 8 8 337 1 0 0 0 0 0 0 ?* 0 ?* ?8 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 9700 ps> : 8 8 8 337 1 0 0 0 1 0 0 ?* 0 ?* ?8 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 9800 ps> : 9 9 9 337 1 0 0 0 0 0 0 ?* 0 ?* ?9 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 9900 ps> : 9 9 9 337 1 0 0 0 1 0 0 ?* 0 ?* ?9 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 10000 ps> : a a a 337 1 0 0 0 0 0 0 ?* 0 ?* ?a ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 10100 ps> : a a a 337 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 10200 ps> : b b b 337 1 0 0 0 0 0 0 ?* 0 ?* ?b ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 10300 ps> : b b b 337 1 0 0 0 1 0 0 ?* 0 ?* ?b ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 10400 ps> : c c c 337 1 0 0 0 0 0 0 ?* 0 ?* ?c ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 10500 ps> : c c c 337 1 0 0 0 1 0 0 ?* 0 ?* ?c ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 10600 ps> : d d d 337 1 0 0 0 0 0 0 ?* 0 ?* ?d ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 10700 ps> : d d d 337 1 0 0 0 1 0 0 ?* 0 ?* ?d ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 10800 ps> : e e e 337 1 0 0 0 0 0 0 ?* 0 ?* ?e ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 10900 ps> : e e e 337 1 0 0 0 1 0 0 ?* 0 ?* ?e ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 11000 ps> : f f f 337 1 0 0 0 0 0 0 ?* 0 ?* ?f ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 11100 ps> : f f f 337 1 0 0 0 1 0 0 ?* 0 ?* ?f ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 11200 ps> : f f f 337 1 0 0 0 0 0 0 ?* 0 ?* ?f ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 11300 ps> : f f f 337 1 0 0 0 1 0 0 ?* 0 ?* ?f ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 11400 ps> : 0 0 0 137 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 11500 ps> : 0 0 0 137 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 11600 ps> : 0 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?0 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 11700 ps> : 0 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?0 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 11800 ps> : 1 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?1 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 11900 ps> : 1 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?1 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 12000 ps> : 2 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?2 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 12100 ps> : 2 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?2 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 12200 ps> : 3 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?3 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 12300 ps> : 3 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?3 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 12400 ps> : 4 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?4 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 12500 ps> : 4 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?4 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 12600 ps> : 5 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 12700 ps> : 5 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?5 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 12800 ps> : 6 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?6 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 12900 ps> : 6 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?6 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 13000 ps> : 7 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?7 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 13100 ps> : 7 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?7 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 13200 ps> : 8 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?8 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 13300 ps> : 8 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?8 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 13400 ps> : 9 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?9 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 13500 ps> : 9 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?9 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 13600 ps> : a 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?a ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 13700 ps> : a 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 13800 ps> : b 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?b ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 13900 ps> : b 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?b ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 14000 ps> : c 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?c ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 14100 ps> : c 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?c ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 14200 ps> : d 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?d ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 14300 ps> : d 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?d ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 14400 ps> : e 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?e ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 14500 ps> : e 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?e ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 14600 ps> : f 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?f ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 14700 ps> : f 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 14800 ps> : f 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 14900 ps> : f 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 15000 ps> : 0 0 0 137 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 15100 ps> : 0 0 0 137 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 15200 ps> : 0 0 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 15300 ps> : 0 0 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?0 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 15400 ps> : 0 0 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?0 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 15500 ps> : 0 0 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 15600 ps> : 0 1 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 15700 ps> : 0 1 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?1 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 15800 ps> : 0 1 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?1 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 15900 ps> : 0 1 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 16000 ps> : 0 2 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 16100 ps> : 0 2 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?2 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 16200 ps> : 0 2 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?2 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 16300 ps> : 0 2 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 16400 ps> : 0 3 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 16500 ps> : 0 3 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?3 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 16600 ps> : 0 3 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?3 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 16700 ps> : 0 3 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 16800 ps> : 0 4 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 16900 ps> : 0 4 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?4 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 17000 ps> : 0 4 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?4 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 17100 ps> : 0 4 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 17200 ps> : 0 5 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 17300 ps> : 0 5 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?5 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 17400 ps> : 0 5 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 17500 ps> : 0 5 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 17600 ps> : 0 6 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 17700 ps> : 0 6 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?6 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 17800 ps> : 0 6 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?6 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 17900 ps> : 0 6 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 18000 ps> : 0 7 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 18100 ps> : 0 7 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?7 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 18200 ps> : 0 7 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?7 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 18300 ps> : 0 7 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 18400 ps> : 0 8 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 18500 ps> : 0 8 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?8 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 18600 ps> : 0 8 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?8 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 18700 ps> : 0 8 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 18800 ps> : 0 9 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 18900 ps> : 0 9 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?9 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 19000 ps> : 0 9 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?9 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 19100 ps> : 0 9 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 19200 ps> : 0 a 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 19300 ps> : 0 a 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 19400 ps> : 0 a 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?a ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 19500 ps> : 0 a 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 19600 ps> : 0 b 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 19700 ps> : 0 b 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?b ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 19800 ps> : 0 b 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?b ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 19900 ps> : 0 b 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 20000 ps> : 0 c 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 20100 ps> : 0 c 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?c ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 20200 ps> : 0 c 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?c ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 20300 ps> : 0 c 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 20400 ps> : 0 d 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 20500 ps> : 0 d 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?d ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 20600 ps> : 0 d 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?d ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 20700 ps> : 0 d 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 20800 ps> : 0 e 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 20900 ps> : 0 e 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?e ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 21000 ps> : 0 e 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?e ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 21100 ps> : 0 e 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 21200 ps> : 0 f 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 21300 ps> : 0 f 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?f ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 21400 ps> : 0 f 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?f ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 21500 ps> : 0 f 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 21600 ps> : 0 0 0 107 1 0 0 0 0 0 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 21700 ps> : 0 0 0 107 1 0 0 0 1 0 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 21800 ps> : 0 0 1 107 1 0 0 0 0 0 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 21900 ps> : 0 0 1 107 1 0 0 0 1 0 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 22000 ps> : 0 0 2 107 1 0 0 0 0 0 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 22100 ps> : 0 0 2 107 1 0 0 0 1 0 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 22200 ps> : 0 0 3 107 1 0 0 0 0 0 0 0 0 0 ?3 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 22300 ps> : 0 0 3 107 1 0 0 0 1 0 0 0 0 0 ?3 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 22400 ps> : 0 0 4 107 1 0 0 0 0 0 0 0 0 0 ?4 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 22500 ps> : 0 0 4 107 1 0 0 0 1 0 0 0 0 0 ?4 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 22600 ps> : 0 0 5 107 1 0 0 0 0 0 0 0 0 0 ?5 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 22700 ps> : 0 0 5 107 1 0 0 0 1 0 0 0 0 0 ?5 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 22800 ps> : 0 0 6 107 1 0 0 0 0 0 0 0 0 0 ?6 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 22900 ps> : 0 0 6 107 1 0 0 0 1 0 0 0 0 0 ?6 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 23000 ps> : 0 0 7 107 1 0 0 0 0 0 0 0 0 0 ?7 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 23100 ps> : 0 0 7 107 1 0 0 0 1 0 0 0 0 0 ?7 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 23200 ps> : 0 0 8 107 1 0 0 0 0 0 0 0 0 0 ?8 ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 23300 ps> : 0 0 8 107 1 0 0 0 1 0 0 0 0 0 ?8 ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 23400 ps> : 0 0 9 107 1 0 0 0 0 0 0 0 0 0 ?9 ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 23500 ps> : 0 0 9 107 1 0 0 0 1 0 0 0 0 0 ?9 ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 23600 ps> : 0 0 a 107 1 0 0 0 0 0 0 0 0 0 ?a ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 23700 ps> : 0 0 a 107 1 0 0 0 1 0 0 0 0 0 ?a ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 23800 ps> : 0 0 b 107 1 0 0 0 0 0 0 0 0 0 ?b ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 23900 ps> : 0 0 b 107 1 0 0 0 1 0 0 0 0 0 ?b ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 24000 ps> : 0 0 c 107 1 0 0 0 0 0 0 0 0 0 ?c ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 24100 ps> : 0 0 c 107 1 0 0 0 1 0 0 0 0 0 ?c ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 24200 ps> : 0 0 d 107 1 0 0 0 0 0 0 0 0 0 ?d ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 24300 ps> : 0 0 d 107 1 0 0 0 1 0 0 0 0 0 ?d ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 24400 ps> : 0 0 e 107 1 0 0 0 0 0 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 24500 ps> : 0 0 e 107 1 0 0 0 1 0 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 24600 ps> : 0 0 f 107 1 0 0 0 0 0 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 24700 ps> : 0 0 f 107 1 0 0 0 1 0 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 24800 ps> : 0 0 0 117 1 0 0 0 0 1 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 24900 ps> : 0 0 0 117 1 0 0 0 1 1 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 25000 ps> : 0 0 1 117 1 0 0 0 0 1 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 25100 ps> : 0 0 1 117 1 0 0 0 1 1 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 25200 ps> : 0 0 2 117 1 0 0 0 0 1 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 25300 ps> : 0 0 2 117 1 0 0 0 1 1 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 25400 ps> : 0 0 3 117 1 0 0 0 0 1 0 0 0 0 ?d ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 25500 ps> : 0 0 3 117 1 0 0 0 1 1 0 0 0 0 ?d ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 25600 ps> : 0 0 4 117 1 0 0 0 0 1 0 0 0 0 ?c ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 25700 ps> : 0 0 4 117 1 0 0 0 1 1 0 0 0 0 ?c ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 25800 ps> : 0 0 5 117 1 0 0 0 0 1 0 0 0 0 ?b ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 25900 ps> : 0 0 5 117 1 0 0 0 1 1 0 0 0 0 ?b ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 26000 ps> : 0 0 6 117 1 0 0 0 0 1 0 0 0 0 ?a ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 26100 ps> : 0 0 6 117 1 0 0 0 1 1 0 0 0 0 ?a ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 26200 ps> : 0 0 7 117 1 0 0 0 0 1 0 0 0 0 ?9 ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 26300 ps> : 0 0 7 117 1 0 0 0 1 1 0 0 0 0 ?9 ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 26400 ps> : 0 0 8 117 1 0 0 0 0 1 0 0 0 0 ?8 ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ;
|
||||
< 26500 ps> : 0 0 8 117 1 0 0 0 1 1 0 0 0 0 ?8 ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ;
|
||||
< 26600 ps> : 0 0 9 117 1 0 0 0 0 1 0 0 0 0 ?7 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 26700 ps> : 0 0 9 117 1 0 0 0 1 1 0 0 0 0 ?7 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 26800 ps> : 0 0 a 117 1 0 0 0 0 1 0 0 0 0 ?6 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 26900 ps> : 0 0 a 117 1 0 0 0 1 1 0 0 0 0 ?6 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 27000 ps> : 0 0 b 117 1 0 0 0 0 1 0 0 0 0 ?5 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 27100 ps> : 0 0 b 117 1 0 0 0 1 1 0 0 0 0 ?5 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 27200 ps> : 0 0 c 117 1 0 0 0 0 1 0 0 0 0 ?4 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 27300 ps> : 0 0 c 117 1 0 0 0 1 1 0 0 0 0 ?4 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 27400 ps> : 0 0 d 117 1 0 0 0 0 1 0 0 0 0 ?3 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 27500 ps> : 0 0 d 117 1 0 0 0 1 1 0 0 0 0 ?3 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 27600 ps> : 0 0 e 117 1 0 0 0 0 1 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 27700 ps> : 0 0 e 117 1 0 0 0 1 1 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 27800 ps> : 0 0 f 117 1 0 0 0 0 1 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 27900 ps> : 0 0 f 117 1 0 0 0 1 1 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 28000 ps> : 0 0 0 127 1 0 0 0 0 1 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 28100 ps> : 0 0 0 127 1 0 0 0 1 1 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 28200 ps> : 0 0 1 127 1 0 0 0 0 1 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 28300 ps> : 0 0 1 127 1 0 0 0 1 1 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 28400 ps> : 0 0 2 127 1 0 0 0 0 1 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 28500 ps> : 0 0 2 127 1 0 0 0 1 1 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 28600 ps> : 0 0 3 127 1 0 0 0 0 1 0 0 0 0 ?3 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 28700 ps> : 0 0 3 127 1 0 0 0 1 1 0 0 0 0 ?3 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 28800 ps> : 0 0 4 127 1 0 0 0 0 1 0 0 0 0 ?4 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 28900 ps> : 0 0 4 127 1 0 0 0 1 1 0 0 0 0 ?4 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 29000 ps> : 0 0 5 127 1 0 0 0 0 1 0 0 0 0 ?5 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 29100 ps> : 0 0 5 127 1 0 0 0 1 1 0 0 0 0 ?5 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 29200 ps> : 0 0 6 127 1 0 0 0 0 1 0 0 0 0 ?6 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 29300 ps> : 0 0 6 127 1 0 0 0 1 1 0 0 0 0 ?6 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 29400 ps> : 0 0 7 127 1 0 0 0 0 1 0 0 0 0 ?7 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 29500 ps> : 0 0 7 127 1 0 0 0 1 1 0 0 0 0 ?7 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 29600 ps> : 0 0 8 127 1 0 0 0 0 1 0 0 0 0 ?8 ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 29700 ps> : 0 0 8 127 1 0 0 0 1 1 0 0 0 0 ?8 ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 29800 ps> : 0 0 9 127 1 0 0 0 0 1 0 0 0 0 ?9 ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 29900 ps> : 0 0 9 127 1 0 0 0 1 1 0 0 0 0 ?9 ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 30000 ps> : 0 0 a 127 1 0 0 0 0 1 0 0 0 0 ?a ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 30100 ps> : 0 0 a 127 1 0 0 0 1 1 0 0 0 0 ?a ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 30200 ps> : 0 0 b 127 1 0 0 0 0 1 0 0 0 0 ?b ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 30300 ps> : 0 0 b 127 1 0 0 0 1 1 0 0 0 0 ?b ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 30400 ps> : 0 0 c 127 1 0 0 0 0 1 0 0 0 0 ?c ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 30500 ps> : 0 0 c 127 1 0 0 0 1 1 0 0 0 0 ?c ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 30600 ps> : 0 0 d 127 1 0 0 0 0 1 0 0 0 0 ?d ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 30700 ps> : 0 0 d 127 1 0 0 0 1 1 0 0 0 0 ?d ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 30800 ps> : 0 0 e 127 1 0 0 0 0 1 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 30900 ps> : 0 0 e 127 1 0 0 0 1 1 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 31000 ps> : 0 0 f 127 1 0 0 0 0 1 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 31100 ps> : 0 0 f 127 1 0 0 0 1 1 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 31200 ps> : 0 0 0 127 1 0 0 0 0 1 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 31300 ps> : 0 0 0 127 1 0 0 0 1 1 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 31400 ps> : 0 0 1 127 1 0 0 0 0 1 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 31500 ps> : 0 0 1 127 1 0 0 0 1 1 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 31600 ps> : 0 0 2 127 1 0 0 0 0 1 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 31700 ps> : 0 0 2 127 1 0 0 0 1 1 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 31800 ps> : 0 0 3 127 1 0 0 0 0 1 0 0 0 0 ?3 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 31900 ps> : 0 0 3 127 1 0 0 0 1 1 0 0 0 0 ?3 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 32000 ps> : 0 0 4 127 1 0 0 0 0 1 0 0 0 0 ?4 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 32100 ps> : 0 0 4 127 1 0 0 0 1 1 0 0 0 0 ?4 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 32200 ps> : 0 0 5 127 1 0 0 0 0 1 0 0 0 0 ?5 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 32300 ps> : 0 0 5 127 1 0 0 0 1 1 0 0 0 0 ?5 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 32400 ps> : 0 0 6 127 1 0 0 0 0 1 0 0 0 0 ?6 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 32500 ps> : 0 0 6 127 1 0 0 0 1 1 0 0 0 0 ?6 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 32600 ps> : 0 0 7 127 1 0 0 0 0 1 0 0 0 0 ?7 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 32700 ps> : 0 0 7 127 1 0 0 0 1 1 0 0 0 0 ?7 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 32800 ps> : 0 0 8 127 1 0 0 0 0 1 0 0 0 0 ?8 ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 32900 ps> : 0 0 8 127 1 0 0 0 1 1 0 0 0 0 ?8 ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 33000 ps> : 0 0 9 127 1 0 0 0 0 1 0 0 0 0 ?9 ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 33100 ps> : 0 0 9 127 1 0 0 0 1 1 0 0 0 0 ?9 ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 33200 ps> : 0 0 a 127 1 0 0 0 0 1 0 0 0 0 ?a ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 33300 ps> : 0 0 a 127 1 0 0 0 1 1 0 0 0 0 ?a ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 33400 ps> : 0 0 b 127 1 0 0 0 0 1 0 0 0 0 ?b ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 33500 ps> : 0 0 b 127 1 0 0 0 1 1 0 0 0 0 ?b ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 33600 ps> : 0 0 c 127 1 0 0 0 0 1 0 0 0 0 ?c ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 33700 ps> : 0 0 c 127 1 0 0 0 1 1 0 0 0 0 ?c ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 33800 ps> : 0 0 d 127 1 0 0 0 0 1 0 0 0 0 ?d ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 33900 ps> : 0 0 d 127 1 0 0 0 1 1 0 0 0 0 ?d ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 34000 ps> : 0 0 e 127 1 0 0 0 0 1 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 34100 ps> : 0 0 e 127 1 0 0 0 1 1 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 34200 ps> : 0 0 f 127 1 0 0 0 0 1 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 34300 ps> : 0 0 f 127 1 0 0 0 1 1 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 34400 ps> : 0 0 0 167 1 0 0 0 0 0 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 34500 ps> : 0 0 0 167 1 0 0 0 1 0 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 34600 ps> : 0 0 1 167 1 0 0 0 0 0 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 34700 ps> : 0 0 1 167 1 0 0 0 1 0 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 34800 ps> : 0 0 2 167 1 0 0 0 0 0 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 34900 ps> : 0 0 2 167 1 0 0 0 1 0 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 35000 ps> : 0 0 3 167 1 0 0 0 0 0 0 0 0 0 ?3 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 35100 ps> : 0 0 3 167 1 0 0 0 1 0 0 0 0 0 ?3 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
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|
||||
< 51500 ps> : 0 0 a 126 1 0 0 0 1 1 0 0 0 0 ?5 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ;
|
||||
< 51600 ps> : 0 0 b 126 1 0 0 0 0 1 0 0 0 0 ?6 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ;
|
||||
< 51700 ps> : 0 0 b 126 1 0 0 0 1 1 0 0 0 0 ?6 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ;
|
||||
< 51800 ps> : 0 0 c 126 1 0 0 0 0 1 0 0 0 0 ?7 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ;
|
||||
< 51900 ps> : 0 0 c 126 1 0 0 0 1 1 0 0 0 0 ?7 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ;
|
||||
< 52000 ps> : 0 0 d 126 1 0 0 0 0 1 0 0 0 0 ?8 ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 52100 ps> : 0 0 d 126 1 0 0 0 1 1 0 0 0 0 ?8 ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 52200 ps> : 0 0 e 126 1 0 0 0 0 1 0 0 0 0 ?9 ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 52300 ps> : 0 0 e 126 1 0 0 0 1 1 0 0 0 0 ?9 ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 52400 ps> : 0 0 f 126 1 0 0 0 0 1 0 0 0 0 ?a ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 52500 ps> : 0 0 f 126 1 0 0 0 1 1 0 0 0 0 ?a ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 52600 ps> : 0 0 0 126 1 0 0 0 0 1 0 0 0 0 ?b ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 52700 ps> : 0 0 0 126 1 0 0 0 1 1 0 0 0 0 ?b ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 52800 ps> : 0 0 1 126 1 0 0 0 0 1 0 0 0 0 ?c ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 52900 ps> : 0 0 1 126 1 0 0 0 1 1 0 0 0 0 ?c ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 53000 ps> : 0 0 2 126 1 0 0 0 0 1 0 0 0 0 ?d ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 53100 ps> : 0 0 2 126 1 0 0 0 1 1 0 0 0 0 ?d ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 53200 ps> : 0 0 3 126 1 0 0 0 0 1 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 53300 ps> : 0 0 3 126 1 0 0 0 1 1 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 53400 ps> : 0 0 4 126 1 0 0 0 0 1 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 53500 ps> : 0 0 4 126 1 0 0 0 1 1 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 53600 ps> : 0 0 5 126 1 0 0 0 0 1 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 53700 ps> : 0 0 5 126 1 0 0 0 1 1 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 53800 ps> : 0 0 6 126 1 0 0 0 0 1 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 53900 ps> : 0 0 6 126 1 0 0 0 1 1 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 54000 ps> : 0 0 7 126 1 0 0 0 0 1 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 54100 ps> : 0 0 7 126 1 0 0 0 1 1 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
|
||||
end;
|
||||
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Reference in New Issue