From 42b008a67edfe5a999c6433686395b9e02448265 Mon Sep 17 00:00:00 2001 From: Ludovic Jacomme Date: Sun, 23 May 2004 18:55:17 +0000 Subject: [PATCH] - full working AMD2901 --- .../alliance-examples/amd2901/Makefile | 276 ++++ .../alliance-examples/amd2901/amd2901_chip.c | 134 ++ .../amd2901/amd2901_chip.rin | 4 + .../alliance-examples/amd2901/amd2901_core.c | 173 +++ .../amd2901/amd2901_core.ioc | 66 + .../alliance-examples/amd2901/amd2901_ctl.lax | 6 + .../alliance-examples/amd2901/amd2901_ctl.vbe | 249 ++++ .../alliance-examples/amd2901/amd2901_dpt.c | 387 +++++ .../alliance-examples/amd2901/amd2901_dpt.vbe | 566 ++++++++ .../alliance-examples/amd2901/pattern.c | 1109 ++++++++++++++ .../alliance-examples/amd2901/pattern.pat | 593 ++++++++ .../amd2901/pattern_core.spi | 1281 +++++++++++++++++ 12 files changed, 4844 insertions(+) create mode 100644 alliance/src/documentation/alliance-examples/amd2901/Makefile create mode 100644 alliance/src/documentation/alliance-examples/amd2901/amd2901_chip.c create mode 100644 alliance/src/documentation/alliance-examples/amd2901/amd2901_chip.rin create mode 100644 alliance/src/documentation/alliance-examples/amd2901/amd2901_core.c create mode 100644 alliance/src/documentation/alliance-examples/amd2901/amd2901_core.ioc create mode 100644 alliance/src/documentation/alliance-examples/amd2901/amd2901_ctl.lax create mode 100644 alliance/src/documentation/alliance-examples/amd2901/amd2901_ctl.vbe create mode 100644 alliance/src/documentation/alliance-examples/amd2901/amd2901_dpt.c create mode 100644 alliance/src/documentation/alliance-examples/amd2901/amd2901_dpt.vbe create mode 100644 alliance/src/documentation/alliance-examples/amd2901/pattern.c create mode 100644 alliance/src/documentation/alliance-examples/amd2901/pattern.pat create mode 100644 alliance/src/documentation/alliance-examples/amd2901/pattern_core.spi diff --git a/alliance/src/documentation/alliance-examples/amd2901/Makefile b/alliance/src/documentation/alliance-examples/amd2901/Makefile new file mode 100644 index 00000000..d3ff9662 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/amd2901/Makefile @@ -0,0 +1,276 @@ + + +# +# /------------------------------------------------------------------\ +# | Macros definitions | +# \------------------------------------------------------------------/ +# + +# Standart System binary access paths. + STANDART_BIN = /usr/local/bin:/usr/bin:/bin + STANDART_PATH = PATH=$(STANDART_BIN); export PATH + +# Standart Alliance binary access paths. + ALLIANCE_BIN = $(ALLIANCE_TOP)/bin + +# -------------------------------------------------------------------- +# Standarts binaries. + + LS = /bin/ls + CD = PATH=$(STANDART_BIN); cd + CP = PATH=$(STANDART_BIN); cp + LN = PATH=$(STANDART_BIN); ln + MV = PATH=$(STANDART_BIN); mv + RM = PATH=$(STANDART_BIN); rm + SED = PATH=$(STANDART_BIN); sed + AWK = PATH=$(STANDART_BIN); gawk + CAT = PATH=$(STANDART_BIN); cat + MAKE = PATH=$(STANDART_BIN); make + TOUCH = PATH=$(STANDART_BIN); touch + GREP = PATH=$(STANDART_BIN); grep + ECHO = /bin/echo +# Alliance paths and formats settings. + GENERAT_LO = vst + EXTRACT_LO = al + GENERAT_PH = ap + EXTRACT_PH = ap + GENERAT_SP = . + EXTRACT_SP = . + CATA_LIB0 = $(ALLIANCE_TOP)/cells/sxlib + CATA_LIB1 = $(ALLIANCE_TOP)/cells/dp_sxlib + CATA_LIB2 = $(ALLIANCE_TOP)/cells/padlib + CATA_LIB = .:$(CATA_LIB0):$(CATA_LIB1):$(CATA_LIB2) + TARGET_LIB = $(ALLIANCE_TOP)/cells/sxlib + RDS_TECHNO = ../etc/techno-symb.rds + REAL_RDS_TECHNO = ../etc/techno-035.rds + GRAAL_TECHNO = $(ALLIANCE_TOP)/etc/cmos.graal + + + MBK_GENERAT_ENV = MBK_TARGET_LIB=$(TARGET_LIB); export MBK_TARGET_LIB; \ + MBK_WORK_LIB=.; export MBK_WORK_LIB; \ + MBK_CATA_LIB=$(CATA_LIB); export MBK_CATA_LIB; \ + MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME; \ + MBK_OUT_LO=$(GENERAT_LO); export MBK_OUT_LO; \ + MBK_OUT_PH=$(GENERAT_PH); export MBK_OUT_PH; \ + MBK_IN_LO=$(GENERAT_LO); export MBK_IN_LO; \ + MBK_IN_PH=$(GENERAT_PH); export MBK_IN_PH; \ + MBK_SEPAR=$(GENERAT_SP); export MBK_SEPAR; \ + MBK_VDD=vdd; export MBK_VDD; \ + MBK_VSS=vss; export MBK_VSS; \ + RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME; \ + GRAAL_TECHNO_NAME=$(GRAAL_TECHNO); export GRAAL_TECHNO_NAME + +# MBK extracting environment. + MBK_EXTRACT_ENV = MBK_TARGET_LIB=$(TARGET_LIB); export MBK_TARGET_LIB; \ + MBK_WORK_LIB=.; export MBK_WORK_LIB; \ + MBK_CATA_LIB=$(CATA_LIB); export MBK_CATA_LIB; \ + MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME; \ + MBK_OUT_LO=$(EXTRACT_LO); export MBK_OUT_LO; \ + MBK_OUT_PH=$(EXTRACT_PH); export MBK_OUT_PH; \ + MBK_IN_LO=$(EXTRACT_LO); export MBK_IN_LO; \ + MBK_IN_PH=$(EXTRACT_PH); export MBK_IN_PH; \ + MBK_SEPAR=$(EXTRACT_SP); export MBK_SEPAR; \ + MBK_VDD=vdd; export MBK_VDD; \ + MBK_VSS=vss; export MBK_VSS; \ + RDS_TECHNO_NAME=$(REAL_RDS_TECHNO); export RDS_TECHNO_NAME;\ + GRAAL_TECHNO_NAME=$(GRAAL_TECHNO); export GRAAL_TECHNO_NAME + +MBK_EXTRACT_ENV_SPI = MBK_TARGET_LIB=$(TARGET_LIB); export MBK_TARGET_LIB; \ + MBK_WORK_LIB=.; export MBK_WORK_LIB; \ + MBK_CATA_LIB=$(CATA_LIB); export MBK_CATA_LIB; \ + MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME; \ + MBK_OUT_LO=spi; export MBK_OUT_LO; \ + MBK_OUT_PH=$(EXTRACT_PH); export MBK_OUT_PH; \ + MBK_IN_LO=spi; export MBK_IN_LO; \ + MBK_IN_PH=$(EXTRACT_PH); export MBK_IN_PH; \ + MBK_SEPAR=$(EXTRACT_SP); export MBK_SEPAR; \ + MBK_VDD=vdd; export MBK_VDD; \ + MBK_VSS=vss; export MBK_VSS; \ + RDS_TECHNO_NAME=$(REAL_RDS_TECHNO); export RDS_TECHNO_NAME;\ + GRAAL_TECHNO_NAME=$(GRAAL_TECHNO); export GRAAL_TECHNO_NAME + +# -------------------------------------------------------------------- +# Alliance binaries & environment. + + BOOM = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/boom -V + BOOG = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/boog + LOON = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/loon + ASIMUT1 = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/asimut + ASIMUT2 = $(MBK_EXTRACT_ENV); $(ALLIANCE_BIN)/asimut + COUGAR = $(ALLIANCE_BIN)/cougar + DRUC = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/druc + LVX = $(MBK_EXTRACT_ENV); $(ALLIANCE_BIN)/lvx + PROOF = $(MBK_EXTRACT_ENV); $(ALLIANCE_BIN)/proof + GENLIB = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/genlib + GENPAT = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/genpat + OCP = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/ocp + NERO = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/nero + OCR = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/ocr + RING = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/ring + GRAAL = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/graal + DREAL = $(MBK_EXTRACT_ENV); $(ALLIANCE_BIN)/dreal + XSCH = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/xsch + XPAT = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/xpat + + +# /------------------------------------------------------------------\ +# | Rules | +# \------------------------------------------------------------------/ +# + +all: nb_transistors + +ctl_part: amd2901_ctl.vst + +view_ctl_logic: amd2901_ctl.vst + $(XSCH) -l amd2901_ctl + +dpt_part: amd2901_dpt.ap amd2901_dpt.vst + +view_dpt_physic: amd2901_dpt.ap + $(GRAAL) -l amd2901_dpt + +chip_part: amd2901_chip.ap + +view_chip_physic: amd2901_chip.ap + $(GRAAL) -l amd2901_chip + +chip_verification: druc_chip lvx_chip test_chip_final.pat + +view_chip_simulation: test_chip_final.pat + $(XPAT) -l test_chip_final + +amd2901_core.vst amd2901_core_place.ap: amd2901_core.c amd2901_ctl.vst amd2901_ctl.vbe amd2901_dpt.vst amd2901_dpt.ap + $(GENLIB) -v amd2901_core + +amd2901_chip.vst: amd2901_core.vst + $(GENLIB) -v amd2901_chip + +test_chip.pat: amd2901_chip.vst pattern.pat + $(ASIMUT1) -zd amd2901_chip pattern test_chip + +test_core.pat: amd2901_core.vst amd2901_core.pat + $(ASIMUT1) -zd amd2901_core amd2901_core test_core + +# LUDO +# pattern.pat: pattern.c +# $(GENPAT) -v pattern + +amd2901_dpt.ap amd2901_dpt.vst: amd2901_dpt.c + $(GENLIB) -v amd2901_dpt + +amd2901_ctl_boom.vbe : amd2901_ctl.vbe + $(BOOM) amd2901_ctl amd2901_ctl_boom + +amd2901_ctl_boog.vst : amd2901_ctl_boom.vbe amd2901_ctl.lax + $(BOOG) amd2901_ctl_boom amd2901_ctl_boog amd2901_ctl + +amd2901_ctl.vst : amd2901_ctl_boog.vst + $(LOON) amd2901_ctl_boog amd2901_ctl + +amd2901_core_p.ap: amd2901_core.vst amd2901_core_place.ap amd2901_core.ioc + $(OCP) -v -gnuplot -partial amd2901_core_place -ioc amd2901_core amd2901_core amd2901_core_p +# $(OCP) -v -gnuplot -partial amd2901_core_place -ring amd2901_core amd2901_core_p + +druc_ocp: amd2901_core_p.ap + $(DRUC) amd2901_core_p + $(TOUCH) druc_ocp + +amd2901_core.ap: druc_ocp + $(NERO) -2 -p amd2901_core_p amd2901_core amd2901_core + +# amd2901_core.ap: druc_ocp +# $(OCR) -v -l 2 -L amd2901_core -P amd2901_core_p -O amd2901_core + +amd2901_core.al: amd2901_core.ap + $(MBK_EXTRACT_ENV); $(COUGAR) -v -f amd2901_core amd2901_core + +amd2901_core.spi: amd2901_core.ap + $(MBK_EXTRACT_ENV_SPI); $(COUGAR) -v -ac -t amd2901_core amd2901_core + +lvx_core: amd2901_core.al amd2901_core.vst + $(LVX) al vst amd2901_core amd2901_core -f + $(TOUCH) lvx_core + +druc_core: amd2901_core.ap + $(DRUC) amd2901_core + $(TOUCH) druc_core + +amd2901_chip.ap: test_chip.pat amd2901_core.ap amd2901_chip.rin druc_core lvx_core + $(MBK_GENERAT_ENV); $(RING) amd2901_chip amd2901_chip + +amd2901_chip.al: amd2901_chip.ap + $(MBK_EXTRACT_ENV); $(COUGAR) -v -f amd2901_chip amd2901_chip + +lvx_chip: amd2901_chip.al amd2901_chip.vst + $(LVX) al vst amd2901_chip amd2901_chip -f + $(TOUCH) lvx_chip + +druc_chip: amd2901_chip.ap + $(DRUC) amd2901_chip + $(TOUCH) druc_chip + +test_chip_final.pat: pattern.pat druc_chip lvx_chip + $(ASIMUT2) -zd amd2901_chip pattern test_chip_final + +nb_transistors: amd2901_chip_tr.al amd2901_core_tr.al + @echo "Number of transistors for the core: ";\ + $(GREP) -c "^T" amd2901_core_tr.al + @echo "Number of transistors for the chip: ";\ + $(GREP) -c "^T" amd2901_chip_tr.al + +amd2901_chip_tr.al: test_chip_final.pat + $(MBK_EXTRACT_ENV); $(COUGAR) -v -t amd2901_chip amd2901_chip_tr + +amd2901_core_tr.al: lvx_core druc_core + $(MBK_EXTRACT_ENV); $(COUGAR) -v -t amd2901_core amd2901_core_tr + +# /*------------------------------------------------------------\ +# | | +# | TOOLS | +# | | +# \------------------------------------------------------------*/ + +graal: amd2901_chip.ap + $(GRAAL) -l amd2901_chip + +xsch: amd2901_ctl.vst + $(XSCH) -l amd2901_ctl + +xpat: test_chip_final.pat + $(XPAT) -l test_chip_final + +dreal: amd2901_chip.cif + $(DREAL) -l amd2901_chip + +# /*------------------------------------------------------------\ +# | | +# | CLEAN | +# | | +# \------------------------------------------------------------*/ + +clean : + rm -f Makefile-* \ + amd2901_core.vst \ + amd2901_chip.vst \ + amd2901_ctl.vst \ + amd2901_dpt.vst \ + amd2901_ctl_boog.vst \ + amd2901_ctl_boom.vbe \ + *.ap \ + res.pat \ + *.frr \ + *.log \ + *.drc \ + *.gds \ + *.def \ + *.gpl \ + *.xsc \ + *.al \ + test_*.pat \ + *~ \ + *cif \ + lvx_core druc_core \ + lvx_chip druc_chip \ + druc_ocp alldata.dat \ + model_* diff --git a/alliance/src/documentation/alliance-examples/amd2901/amd2901_chip.c b/alliance/src/documentation/alliance-examples/amd2901/amd2901_chip.c new file mode 100644 index 00000000..3650e3aa --- /dev/null +++ b/alliance/src/documentation/alliance-examples/amd2901/amd2901_chip.c @@ -0,0 +1,134 @@ +#include +#define POWER "vdde","vdd","vsse","vss",0 + +int main () + { + int i; + + GENLIB_DEF_LOFIG("amd2901_chip"); + + + GENLIB_LOCON("ck", IN ,"ck"); + + GENLIB_LOCON( "cin", IN, "cin"); + GENLIB_LOCON( "cout", OUT, "cout"); + GENLIB_LOCON( "np", OUT , "np"); + GENLIB_LOCON( "ng", OUT , "ng"); + GENLIB_LOCON( "ovr", OUT , "ovr"); + GENLIB_LOCON( "zero", OUT , "zero"); + GENLIB_LOCON("signe", UNKNOWN,"signe"); + + + GENLIB_LOCON("r0", UNKNOWN, "r0"); + GENLIB_LOCON("r3", UNKNOWN, "r3"); + GENLIB_LOCON("q0", UNKNOWN, "q0"); + GENLIB_LOCON("q3", UNKNOWN, "q3"); + + GENLIB_LOCON( "fonc", IN , "fonc"); + GENLIB_LOCON( "test", IN , "test"); + GENLIB_LOCON( "scin", IN , "scin"); + GENLIB_LOCON("scout", OUT ,"scout"); + + GENLIB_LOCON("a[3:0]", IN , "a[3:0]"); + GENLIB_LOCON("b[3:0]", IN , "b[3:0]"); + GENLIB_LOCON("d[3:0]", IN , "d[3:0]"); + GENLIB_LOCON("i[8:0]", IN , "i[8:0]"); + GENLIB_LOCON("noe" , IN , "noe" ); + GENLIB_LOCON("y[3:0]", UNKNOWN, "y[3:0]"); + + GENLIB_LOCON("vdd" , IN , "vdd" ); + GENLIB_LOCON("vss" , IN , "vss" ); + GENLIB_LOCON("vdde", IN , "vdde"); + GENLIB_LOCON("vsse", IN , "vsse"); + + GENLIB_LOINSE ( "amd2901_core", "core", + "cin => cin_i", + "cout => cout_i", + "np => np_i", + "ng => ng_i", + "over => ovr_i", + "zero => zero_i", + + "sh_right => sh_right", + "sh_left => sh_left", + "ram_o_down => ram_o_down", + "ram_o_up => ram_o_up", + "ram_i_down => ram_i_down", + "ram_i_up => ram_i_up", + + "acc_o_down => acc_o_down", + "acc_o_up => acc_o_up", + "acc_i_down => acc_i_down", + "acc_i_up => acc_i_up", + + "fonc => fonc_i", + "test => test_i", + "scin => scin_i", + "ck => ckc", + + "a[3:0] => a_i[3:0]", + "b[3:0] => b_i[3:0]", + "d[3:0] => d_i[3:0]", + "i[8:0] => i_i[8:0]", + + "y[3:0] => y_i[3:0]", + + "noe => noe_i", + "oe => oe", + + "vdd => vdd", + "vss => vss", + 0); + + GENLIB_LOINS("pck_sp","p_ck","ck","cki", POWER); + + GENLIB_LOINS("pi_sp","p_fonc","fonc","fonc_i","cki", POWER ); + GENLIB_LOINS("pi_sp","p_test","test","test_i","cki", POWER ); + GENLIB_LOINS("pi_sp","p_scin","scin","scin_i","cki", POWER ); + GENLIB_LOINS("pi_sp","p_cin","cin","cin_i","cki", POWER ); + GENLIB_LOINS("pi_sp","p_noe","noe","noe_i","cki", POWER ); + + for (i=0;i<4;i++) + { + GENLIB_LOINS("pi_sp",GENLIB_NAME("p_a%d",i), GENLIB_ELM("a",i), GENLIB_ELM("a_i",i), "cki", POWER ); + GENLIB_LOINS("pi_sp",GENLIB_NAME("p_b%d",i), GENLIB_ELM("b",i), GENLIB_ELM("b_i",i), "cki", POWER ); + GENLIB_LOINS("pi_sp",GENLIB_NAME("p_d%d",i), GENLIB_ELM("d",i), GENLIB_ELM("d_i",i), "cki", POWER ); + } + + for (i=0;i<9;i++) + GENLIB_LOINS("pi_sp",GENLIB_NAME("p_i%d",i), GENLIB_ELM("i",i), GENLIB_ELM("i_i",i), "cki", POWER ); + + GENLIB_LOINS("po_sp","p_cout","cout_i","cout","cki", POWER ); + GENLIB_LOINS("po_sp","p_np","np_i","np","cki", POWER ); + GENLIB_LOINS("po_sp","p_ng","ng_i","ng","cki", POWER ); + GENLIB_LOINS("po_sp","p_ovr","ovr_i","ovr","cki", POWER ); + GENLIB_LOINS("po_sp","p_zero","zero_i","zero","cki", POWER ); + GENLIB_LOINS("po_sp","p_signe","ram_o_up","signe","cki", POWER ); + GENLIB_LOINS("po_sp","p_scout","acc_o_up","scout","cki", POWER ); + + for (i=0;i<4;i++) + GENLIB_LOINS ("pot_sp",GENLIB_NAME("p_y%d",i), + GENLIB_ELM("y_i",i), "oe", GENLIB_ELM("y",i), "cki", POWER ); + + GENLIB_LOINS ("piot_sp","p_q0", + "acc_o_down","sh_right","acc_i_down","q0","cki", POWER ); + GENLIB_LOINS ("piot_sp","p_q3", + "acc_o_up","sh_left","acc_i_up","q3","cki", POWER ); + GENLIB_LOINS ("piot_sp","p_r0", + "ram_o_down","sh_right","ram_i_down","r0","cki", POWER ); + GENLIB_LOINS ("piot_sp","p_r3", + "ram_o_up","sh_left","ram_i_up","r3","cki", POWER ); + + GENLIB_LOINS("pvddick_sp","p_vddick0","ckc","cki","vdde","vdd","vsse","vss",0); + GENLIB_LOINS("pvssick_sp","p_vssick0","ckc","cki","vdde","vdd","vsse","vss",0); + + GENLIB_LOINS("pvddeck_sp","p_vddeck0","ckc","cki","vdde","vdd","vsse","vss",0); + GENLIB_LOINS("pvddeck_sp","p_vddeck1","ckc","cki","vdde","vdd","vsse","vss",0); + GENLIB_LOINS("pvsseck_sp","p_vsseck0","ckc","cki","vdde","vdd","vsse","vss",0); + GENLIB_LOINS("pvsseck_sp","p_vsseck1","ckc","cki","vdde","vdd","vsse","vss",0); + + GENLIB_SAVE_LOFIG(); + + exit (0); + + } diff --git a/alliance/src/documentation/alliance-examples/amd2901/amd2901_chip.rin b/alliance/src/documentation/alliance-examples/amd2901/amd2901_chip.rin new file mode 100644 index 00000000..12230393 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/amd2901/amd2901_chip.rin @@ -0,0 +1,4 @@ +east (p_q0 p_q3 p_b0 p_b1 p_b2 p_vddeck0 p_vsseck0 p_zero p_scout p_signe p_y2 p_y3 ) +west (p_b3 p_cin p_ck p_cout p_vddick0 p_vssick0 p_vddeck1 p_vsseck1 p_i3 p_i4 p_i5 p_i6 ) +north ( p_d0 p_d1 p_d2 p_d3 p_fonc p_i0 p_i1 p_i2 p_a0 p_a1 p_a2 p_a3 ) +south ( p_i7 p_i8 p_ng p_noe p_np p_ovr p_r0 p_r3 p_scin p_test p_y0 p_y1 ) diff --git a/alliance/src/documentation/alliance-examples/amd2901/amd2901_core.c b/alliance/src/documentation/alliance-examples/amd2901/amd2901_core.c new file mode 100644 index 00000000..5a54160b --- /dev/null +++ b/alliance/src/documentation/alliance-examples/amd2901/amd2901_core.c @@ -0,0 +1,173 @@ +#include + +main() +{ + GENLIB_DEF_LOFIG ("amd2901_core"); + GENLIB_DEF_PHFIG ("amd2901_core_place"); + + + /* ***************** Terminal Declarations ****************** */ + + + /* Pin terminals associated with ALU. */ + GENLIB_LOCON("cin", UNKNOWN, "cin" ); + GENLIB_LOCON("cout", UNKNOWN, "cout"); + GENLIB_LOCON("np", OUT , "np" ); + GENLIB_LOCON("ng", OUT , "ng" ); + GENLIB_LOCON("over", OUT , "over"); + GENLIB_LOCON("zero", OUT , "zero"); + + /* Pin terminals associated with the RAM and ACCU shifter. */ + /* RAM and ACCU I/O plots controls. */ + GENLIB_LOCON( "sh_right", OUT, "sh_right"); + GENLIB_LOCON( "sh_left" , OUT, "sh_left" ); + /* RAM shifter I/O. */ + GENLIB_LOCON("ram_o_down" ,UNKNOWN, "alu_f[0]" ); + GENLIB_LOCON("ram_o_up" ,UNKNOWN, "alu_f[3]" ); + GENLIB_LOCON("ram_i_down" , IN , "ram_i_down" ); + GENLIB_LOCON("ram_i_up" , IN , "ram_i_up" ); + /* ACC shifter I/O. */ + GENLIB_LOCON("acc_o_down" ,UNKNOWN, "acc_o_down" ); + GENLIB_LOCON("acc_o_up" ,UNKNOWN, "acc_scout" ); + GENLIB_LOCON("acc_i_down" , IN , "acc_i_down" ); + GENLIB_LOCON("acc_i_up" , IN , "acc_i_up" ); + + /* ACCU controls terminals. */ + GENLIB_LOCON( "fonc", IN , "fonc"); + GENLIB_LOCON( "test", IN , "test"); + GENLIB_LOCON( "scin", IN , "scin"); + GENLIB_LOCON( "ck", IN , "ck"); + + /* Data bus terminals. */ + GENLIB_LOCON( "a[3:0]", IN , "a[3:0]"); + GENLIB_LOCON( "b[3:0]", IN , "b[3:0]"); + GENLIB_LOCON( "d[3:0]", IN , "d[3:0]"); + GENLIB_LOCON( "i[8:0]", IN , "i[8:0]"); + GENLIB_LOCON( "y[3:0]", OUT , "y[3:0]"); + + GENLIB_LOCON( "noe", IN, "noe"); + GENLIB_LOCON( "oe", OUT, "oe"); + + /* Power suplies terminals. */ + GENLIB_LOCON("vdd", IN ,"vdd"); + GENLIB_LOCON("vss", IN ,"vss"); + + + /* **************** Data-Path Instanciation ***************** */ + + + GENLIB_LOINSE("amd2901_dpt", "amd2901_dpt", + /* ck */ + "ram_ck[0] => ck", + "ram_ck[1] => ck", + "ram_ck[2] => ck", + "ram_ck[3] => ck", + "ram_ck[4] => ck", + "ram_ck[5] => ck", + "ram_ck[6] => ck", + "ram_ck[7] => ck", + "ram_ck[8] => ck", + "ram_ck[9] => ck", + "ram_ck[10] => ck", + "ram_ck[11] => ck", + "ram_ck[12] => ck", + "ram_ck[13] => ck", + "ram_ck[14] => ck", + "ram_ck[15] => ck", + "ops_mx[2:0] => ops_mx[2:0]", + "opr_mx[1:0] => opr_mx[1:0]", + "alu_k[4:0] => alu_k[4:0]", + "alu_cin => cin", /* plot */ + "alu_cout => cout", + "alu_over => alu_over", + + "ram_sh[1:0] => ram_sh[1:0]", + "acc_sh[1:0] => ram_sh[1:0]", + "ram_i_up => ram_i_up", + "ram_i_down => ram_i_down", + "acc_i_up => acc_i_up", + "acc_i_down => acc_i_down", + "acc_q_down => acc_o_down", + + "out_mx => out_mx", + + "acc_ck => ck", + "acc_wen => acc_wen", + "acc_test => test", /* plot */ + "acc_scin => scin", /* plot */ + "acc_scout => acc_scout", + + "a[15:0] => deca[15:0]", + "b[15:0] => decb[15:0]", + "b_w[15:0] => decwb[15:0]", + + + "opr_d[3:0] => d[3:0]", + "alu_f[3:0] => alu_f[3:0]", + "alu_np[3:0] => alu_np[3:0]", + "alu_ng[3:0] => alu_ng[3:0]", + "out_x[3:0] => y[3:0]", + + "vdd => vdd", + "vss => vss", 0); + + + /* ***************** Control Instanciation ****************** */ + + + GENLIB_LOINSE("amd2901_ctl", "ctl", + + "ops_mx[2:0] => ops_mx[2:0]", + "opr_mx[1:0] => opr_mx[1:0]", + + "alu_k[4:0] => alu_k[4:0]", + "alu_cout => cout", + "alu_over => alu_over", + +/******************************/ + "deca[15:0] => deca[15:0]", + "decb[15:0] => decb[15:0]", + "decwb[15:0] => decwb[15:0]", + + "a[3:0] => a[3:0]", + "b[3:0] => b[3:0]", + +/**********************************/ + "ram_sh[1:0] => ram_sh[1:0]", + + "out_mx => out_mx", + + "acc_wen => acc_wen", + + "alu_f[3:0] => alu_f[3:0]", + "alu_np[3:0] => alu_np[3:0]", + "alu_ng[3:0] => alu_ng[3:0]", + + "core_test => test", /* plot */ + "core_fonc => fonc", /* plot */ + + "core_np => np", /* plot */ + "core_ng => ng", /* plot */ + "core_over => over", /* plot */ + "core_zero => zero", /* plot */ + + "core_sh_right => sh_right", + "core_sh_left => sh_left", + + "i[8:0] => i[8:0]", + + + "noe => noe", + "oe => oe", + + "vdd => vdd", + "vss => vss", 0); + + GENLIB_PLACE ("amd2901_dpt", "amd2901_dpt", NOSYM, 0, 0); + GENLIB_DEF_AB (0, 0, 0, 100); + GENLIB_SAVE_LOFIG(); + GENLIB_SAVE_PHFIG(); + + + exit(0); +} diff --git a/alliance/src/documentation/alliance-examples/amd2901/amd2901_core.ioc b/alliance/src/documentation/alliance-examples/amd2901/amd2901_core.ioc new file mode 100644 index 00000000..83801e88 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/amd2901/amd2901_core.ioc @@ -0,0 +1,66 @@ +# Copyright (c) 1997 by Cadence. All rights reserved. +################################################################### +# In each of TOP()/BOTTOM()/LEFT()/RIGHT() section, there are # +# placed IOs. In the IGNORE() section, the IOs are ignored # +# by the IOPlacer. In every section, the IO syntax could be: # +# for pin: (IOPIN iopinName.0 ); # +# for pad: iopadName orientation ; # +# for space: SPACE value; # +# The capital words are keywords. orientation is not required. # +# The value is the space between the IO above and the IO below it.# +################################################################### + +TOP ( # IOs are ordered from left to right + (IOPIN b(3).0 ); + (IOPIN cin.0 ); + (IOPIN ck.0 ); + (IOPIN cout.0 ); + (IOPIN d(0).0 ); + (IOPIN d(1).0 ); + (IOPIN d(2).0 ); + (IOPIN d(3).0 ); + (IOPIN fonc.0 ); + (IOPIN i(0).0 ); + (IOPIN i(1).0 ); + (IOPIN i(2).0 ); + (IOPIN a(0).0 ); + (IOPIN a(1).0 ); + (IOPIN a(2).0 ); + (IOPIN a(3).0 ); + (IOPIN ng.0 ); + (IOPIN acc_i_down.0 ); + (IOPIN acc_i_up.0 ); + (IOPIN acc_o_down.0 ); + (IOPIN acc_o_up.0 ); + (IOPIN b(0).0 ); + (IOPIN b(1).0 ); + (IOPIN b(2).0 ); + +) +BOTTOM ( # IOs are ordered from left to right + (IOPIN i(3).0 ); + (IOPIN i(4).0 ); + (IOPIN i(5).0 ); + (IOPIN i(6).0 ); + (IOPIN i(7).0 ); + (IOPIN i(8).0 ); + (IOPIN noe.0 ); + (IOPIN np.0 ); + (IOPIN oe.0 ); + (IOPIN over.0 ); + (IOPIN ram_i_down.0 ); + (IOPIN ram_i_up.0 ); + (IOPIN ram_o_down.0 ); + (IOPIN ram_o_up.0 ); + (IOPIN scin.0 ); + (IOPIN sh_left.0 ); + (IOPIN sh_right.0 ); + (IOPIN test.0 ); + (IOPIN y(0).0 ); + (IOPIN y(1).0 ); + (IOPIN y(2).0 ); + (IOPIN y(3).0 ); + (IOPIN zero.0 ); +) +IGNORE ( # IOs are ignored(not placed) by IO Placer +) diff --git a/alliance/src/documentation/alliance-examples/amd2901/amd2901_ctl.lax b/alliance/src/documentation/alliance-examples/amd2901/amd2901_ctl.lax new file mode 100644 index 00000000..ca9b8722 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/amd2901/amd2901_ctl.lax @@ -0,0 +1,6 @@ +##Used by boog and loon +#M{4} +## Set the Optimisation Level (1..5) +## 1 : poor optimisation - small computation time +## 5 : best optimisation - long computation time +#L{5} diff --git a/alliance/src/documentation/alliance-examples/amd2901/amd2901_ctl.vbe b/alliance/src/documentation/alliance-examples/amd2901/amd2901_ctl.vbe new file mode 100644 index 00000000..2ff75d15 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/amd2901/amd2901_ctl.vbe @@ -0,0 +1,249 @@ +ENTITY amd2901_ctl IS + +PORT( + -- Input/Output from and to the data-path. + + + -- Command for selecting operands R and S. + ops_mx : out BIT_VECTOR(2 downto 0); + opr_mx : out BIT_VECTOR(1 downto 0); + + -- ALU commands and auxiliary terminals. + alu_k : out BIT_VECTOR(4 downto 0); + alu_cout : in BIT; + alu_over : in BIT; + + -- RAM, ACCU shifter commands and auxiliary terminals. + -- ("acc_sh" is same as "ram_sh") + ram_sh : out BIT_VECTOR(1 downto 0); + + -- Output multiplexer commnand (for X bus). + out_mx : out BIT; + + -- ACCU controls terminals. + -- ("acc_ck", "acc_test" and "acc_scin" directly comes from the plots) + acc_wen : out BIT; + + -- Data bus terminals. + alu_f : in BIT_VECTOR(3 downto 0); + alu_np : in BIT_VECTOR(3 downto 0); + alu_ng : in BIT_VECTOR(3 downto 0); + + + -- Input/Output from and to the plots. + + + -- Test terminals from/to plots. + core_test : in BIT; + core_fonc : in BIT; + + -- ALU terminals from/to plots. + -- core_ncout : out BIT; + core_np : out BIT; + core_ng : out BIT; + core_over : out BIT; + core_zero : out BIT; + -- core_nsign : out BIT; + + -- RAM, ACCU shifter terminals from/to plots. + -- RAM and ACCU I/O plots controls. + core_sh_right : out BIT; + core_sh_left : out BIT; + + -- Data bus terminals from/to the plots. + i : in BIT_VECTOR(8 downto 0); + + noe : in BIT; + oe : out BIT; +-- - +-- ram_wri : out BIT; + + -- + + a : in BIT_VECTOR(3 downto 0); + b : in BIT_VECTOR(3 downto 0); + + deca : out BIT_VECTOR(15 downto 0); + decb : out BIT_VECTOR(15 downto 0); + decwb : out BIT_VECTOR(15 downto 0); + + -- Power supply connectors. + vdd : in BIT; + vss : in BIT + + -- - + + ); + +END amd2901_ctl; + + +ARCHITECTURE behavior_data_flow OF amd2901_ctl IS + + -- Internals bus. + SIGNAL alu_p : BIT_VECTOR(3 downto 0); + SIGNAL alu_g : BIT_VECTOR(3 downto 0); + -- Internals signals. + SIGNAL fonc_mode : BIT; + SIGNAL ram_wri : BIT; + SIGNAL interm : BIT_VECTOR (15 downto 0); +BEGIN + + + -- ******************** Miscellaneous controls ******************* + + + -- Select between normal and test mode. + fonc_mode <= core_fonc and (not core_test); + + + -- *************** ACCU and RAM multiplexer control ************** + + WITH i(8 DOWNTO 6) SELECT + ram_sh <= "00" WHEN B"110" + | B"111", + "01" WHEN B"100" + | B"101", + "11" WHEN OTHERS; + + + -- ******************** S multiplexer control ******************** + + WITH i(2 downto 0) SELECT + ops_mx <= "000" WHEN B"110", + "000" WHEN B"010", + "000" WHEN B"000", + "010" WHEN B"101" + | B"100", + "001" WHEN B"001", + "001" WHEN B"011", + "100" WHEN B"111"; + + + -- ******************** R multiplexer control ******************** + + WITH i(2 downto 0) SELECT + opr_mx <= "11" WHEN B"100" + | B"010" + | B"011", + "01" WHEN B"101" + | B"110" + | B"111", + "00" WHEN B"000" + | B"001"; + + + -- ******************** X multiplexer control ******************** + + WITH i(8 downto 6) SELECT + out_mx <= "1" WHEN B"010", + "0" WHEN OTHERS; + + + -- ************************* ALU control ************************* + + -- ALU commands. + alu_k(4) <= ( i(5) or ( i(4) and i(3))); + alu_k(3) <= (not i(5) and ( i(4) and i(3))); + alu_k(2) <= ( i(5) and not i(4)) ; + alu_k(1) <= i(5) xor i(4); + alu_k(0) <= i(5) xor i(3); + + -- Compute of ALU flags. + -- Propagate. + alu_p(3 downto 0) <= not alu_np(3 downto 0); + core_np <= not ( alu_p(0) + and alu_p(1) + and alu_p(2) + and alu_p(3)); + + -- Generate. + alu_g(3 downto 0) <= not alu_ng(3 downto 0); + core_ng <= not ( alu_g(3) + or (alu_p(3) and alu_g(2)) + or (alu_p(3) and alu_p(2) and alu_g(1)) + or (alu_p(3) and alu_p(2) and alu_p(1) and alu_g(0))); + + -- Sign, zero, overflow and carry out. + -- core_nsign <= not alu_f(3); + core_zero <= not ( alu_f(3) + or alu_f(2) + or alu_f(1) + or alu_f(0)); + core_over <= alu_cout xor alu_over; + + + -- ************************* ACCU control ************************ + + -- Compute of ACCU write enable. + acc_wen <= (not i(6)) and ((not i(7)) or i(8)); + + -- ACCU shifter I/O. + -- acc_i_up <= not core_acc_i_nup; + -- acc_i_down <= not core_acc_i_ndown; + -- core_acc_o_nup <= not acc_scout; + -- core_acc_o_ndown <= not acc_q_down; + + + -- ************************** RAM control ************************ + + + -- Compute of RAM write enable. + ram_wri <= fonc_mode and (i(8) or i(7)); + + -- RAM and ACCU I/O plots controls. + core_sh_right <= i(8) and (not i(7)); + core_sh_left <= i(8) and i(7) ; + -- RAM shifter I/O. + -- ram_i_up <= not core_ram_i_nup; + -- ram_i_down <= not core_ram_i_ndown; + -- core_ram_o_ndown <= not alu_f(0); + -- core_ram_o_nup <= not alu_f(3); + + oe <= not noe; + + -- + + + WITH a(3 downto 0) SELECT + deca<= B"0000000000000001" WHEN X"0", + B"0000000000000010" WHEN X"1", + B"0000000000000100" WHEN X"2", + B"0000000000001000" WHEN X"3", + B"0000000000010000" WHEN X"4", + B"0000000000100000" WHEN X"5", + B"0000000001000000" WHEN X"6", + B"0000000010000000" WHEN X"7", + B"0000000100000000" WHEN X"8", + B"0000001000000000" WHEN X"9", + B"0000010000000000" WHEN X"A", + B"0000100000000000" WHEN X"B", + B"0001000000000000" WHEN X"C", + B"0010000000000000" WHEN X"D", + B"0100000000000000" WHEN X"E", + B"1000000000000000" WHEN OTHERS; + WITH b(3 downto 0) SELECT + interm<= B"0000000000000001" WHEN X"0", + B"0000000000000010" WHEN X"1", + B"0000000000000100" WHEN X"2", + B"0000000000001000" WHEN X"3", + B"0000000000010000" WHEN X"4", + B"0000000000100000" WHEN X"5", + B"0000000001000000" WHEN X"6", + B"0000000010000000" WHEN X"7", + B"0000000100000000" WHEN X"8", + B"0000001000000000" WHEN X"9", + B"0000010000000000" WHEN X"A", + B"0000100000000000" WHEN X"B", + B"0001000000000000" WHEN X"C", + B"0010000000000000" WHEN X"D", + B"0100000000000000" WHEN X"E", + B"1000000000000000" WHEN OTHERS; + + decb <= interm; + + WITH ram_wri SELECT + decwb<= interm WHEN B"1", + B"0000000000000000" WHEN OTHERS; + +END behavior_data_flow; + + diff --git a/alliance/src/documentation/alliance-examples/amd2901/amd2901_dpt.c b/alliance/src/documentation/alliance-examples/amd2901/amd2901_dpt.c new file mode 100644 index 00000000..2a2e4ba5 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/amd2901/amd2901_dpt.c @@ -0,0 +1,387 @@ + + +# include + + +#define getbit(val,bit) (((val) >> (bit))%2) + + +extern int main() +{ + long i; + + + /* Generate all the operators required for the register file. */ + GENLIB_MACRO (DPGEN_INV , "model_inv_x8", F_PLACE, 4, 8); + GENLIB_MACRO (DPGEN_DFF , "model_dff" , F_PLACE, 4); + GENLIB_MACRO (DPGEN_NBUSE, "model_nbuse" , F_PLACE, 4); + + /* Generate all the operators required */ + + GENLIB_MACRO (DPGEN_MUX2 , "model_mux2", F_PLACE, 4, 2); + GENLIB_MACRO (DPGEN_NAND2MASK, "model_nand2mask_0000", F_PLACE, 4,"0b0000"); + GENLIB_MACRO (DPGEN_XNOR2MASK, "model_xnor2mask_1111", F_PLACE, 4, "0b1111"); + GENLIB_MACRO (DPGEN_NAND2 , "model_nand2", F_PLACE, 4, 4); /* 1 ou 4 */ + GENLIB_MACRO (DPGEN_NOR2MASK , "model_nor2mask_1111", F_PLACE, 4,"0b1111"); + GENLIB_MACRO (DPGEN_NMUX2 , "model_nmux2", F_PLACE, 4,2); + GENLIB_MACRO (DPGEN_INV , "model_inv", F_PLACE, 4,1); + GENLIB_MACRO (DPGEN_NOR2 , "model_nor2", F_PLACE, 4, 4); /* 1 ou 4 */ + GENLIB_MACRO (DPGEN_XOR2 , "model_xor2", F_PLACE, 4, 4); /* 1 ou 4 */ + GENLIB_MACRO (DPGEN_XNOR2 , "model_xnor2", F_PLACE, 4, 4); /* 1 ou 4 */ + GENLIB_MACRO (DPGEN_DFFT , "model_dfft", F_PLACE, 4); /* 1 ou 4 */ + + + /* Netlist description. */ + GENLIB_DEF_LOFIG ("amd2901_dpt"); + +/* Command for selecting operands R and S.*/ + GENLIB_LOCON ("ops_mx[2:0]" , IN , "ops_mx[2:0]"); + GENLIB_LOCON ("opr_mx[1:0]" , IN , "opr_mx[1:0]"); + +/* ALU commands and auxiliary terminals. */ + GENLIB_LOCON ("alu_k[4:0]" , IN , "alu_k[4:0]"); + GENLIB_LOCON ("alu_cin" , IN , "alu_cin") ; + GENLIB_LOCON ("alu_cout", OUT , "alu_cout") ; + GENLIB_LOCON ("alu_over" , INOUT , "alu_over"); + +/* RAM, ACCU shifter commands and auxiliary terminals.*/ + GENLIB_LOCON ("ram_sh[1:0]" , IN , "ram_sh[1:0]") ; + GENLIB_LOCON ("acc_sh[1:0]" , IN , "acc_sh[1:0]") ; + +/* RAM shifter inputs.*/ + GENLIB_LOCON ("ram_i_up" , IN , "ram_i_up"); + GENLIB_LOCON ("ram_i_down" , IN , "ram_i_down"); + +/* ACCU shifter inputs.*/ + GENLIB_LOCON ("acc_i_up" , IN , "acc_i_up" ) ; + GENLIB_LOCON ("acc_i_down" , IN , "acc_i_down") ; + +/* ACCU shifter outputs ("acc_scout" is "acc_q_up").*/ + GENLIB_LOCON ("acc_q_down" , OUT , "acc_q_down"); + +/* Output multiplexer commnand (for X bus).*/ + GENLIB_LOCON ("out_mx" , IN , "out_mx"); + +/* ACCU controls terminals.*/ + GENLIB_LOCON ("acc_ck" , IN , "acc_ck" ); + GENLIB_LOCON ("acc_wen" , IN , "acc_wen" ); + GENLIB_LOCON ("acc_test" , IN , "acc_test" ); + GENLIB_LOCON ("acc_scin" , IN , "acc_scin") ; /* Scan-Path input.*/ + GENLIB_LOCON ("acc_scout", INOUT ,"acc_scout"); /* Scan-Path output.*/ + +/* Register file controls terminals.*/ + GENLIB_LOCON ("ram_ck[15:0]", IN ,"ram_ck[15:0]") ; /* Register clocks (ck) */ + GENLIB_LOCON ("b_w[15:0]" , IN , "b_w[15:0]") ; /* Write enable */ + GENLIB_LOCON ("a[15:0]" , IN , "a[15:0]") ; /* Register A address. */ + GENLIB_LOCON ("b[15:0]" , IN , "b[15:0]") ; /* Register B address. */ + +/* Data buses terminals.*/ +GENLIB_LOCON ("opr_d[3:0]" , IN ,"opr_d[3:0]"); +GENLIB_LOCON ("alu_f[3:0]" , INOUT ,"alu_f[3:0]"); +GENLIB_LOCON ("alu_np[3:0]" , OUT ,"alu_np[3:0]"); +GENLIB_LOCON ("alu_ng[3:0]" , OUT , "alu_ng[3:0]"); +GENLIB_LOCON ("out_x[3:0]" ,OUT , "out_x[3:0]"); + + /* Power supply connectors. */ + GENLIB_LOCON ("vdd", IN , "vdd"); + GENLIB_LOCON ("vss", IN , "vss"); + + + /* Register file description. */ + for (i = 0; i < 16; i++) + { + /* Register part. */ + GENLIB_LOINS ("model_dff", GENLIB_NAME("ram_reg%ld",i), + GENLIB_ELM ("b_w", i), + GENLIB_ELM ("ram_ck" , i), + "ram_d[3:0]", + GENLIB_NAME ("ram_q%ld[3:0]", i), + "vdd", "vss", NULL); + + /* Tristate for A output. */ + GENLIB_LOINS ("model_nbuse", GENLIB_NAME ("ram_ntsa%ld",i), + GENLIB_ELM ("a", i), + GENLIB_NAME ("ram_q%ld[3:0]", i), + "ram_nra[3:0]", + "vdd", "vss", NULL); + + /* Tristate for B output. */ + GENLIB_LOINS ("model_nbuse", GENLIB_NAME("ram_ntsb%ld",i), + GENLIB_ELM ("b", i), + GENLIB_NAME ("ram_q%ld[3:0]", i), + "ram_nrb[3:0]", + "vdd", "vss", NULL); + } + + + /* Output drivers for A & B output. */ + GENLIB_LOINS ("model_inv_x8", "inv_ra", + "ram_nra[3:0]", + "ram_ra[3:0]", + "vdd", "vss", NULL); + GENLIB_LOINS ("model_inv_x8", "inv_rb", + "ram_nrb[3:0]", + "ram_rb[3:0]", + "vdd", "vss", NULL); + + /* -------------------------------------------------------------- + * RAM shifter. + */ + + GENLIB_LOINS ("model_nmux2", "ram_nmux_0", + "ram_sh[0]", + "ram_i_up", "alu_f[3:1]", /* i1 */ + "alu_f[2:0]", "ram_i_down", /* i0 */ + "ram_nmux_0[3:0]", + "vdd", "vss", NULL); + + GENLIB_LOINS ("model_inv", "ram_inv_1", + "alu_f[3:0]", /* i2 */ + "ram_inv_1[3:0]", + "vdd", "vss", NULL); + + GENLIB_LOINS ("model_nmux2", "ram_nmux_1", + "ram_sh[1]", + "ram_inv_1[3:0]", + "ram_nmux_0[3:0]", + "ram_d[3:0]", + "vdd", "vss", NULL); + + + + /* *********************** Operand S ************************ */ + + GENLIB_LOINS ("model_nmux2", "ops_nmux_0", + "ops_mx[0]", + "ram_rb[3:0]", /* i1 */ + "acc_scout", "acc_q[2:1]", "acc_q_down", /* i0 */ + "ops_nmux_0[3:0]", + "vdd", "vss", NULL); + + GENLIB_LOINS ("model_inv", "ops_inv_1", + "ram_ra[3:0]", /* i2 */ + "ops_inv_1[3:0]", + "vdd", "vss", NULL); + + GENLIB_LOINS ("model_nmux2", "ops_nmux_1", + "ops_mx[1]", + "ops_inv_1[3:0]", + "ops_nmux_0[3:0]", + "ops_it[3:0]", + "vdd", "vss", NULL); + + GENLIB_LOINS ("model_nand2mask_0000", "ops_na2mask_0b0000", + "ops_mx[2]" , + "ops_it[3:0]", + "ops_ns[3:0]", + "vdd", "vss", NULL); + + +/* *********************** Operand R ************************ */ + + + GENLIB_LOINS ("model_mux2", "opr_mux", + "opr_mx[0]", + "opr_d[3:0]", /* i1 */ + "ram_ra[3:0]", /* i0 */ + "opr_it[3:0]", + "vdd", "vss", NULL); + + GENLIB_LOINS ("model_nand2mask_0000", "opr_na2mask_0b0000", + "opr_mx[1]" , + "opr_it[3:0]", + "opr_nr[3:0]", + "vdd", "vss", NULL); + +/* *********************** ALU Description ****************** */ + + GENLIB_LOINS ("model_xnor2mask_1111", "alu_xr2_opnr", + "alu_k[0]" , + "opr_nr[3:0]", + "alu_xr[3:0]", + "vdd", "vss", NULL); + + GENLIB_LOINS ("model_xnor2mask_1111", "alu_xr2_opns", + "alu_k[1]" , + "ops_ns[3:0]", + "alu_xs[3:0]", + "vdd", "vss", NULL); + + +/* Compute of "generate". */ + GENLIB_LOINS ("model_nand2", "alu_na2_ng", + "alu_xr[3:0]", + "alu_xs[3:0]", + "alu_ng[3:0]", + "vdd", "vss", NULL); + +/* Compute of "propagate". */ + GENLIB_LOINS ("model_nor2", "alu_no2_np", + "alu_xr[3:0]", + "alu_xs[3:0]", + "alu_np[3:0]", + "vdd", "vss", NULL); + +GENLIB_LOINS ("model_inv", "alu_n1_p" , + "alu_np[3:0]", + "alu_p[3:0]", + "vdd", "vss", NULL); + /* Compute of carry. */ + GENLIB_LOINS ("model_nand2", "alu_na2_npc" , + "alu_p[3:0]", + "alu_over", "alu_carry[2:1]", "alu_cin", + "alu_npc[3:0]", + "vdd", "vss", NULL); + + GENLIB_LOINS ("model_nand2", "alu_na2_carry", + "alu_ng[3:0]", + "alu_npc[3:0]", + "alu_cout", "alu_over", "alu_carry[2:1]", + "vdd", "vss", NULL); + + /* Logical and arithmetical operators. */ + GENLIB_LOINS ("model_nor2mask_1111", "alu_no2_and", + "alu_k[2]" , + "alu_ng[3:0]", + "alu_r_and_s[3:0]", + "vdd", "vss", NULL); + + GENLIB_LOINS ("model_nor2mask_1111", "alu_no2_or" , + "alu_k[3]" , + "alu_np[3:0]", + "alu_r_or_s[3:0]", + "vdd", "vss", NULL); + + GENLIB_LOINS ("model_nor2mask_1111", "alu_no2_add", + "alu_k[4]" , + "alu_over", "alu_carry[2:1]", "alu_cin", + "alu_r_add_s[3:0]", + "vdd", "vss", NULL); + + /* Output. */ + GENLIB_LOINS ("model_xor2", "alu_nxr2_op", + "alu_r_and_s[3:0]", + "alu_r_or_s[3:0]", + "alu_r_op_s[3:0]", + "vdd", "vss", NULL); + + GENLIB_LOINS ("model_xnor2", "alu_nxr2_f" , + "alu_r_op_s[3:0]", + "alu_r_add_s[3:0]", + "alu_f[3:0]", + "vdd", "vss", NULL); + + /* ******************** ACCU Description ******************** */ + + GENLIB_LOINS ("model_nmux2", "accu_nmux_0", + "acc_sh[0]", + "acc_i_up", "acc_scout", "acc_q[2:1]", /* i1 : down */ + "acc_q[2:1]", "acc_q_down", "acc_i_down", /* i0 : up */ + "accu_nmux_0[3:0]", + "vdd", "vss", NULL); + + GENLIB_LOINS ("model_inv", "accu_inv_1", + "alu_f[3:0]", /* i2: no */ + "accu_inv_1[3:0]", + "vdd", "vss", NULL); + + GENLIB_LOINS ("model_nmux2", "accu_nmux_1", + "acc_sh[1]", + "accu_inv_1[3:0]", + "accu_nmux_0[3:0]", + "acc_d[3:0]", + "vdd", "vss", NULL); + + GENLIB_LOINS ("model_dfft", "acc_reg", + "acc_test" , + "acc_scin" , + "acc_wen", + "acc_ck" , + "acc_d[3:0]", + "acc_scout", "acc_q[2:1]", "acc_q_down", + "vdd", "vss", NULL); + + /* ******************* Output Multiplexer ******************* */ + + GENLIB_LOINS ("model_mux2", "out_mx", + "out_mx" , + "ram_ra[3:0]", /* i1 */ + "alu_f[3:0]", /* i0 */ + "out_x[3:0]", + "vdd", "vss", NULL); + + + /* End of netlist description. */ + GENLIB_SAVE_LOFIG (); + + /* Partial placement description. */ + GENLIB_DEF_PHFIG ("amd2901_dpt"); + + + for (i = 0; i < 16; i++) + { + /* Register part. */ + if (!(i % 8)) { + if (!i) { + GENLIB_PLACE ("model_dff", GENLIB_NAME ("ram_reg%ld",i), NOSYM, 0, 0); + } else { + GENLIB_DEF_PHINS (GENLIB_NAME ("ram_reg%ld", i - 8)); + GENLIB_PLACE_TOP ("model_dff", GENLIB_NAME ("ram_reg%ld",i), NOSYM); + } + } else { + GENLIB_PLACE_RIGHT ("model_dff", GENLIB_NAME ("ram_reg%ld",i), NOSYM); + } + + GENLIB_PLACE_RIGHT ("model_nbuse", GENLIB_NAME ("ram_ntsa%ld",i), NOSYM); + GENLIB_PLACE_RIGHT ("model_nbuse", GENLIB_NAME ("ram_ntsb%ld",i), NOSYM); + } + + + GENLIB_PLACE("model_nmux2","ram_nmux_0",NOSYM, 500,700); + GENLIB_PLACE_RIGHT ("model_nmux2", "ram_nmux_1", NOSYM); + GENLIB_PLACE_RIGHT ("model_nmux2", "ops_nmux_0", NOSYM); + GENLIB_PLACE_RIGHT ("model_nmux2", "ops_nmux_1", NOSYM); + GENLIB_PLACE_RIGHT ("model_mux2", "opr_mux", NOSYM); +#if 0 + GENLIB_PLACE_RIGHT ("model_inv", "ram_inv_1", NOSYM); + + + /* *********************** Operand S ************************ */ + GENLIB_PLACE_RIGHT ("model_inv", "ops_inv_1", NOSYM); + GENLIB_PLACE_RIGHT ("model_nand2mask_0000", "ops_na2mask_0b0000", NOSYM); + +/* *********************** Operand R ************************ */ + GENLIB_PLACE_RIGHT ("model_nand2mask_0000", "opr_na2mask_0b0000", NOSYM); + +/* *********************** ALU Description ****************** */ + GENLIB_PLACE_RIGHT ("model_xnor2mask_1111", "alu_xr2_opnr", NOSYM); + GENLIB_PLACE_RIGHT ("model_xnor2mask_1111", "alu_xr2_opns", NOSYM); + +/* Compute of "generate". */ + +/* Compute of "propagate". */ + +/* Compute of carry. */ +/* Logical and arithmetical operators. */ +/* Output. */ + GENLIB_PLACE_RIGHT ("model_xor2", "alu_nxr2_op", NOSYM); + GENLIB_PLACE_RIGHT ("model_xnor2", "alu_nxr2_f" , NOSYM); + +/* ******************** ACCU Description ******************** */ +#endif + GENLIB_PLACE_RIGHT ("model_nmux2", "accu_nmux_0", NOSYM); + GENLIB_PLACE_RIGHT ("model_nmux2", "accu_nmux_1", NOSYM); + GENLIB_PLACE_RIGHT ("model_dfft", "acc_reg", NOSYM); + +/* ******************* Output Multiplexer ******************* */ + GENLIB_PLACE_RIGHT ("model_mux2", "out_mx", NOSYM); + + GENLIB_DEF_AB (0, 0, 0, 0); + + + /* End of placement description. */ + GENLIB_SAVE_PHFIG (); + + /* A good C program must always terminate by an "exit(0)". */ + exit(0); +} diff --git a/alliance/src/documentation/alliance-examples/amd2901/amd2901_dpt.vbe b/alliance/src/documentation/alliance-examples/amd2901/amd2901_dpt.vbe new file mode 100644 index 00000000..1cda72de --- /dev/null +++ b/alliance/src/documentation/alliance-examples/amd2901/amd2901_dpt.vbe @@ -0,0 +1,566 @@ +ENTITY amd2901_dpt IS + +PORT( + -- Command for selecting operands R and S. + ops_mx : in BIT_VECTOR(2 downto 0); + opr_mx : in BIT_VECTOR(1 downto 0); + + -- ALU commands and auxiliary terminals. + alu_k : in BIT_VECTOR(4 downto 0); + alu_cin : in BIT; + alu_cout : out BIT; + alu_over : inout BIT; + + -- RAM, ACCU shifter commands and auxiliary terminals. + ram_sh : in BIT_VECTOR(1 downto 0); + acc_sh : in BIT_VECTOR(1 downto 0); + -- RAM shifter inputs. + ram_i_up : in BIT; + ram_i_down : in BIT; + -- ACCU shifter inputs. + acc_i_up : in BIT; + acc_i_down : in BIT; + -- ACCU shifter outputs ("acc_scout" is "acc_q_up"). + acc_q_down : out BIT; + + -- Output multiplexer commnand (for X bus). + out_mx : in BIT; + + -- ACCU controls terminals. + acc_ck : in BIT; + acc_wen : in BIT; + acc_test : in BIT; + acc_scin : in BIT; -- Scan-Path input. + acc_scout : inout BIT; -- Scan-Path output. + + -- Register file controls terminals. + ram_ck : in BIT_VECTOR(15 downto 0) ; -- Register clocks (ck). + b_w : in BIT_VECTOR(15 downto 0) ; -- Write enable + a : in BIT_VECTOR(15 downto 0) ; -- Register A address. + b : in BIT_VECTOR(15 downto 0) ; -- Register B address. + +-- register_file_test : IN BIT_VECTOR(15 downto 0) ; -- register_file_test[15:0] +-- register_file_scout : OUT BIT_VECTOR(15 downto 0) ; -- Scan path for ram +-- register_file_scin : IN BIT_VECTOR(15 downto 0) ; -- Scan path for ram + + -- Data buses terminals. + opr_d : in BIT_VECTOR(3 downto 0); + alu_f : inout BIT_VECTOR(3 downto 0); + alu_np : out BIT_VECTOR(3 downto 0); + alu_ng : out BIT_VECTOR(3 downto 0); + out_x : out BIT_VECTOR(3 downto 0); + + -- Power supply connectors. + vdd : in BIT; + vss : in BIT + ); + +END amd2901_dpt; + + +ARCHITECTURE behavior_data_flow OF amd2901_dpt IS + + -- Internals bus. + SIGNAL ops_ns : BIT_VECTOR(3 downto 0); + SIGNAL opr_nr : BIT_VECTOR(3 downto 0); + SIGNAL ram_d : BIT_VECTOR(3 downto 0); + SIGNAL acc_d : BIT_VECTOR(3 downto 0); + + -- Internal registers. + -- ACCU master/slave. + -- SIGNAL acc_m_q : REG_VECTOR(3 downto 0) REGISTER; + SIGNAL acc_s_q : REG_VECTOR(3 downto 0) REGISTER; + SIGNAL acc_m_q : REG_VECTOR(3 downto 0) REGISTER; + -- Internal ACCU clock signals. + SIGNAL acc_wmd : BIT; + SIGNAL acc_wmt : BIT; + SIGNAL acc_ws : BIT; + -- RAM SIGNALS + SIGNAL ram_adra : BIT_VECTOR(15 DOWNTO 0); + SIGNAL ram_adrb : BIT_VECTOR(15 DOWNTO 0); + -- RAM masters. + SIGNAL ram_m_r0 : REG_VECTOR(3 downto 0) REGISTER; + SIGNAL ram_m_r1 : REG_VECTOR(3 downto 0) REGISTER; + SIGNAL ram_m_r2 : REG_VECTOR(3 downto 0) REGISTER; + SIGNAL ram_m_r3 : REG_VECTOR(3 downto 0) REGISTER; + SIGNAL ram_m_r4 : REG_VECTOR(3 downto 0) REGISTER; + SIGNAL ram_m_r5 : REG_VECTOR(3 downto 0) REGISTER; + SIGNAL ram_m_r6 : REG_VECTOR(3 downto 0) REGISTER; + SIGNAL ram_m_r7 : REG_VECTOR(3 downto 0) REGISTER; + SIGNAL ram_m_r8 : REG_VECTOR(3 downto 0) REGISTER; + SIGNAL ram_m_r9 : REG_VECTOR(3 downto 0) REGISTER; + SIGNAL ram_m_r10 : REG_VECTOR(3 downto 0) REGISTER; + SIGNAL ram_m_r11 : REG_VECTOR(3 downto 0) REGISTER; + SIGNAL ram_m_r12 : REG_VECTOR(3 downto 0) REGISTER; + SIGNAL ram_m_r13 : REG_VECTOR(3 downto 0) REGISTER; + SIGNAL ram_m_r14 : REG_VECTOR(3 downto 0) REGISTER; + SIGNAL ram_m_r15 : REG_VECTOR(3 downto 0) REGISTER; + -- RAM slaves. + SIGNAL ram_s_r0 : REG_VECTOR(3 downto 0) REGISTER; + SIGNAL ram_s_r1 : REG_VECTOR(3 downto 0) REGISTER; + SIGNAL ram_s_r2 : REG_VECTOR(3 downto 0) REGISTER; + SIGNAL ram_s_r3 : REG_VECTOR(3 downto 0) REGISTER; + SIGNAL ram_s_r4 : REG_VECTOR(3 downto 0) REGISTER; + SIGNAL ram_s_r5 : REG_VECTOR(3 downto 0) REGISTER; + SIGNAL ram_s_r6 : REG_VECTOR(3 downto 0) REGISTER; + SIGNAL ram_s_r7 : REG_VECTOR(3 downto 0) REGISTER; + SIGNAL ram_s_r8 : REG_VECTOR(3 downto 0) REGISTER; + SIGNAL ram_s_r9 : REG_VECTOR(3 downto 0) REGISTER; + SIGNAL ram_s_r10 : REG_VECTOR(3 downto 0) REGISTER; + SIGNAL ram_s_r11 : REG_VECTOR(3 downto 0) REGISTER; + SIGNAL ram_s_r12 : REG_VECTOR(3 downto 0) REGISTER; + SIGNAL ram_s_r13 : REG_VECTOR(3 downto 0) REGISTER; + SIGNAL ram_s_r14 : REG_VECTOR(3 downto 0) REGISTER; + SIGNAL ram_s_r15 : REG_VECTOR(3 downto 0) REGISTER; + -- Internal RAM clocks signals. + -- Masters write enable. + SIGNAL ram_wmd0 :BIT; + SIGNAL ram_wmd1 :BIT; + SIGNAL ram_wmd2 :BIT; + SIGNAL ram_wmd3 :BIT; + SIGNAL ram_wmd4 :BIT; + SIGNAL ram_wmd5 :BIT; + SIGNAL ram_wmd6 :BIT; + SIGNAL ram_wmd7 :BIT; + SIGNAL ram_wmd8 :BIT; + SIGNAL ram_wmd9 :BIT; + SIGNAL ram_wmd10 :BIT; + SIGNAL ram_wmd11 :BIT; + SIGNAL ram_wmd12 :BIT; + SIGNAL ram_wmd13 :BIT; + SIGNAL ram_wmd14 :BIT; + SIGNAL ram_wmd15 :BIT; + -- Slaves write enable. + SIGNAL ram_ws0 :BIT; + SIGNAL ram_ws1 :BIT; + SIGNAL ram_ws2 :BIT; + SIGNAL ram_ws3 :BIT; + SIGNAL ram_ws4 :BIT; + SIGNAL ram_ws5 :BIT; + SIGNAL ram_ws6 :BIT; + SIGNAL ram_ws7 :BIT; + SIGNAL ram_ws8 :BIT; + SIGNAL ram_ws9 :BIT; + SIGNAL ram_ws10 :BIT; + SIGNAL ram_ws11 :BIT; + SIGNAL ram_ws12 :BIT; + SIGNAL ram_ws13 :BIT; + SIGNAL ram_ws14 :BIT; + SIGNAL ram_ws15 :BIT; + -- Output mux bus RA and RB. + SIGNAL ram_ra : MUX_VECTOR(3 downto 0) BUS; + SIGNAL ram_rb : MUX_VECTOR(3 downto 0) BUS; + -- Internal ALU signals. + SIGNAL alu_cry : BIT_VECTOR(4 downto 0); + SIGNAL alu_s : BIT_VECTOR(3 downto 0); + SIGNAL alu_r : BIT_VECTOR(3 downto 0); + + + + SIGNAL sel_acc : BIT_VECTOR(1 downto 0); + SIGNAL sig_acc : BIT_VECTOR(3 downto 0); + + SIGNAL sig_ram0 : BIT_VECTOR(3 downto 0); + SIGNAL sig_ram1 : BIT_VECTOR(3 downto 0); + SIGNAL sig_ram2 : BIT_VECTOR(3 downto 0); + SIGNAL sig_ram3 : BIT_VECTOR(3 downto 0); + SIGNAL sig_ram4 : BIT_VECTOR(3 downto 0); + SIGNAL sig_ram5 : BIT_VECTOR(3 downto 0); + SIGNAL sig_ram6 : BIT_VECTOR(3 downto 0); + SIGNAL sig_ram7 : BIT_VECTOR(3 downto 0); + SIGNAL sig_ram8 : BIT_VECTOR(3 downto 0); + SIGNAL sig_ram9 : BIT_VECTOR(3 downto 0); + SIGNAL sig_ram10 : BIT_VECTOR(3 downto 0); + SIGNAL sig_ram11 : BIT_VECTOR(3 downto 0); + SIGNAL sig_ram12 : BIT_VECTOR(3 downto 0); + SIGNAL sig_ram13 : BIT_VECTOR(3 downto 0); + SIGNAL sig_ram14 : BIT_VECTOR(3 downto 0); + SIGNAL sig_ram15 : BIT_VECTOR(3 downto 0); + + SIGNAL ram_ck0 :BIT; + SIGNAL ram_ck1 :BIT; + SIGNAL ram_ck2 :BIT; + SIGNAL ram_ck3 :BIT; + SIGNAL ram_ck4 :BIT; + SIGNAL ram_ck5 :BIT; + SIGNAL ram_ck6 :BIT; + SIGNAL ram_ck7 :BIT; + SIGNAL ram_ck8 :BIT; + SIGNAL ram_ck9 :BIT; + SIGNAL ram_ck10 :BIT; + SIGNAL ram_ck11 :BIT; + SIGNAL ram_ck12 :BIT; + SIGNAL ram_ck13 :BIT; + SIGNAL ram_ck14 :BIT; + SIGNAL ram_ck15 :BIT; + +BEGIN + + + -- ******************* RAM shifter description ******************* + + -- RAM shifter control code : + -- 1) "00" : UP shift. + -- 2) "01" : DOWN shift. + -- 3) either "10" or "11" : NO shift. + WITH ram_sh(1 downto 0) SELECT + ram_d <= alu_f(2 downto 0)&ram_i_down WHEN B"00", + ram_i_up&alu_f(3 downto 1) WHEN B"01", + alu_f(3 downto 0) WHEN B"10" + | B"11"; + + + -- ****************** ACCU shifter description ******************* + + acc_q_down <= acc_s_q(0); + + -- ACCU shifter control code : + -- 1) "00" : UP shift accu. + -- 2) "01" : DOWN shift accu. + -- 3) either "10" or "11" : write accu with no shift. + WITH acc_sh(1 downto 0) SELECT + acc_d <= acc_s_q(2 downto 0)&acc_i_down WHEN B"00", + acc_i_up&acc_s_q(3 downto 1) WHEN B"01", + alu_f(3 downto 0) WHEN B"10" + | B"11"; + + + -- ****************** S multiplexer description ****************** + + WITH ops_mx(2 downto 0) SELECT + ops_ns <= not acc_s_q WHEN B"000", + not ram_rb WHEN B"001", + not ram_ra WHEN B"010" + | B"011", + "1111" WHEN B"100" + | B"101" + | B"110" + | B"111"; + + + -- ****************** R multiplexer description ****************** + + WITH opr_mx(1 downto 0) SELECT + opr_nr <= not ram_ra WHEN B"00", + not opr_d WHEN B"01", + "1111" WHEN B"10" + | B"11"; + + + -- ****************** X multiplexer description ****************** + + WITH out_mx SELECT + out_x <= alu_f WHEN B"0", + ram_ra WHEN B"1"; + + + -- *********************** ALU description *********************** + + alu_cry(0) <= alu_cin; + alu_cout <= alu_cry(4); + alu_over <= alu_cry(3); + + -- Inversion of R and S operands. + alu_s <= not ops_ns WHEN alu_k(1) = '0' ELSE ops_ns; + alu_r <= not opr_nr WHEN alu_k(0) = '0' ELSE opr_nr; + + -- Compute of nP and nG. + alu_np <= not (alu_s or alu_r); + alu_ng <= not (alu_s and alu_r); + + -- Arithmetic adder description. + alu_cry(4 downto 1) <= (alu_s and alu_r ) + or (alu_s and alu_cry(3 downto 0)) + or (alu_cry(3 downto 0) and alu_r ); + + -- Select the ALU output. + WITH alu_k(4 downto 2) SELECT + alu_f <= alu_s xor alu_r xor alu_cry(3 downto 0) WHEN B"000", + (alu_s or alu_r) xor alu_cry(3 downto 0) WHEN B"001", + (alu_s and alu_r) xor alu_cry(3 downto 0) WHEN B"010", + alu_cry(3 downto 0) WHEN B"011", + not (alu_s xor alu_r) WHEN B"100", + not (alu_s or alu_r) WHEN B"101", + not (alu_s and alu_r) WHEN B"110", + B"1111" WHEN B"111"; + + + + -- ********************** ACCU description ************************ + -- Modification tenant compte du front montant de l'horloge + + acc_wmt <= acc_test; + acc_wmd <= (not acc_test) and acc_wen; + acc_ws <= not acc_ck; + acc_scout <= acc_s_q(3); + + sel_acc <= acc_wmt & acc_wmd ; + + WITH sel_acc SELECT + sig_acc <= acc_s_q(2 downto 0) & acc_scin WHEN B"10" , -- Mode chemin de tests + acc_d WHEN B"01" , -- Mode normal + acc_s_q WHEN OTHERS ; -- Reprise du registre + + -- A chaque cycle, on ecrit dans acc_s_q + + -- Echantillonnage lorsque ck=0 et memorisation sur front montant + acc_ck:BLOCK(acc_ws = '1') + BEGIN + acc_m_q <= GUARDED sig_acc; + END BLOCK acc_ck; + + -- Slave register write. + -- Echantillonnage lorsque ck=1 et memorisation sur front descendant + acc_ws:BLOCK(acc_ck = '1') + BEGIN + acc_s_q <= GUARDED acc_m_q; + END BLOCK acc_ws; + + -- *********************** RAM description *********************** + + -- Select B register. + ram_adrb(0 ) <= b(0 ) ; + ram_adrb(1 ) <= b(1 ) ; + ram_adrb(2 ) <= b(2 ) ; + ram_adrb(3 ) <= b(3 ) ; + ram_adrb(4 ) <= b(4 ) ; + ram_adrb(5 ) <= b(5 ) ; + ram_adrb(6 ) <= b(6 ) ; + ram_adrb(7 ) <= b(7 ) ; + ram_adrb(8 ) <= b(8 ) ; + ram_adrb(9 ) <= b(9 ) ; + ram_adrb(10) <= b(10) ; + ram_adrb(11) <= b(11) ; + ram_adrb(12) <= b(12) ; + ram_adrb(13) <= b(13) ; + ram_adrb(14) <= b(14) ; + ram_adrb(15) <= b(15) ; + + -- Select A register. + ram_adra(0 ) <= a(0 ) ; + ram_adra(1 ) <= a(1 ) ; + ram_adra(2 ) <= a(2 ) ; + ram_adra(3 ) <= a(3 ) ; + ram_adra(4 ) <= a(4 ) ; + ram_adra(5 ) <= a(5 ) ; + ram_adra(6 ) <= a(6 ) ; + ram_adra(7 ) <= a(7 ) ; + ram_adra(8 ) <= a(8 ) ; + ram_adra(9 ) <= a(9 ) ; + ram_adra(10) <= a(10) ; + ram_adra(11) <= a(11) ; + ram_adra(12) <= a(12) ; + ram_adra(13) <= a(13) ; + ram_adra(14) <= a(14) ; + ram_adra(15) <= a(15) ; + + + -- Write master enable signals for b + ram_wmd0 <= b_w(0 ); + ram_wmd1 <= b_w(1 ); + ram_wmd2 <= b_w(2 ); + ram_wmd3 <= b_w(3 ); + ram_wmd4 <= b_w(4 ); + ram_wmd5 <= b_w(5 ); + ram_wmd6 <= b_w(6 ); + ram_wmd7 <= b_w(7 ); + ram_wmd8 <= b_w(8 ); + ram_wmd9 <= b_w(9 ); + ram_wmd10 <= b_w(10); + ram_wmd11 <= b_w(11); + ram_wmd12 <= b_w(12); + ram_wmd13 <= b_w(13); + ram_wmd14 <= b_w(14); + ram_wmd15 <= b_w(15); + + -- Write slave enable signals. + ram_ws0 <= not ram_ck(0 ) ; + ram_ws1 <= not ram_ck(1 ) ; + ram_ws2 <= not ram_ck(2 ) ; + ram_ws3 <= not ram_ck(3 ) ; + ram_ws4 <= not ram_ck(4 ) ; + ram_ws5 <= not ram_ck(5 ) ; + ram_ws6 <= not ram_ck(6 ) ; + ram_ws7 <= not ram_ck(7 ) ; + ram_ws8 <= not ram_ck(8 ) ; + ram_ws9 <= not ram_ck(9 ) ; + ram_ws10 <= not ram_ck(10) ; + ram_ws11 <= not ram_ck(11) ; + ram_ws12 <= not ram_ck(12) ; + ram_ws13 <= not ram_ck(13) ; + ram_ws14 <= not ram_ck(14) ; + ram_ws15 <= not ram_ck(15) ; + + ram_ck0 <= ram_ck(0 ) ; + ram_ck1 <= ram_ck(1 ) ; + ram_ck2 <= ram_ck(2 ) ; + ram_ck3 <= ram_ck(3 ) ; + ram_ck4 <= ram_ck(4 ) ; + ram_ck5 <= ram_ck(5 ) ; + ram_ck6 <= ram_ck(6 ) ; + ram_ck7 <= ram_ck(7 ) ; + ram_ck8 <= ram_ck(8 ) ; + ram_ck9 <= ram_ck(9 ) ; + ram_ck10 <= ram_ck(10) ; + ram_ck11 <= ram_ck(11) ; + ram_ck12 <= ram_ck(12) ; + ram_ck13 <= ram_ck(13) ; + ram_ck14 <= ram_ck(14) ; + ram_ck15 <= ram_ck(15) ; + + + WITH ram_wmd0 SELECT + sig_ram0 <= ram_d WHEN B"1" , -- Mode ecriture + ram_s_r0 WHEN OTHERS ; + + WITH ram_wmd1 SELECT + sig_ram1 <= ram_d WHEN B"1" , -- Mode ecriture + ram_s_r1 WHEN OTHERS ; + + WITH ram_wmd2 SELECT + sig_ram2 <= ram_d WHEN B"1" , -- Mode ecriture + ram_s_r2 WHEN OTHERS ; + + WITH ram_wmd3 SELECT + sig_ram3 <= ram_d WHEN B"1" , -- Mode ecriture + ram_s_r3 WHEN OTHERS ; + + WITH ram_wmd4 SELECT + sig_ram4 <= ram_d WHEN B"1" , -- Mode ecriture + ram_s_r4 WHEN OTHERS ; + + WITH ram_wmd5 SELECT + sig_ram5 <= ram_d WHEN B"1" , -- Mode ecriture + ram_s_r5 WHEN OTHERS ; + + WITH ram_wmd6 SELECT + sig_ram6 <= ram_d WHEN B"1" , -- Mode ecriture + ram_s_r6 WHEN OTHERS ; + + WITH ram_wmd7 SELECT + sig_ram7 <= ram_d WHEN B"1" , -- Mode ecriture + ram_s_r7 WHEN OTHERS ; + + WITH ram_wmd8 SELECT + sig_ram8 <= ram_d WHEN B"1" , -- Mode ecriture + ram_s_r8 WHEN OTHERS ; + + WITH ram_wmd9 SELECT + sig_ram9 <= ram_d WHEN B"1" , -- Mode ecriture + ram_s_r9 WHEN OTHERS ; + + WITH ram_wmd10 SELECT + sig_ram10 <= ram_d WHEN B"1" , -- Mode ecriture + ram_s_r10 WHEN OTHERS ; + + WITH ram_wmd11 SELECT + sig_ram11 <= ram_d WHEN B"1" , -- Mode ecriture + ram_s_r11 WHEN OTHERS ; + + WITH ram_wmd12 SELECT + sig_ram12 <= ram_d WHEN B"1" , -- Mode ecriture + ram_s_r12 WHEN OTHERS ; + + WITH ram_wmd13 SELECT + sig_ram13 <= ram_d WHEN B"1" , -- Mode ecriture + ram_s_r13 WHEN OTHERS ; + + WITH ram_wmd14 SELECT + sig_ram14 <= ram_d WHEN B"1" , -- Mode ecriture + ram_s_r14 WHEN OTHERS ; + + WITH ram_wmd15 SELECT + sig_ram15 <= ram_d WHEN B"1" , -- Mode ecriture + ram_s_r15 WHEN OTHERS ; + + + -- Write registers description. + + -- Echantillonnage lorsque ck=0 et memorisation sur front montant +wm0 :BLOCK(ram_ws0 = '1') BEGIN ram_m_r0 <= GUARDED sig_ram0 ; END BLOCK wm0 ; +wm1 :BLOCK(ram_ws1 = '1') BEGIN ram_m_r1 <= GUARDED sig_ram1 ; END BLOCK wm1 ; +wm2 :BLOCK(ram_ws2 = '1') BEGIN ram_m_r2 <= GUARDED sig_ram2 ; END BLOCK wm2 ; +wm3 :BLOCK(ram_ws3 = '1') BEGIN ram_m_r3 <= GUARDED sig_ram3 ; END BLOCK wm3 ; +wm4 :BLOCK(ram_ws4 = '1') BEGIN ram_m_r4 <= GUARDED sig_ram4 ; END BLOCK wm4 ; +wm5 :BLOCK(ram_ws5 = '1') BEGIN ram_m_r5 <= GUARDED sig_ram5 ; END BLOCK wm5 ; +wm6 :BLOCK(ram_ws6 = '1') BEGIN ram_m_r6 <= GUARDED sig_ram6 ; END BLOCK wm6 ; +wm7 :BLOCK(ram_ws7 = '1') BEGIN ram_m_r7 <= GUARDED sig_ram7 ; END BLOCK wm7 ; +wm8 :BLOCK(ram_ws8 = '1') BEGIN ram_m_r8 <= GUARDED sig_ram8 ; END BLOCK wm8 ; +wm9 :BLOCK(ram_ws9 = '1') BEGIN ram_m_r9 <= GUARDED sig_ram9 ; END BLOCK wm9 ; +wm10:BLOCK(ram_ws10 = '1') BEGIN ram_m_r10 <= GUARDED sig_ram10 ; END BLOCK wm10; +wm11:BLOCK(ram_ws11 = '1') BEGIN ram_m_r11 <= GUARDED sig_ram11 ; END BLOCK wm11; +wm12:BLOCK(ram_ws12 = '1') BEGIN ram_m_r12 <= GUARDED sig_ram12 ; END BLOCK wm12; +wm13:BLOCK(ram_ws13 = '1') BEGIN ram_m_r13 <= GUARDED sig_ram13 ; END BLOCK wm13; +wm14:BLOCK(ram_ws14 = '1') BEGIN ram_m_r14 <= GUARDED sig_ram14 ; END BLOCK wm14; +wm15:BLOCK(ram_ws15 = '1') BEGIN ram_m_r15 <= GUARDED sig_ram15 ; END BLOCK wm15; + + -- Write slave registers description. + -- Echantillonnage lorsque ck=1 et memorisation sur front descendant +ws0 :BLOCK(ram_ck0 = '1') BEGIN ram_s_r0 <= GUARDED ram_m_r0 ; END BLOCK ws0 ; +ws1 :BLOCK(ram_ck1 = '1') BEGIN ram_s_r1 <= GUARDED ram_m_r1 ; END BLOCK ws1 ; +ws2 :BLOCK(ram_ck2 = '1') BEGIN ram_s_r2 <= GUARDED ram_m_r2 ; END BLOCK ws2 ; +ws3 :BLOCK(ram_ck3 = '1') BEGIN ram_s_r3 <= GUARDED ram_m_r3 ; END BLOCK ws3 ; +ws4 :BLOCK(ram_ck4 = '1') BEGIN ram_s_r4 <= GUARDED ram_m_r4 ; END BLOCK ws4 ; +ws5 :BLOCK(ram_ck5 = '1') BEGIN ram_s_r5 <= GUARDED ram_m_r5 ; END BLOCK ws5 ; +ws6 :BLOCK(ram_ck6 = '1') BEGIN ram_s_r6 <= GUARDED ram_m_r6 ; END BLOCK ws6 ; +ws7 :BLOCK(ram_ck7 = '1') BEGIN ram_s_r7 <= GUARDED ram_m_r7 ; END BLOCK ws7 ; +ws8 :BLOCK(ram_ck8 = '1') BEGIN ram_s_r8 <= GUARDED ram_m_r8 ; END BLOCK ws8 ; +ws9 :BLOCK(ram_ck9 = '1') BEGIN ram_s_r9 <= GUARDED ram_m_r9 ; END BLOCK ws9 ; +ws10:BLOCK(ram_ck10 = '1') BEGIN ram_s_r10 <= GUARDED ram_m_r10; END BLOCK ws10; +ws11:BLOCK(ram_ck11 = '1') BEGIN ram_s_r11 <= GUARDED ram_m_r11; END BLOCK ws11; +ws12:BLOCK(ram_ck12 = '1') BEGIN ram_s_r12 <= GUARDED ram_m_r12; END BLOCK ws12; +ws13:BLOCK(ram_ck13 = '1') BEGIN ram_s_r13 <= GUARDED ram_m_r13; END BLOCK ws13; +ws14:BLOCK(ram_ck14 = '1') BEGIN ram_s_r14 <= GUARDED ram_m_r14; END BLOCK ws14; +ws15:BLOCK(ram_ck15 = '1') BEGIN ram_s_r15 <= GUARDED ram_m_r15; END BLOCK ws15; + + + + + + -- Select register to write on tristate bus RA. +wa0 :BLOCK(ram_adra(0 )) BEGIN ram_ra <= GUARDED ram_s_r0 ; END BLOCK wa0 ; +wa1 :BLOCK(ram_adra(1 )) BEGIN ram_ra <= GUARDED ram_s_r1 ; END BLOCK wa1 ; +wa2 :BLOCK(ram_adra(2 )) BEGIN ram_ra <= GUARDED ram_s_r2 ; END BLOCK wa2 ; +wa3 :BLOCK(ram_adra(3 )) BEGIN ram_ra <= GUARDED ram_s_r3 ; END BLOCK wa3 ; +wa4 :BLOCK(ram_adra(4 )) BEGIN ram_ra <= GUARDED ram_s_r4 ; END BLOCK wa4 ; +wa5 :BLOCK(ram_adra(5 )) BEGIN ram_ra <= GUARDED ram_s_r5 ; END BLOCK wa5 ; +wa6 :BLOCK(ram_adra(6 )) BEGIN ram_ra <= GUARDED ram_s_r6 ; END BLOCK wa6 ; +wa7 :BLOCK(ram_adra(7 )) BEGIN ram_ra <= GUARDED ram_s_r7 ; END BLOCK wa7 ; +wa8 :BLOCK(ram_adra(8 )) BEGIN ram_ra <= GUARDED ram_s_r8 ; END BLOCK wa8 ; +wa9 :BLOCK(ram_adra(9 )) BEGIN ram_ra <= GUARDED ram_s_r9 ; END BLOCK wa9 ; +wa10:BLOCK(ram_adra(10)) BEGIN ram_ra <= GUARDED ram_s_r10; END BLOCK wa10; +wa11:BLOCK(ram_adra(11)) BEGIN ram_ra <= GUARDED ram_s_r11; END BLOCK wa11; +wa12:BLOCK(ram_adra(12)) BEGIN ram_ra <= GUARDED ram_s_r12; END BLOCK wa12; +wa13:BLOCK(ram_adra(13)) BEGIN ram_ra <= GUARDED ram_s_r13; END BLOCK wa13; +wa14:BLOCK(ram_adra(14)) BEGIN ram_ra <= GUARDED ram_s_r14; END BLOCK wa14; +wa15:BLOCK(ram_adra(15)) BEGIN ram_ra <= GUARDED ram_s_r15; END BLOCK wa15; + + -- Select register to write on tristate bus RB. +wb0 :BLOCK(ram_adrb(0 )) BEGIN ram_rb <= GUARDED ram_s_r0 ; END BLOCK wb0 ; +wb1 :BLOCK(ram_adrb(1 )) BEGIN ram_rb <= GUARDED ram_s_r1 ; END BLOCK wb1 ; +wb2 :BLOCK(ram_adrb(2 )) BEGIN ram_rb <= GUARDED ram_s_r2 ; END BLOCK wb2 ; +wb3 :BLOCK(ram_adrb(3 )) BEGIN ram_rb <= GUARDED ram_s_r3 ; END BLOCK wb3 ; +wb4 :BLOCK(ram_adrb(4 )) BEGIN ram_rb <= GUARDED ram_s_r4 ; END BLOCK wb4 ; +wb5 :BLOCK(ram_adrb(5 )) BEGIN ram_rb <= GUARDED ram_s_r5 ; END BLOCK wb5 ; +wb6 :BLOCK(ram_adrb(6 )) BEGIN ram_rb <= GUARDED ram_s_r6 ; END BLOCK wb6 ; +wb7 :BLOCK(ram_adrb(7 )) BEGIN ram_rb <= GUARDED ram_s_r7 ; END BLOCK wb7 ; +wb8 :BLOCK(ram_adrb(8 )) BEGIN ram_rb <= GUARDED ram_s_r8 ; END BLOCK wb8 ; +wb9 :BLOCK(ram_adrb(9 )) BEGIN ram_rb <= GUARDED ram_s_r9 ; END BLOCK wb9 ; +wb10:BLOCK(ram_adrb(10)) BEGIN ram_rb <= GUARDED ram_s_r10; END BLOCK wb10; +wb11:BLOCK(ram_adrb(11)) BEGIN ram_rb <= GUARDED ram_s_r11; END BLOCK wb11; +wb12:BLOCK(ram_adrb(12)) BEGIN ram_rb <= GUARDED ram_s_r12; END BLOCK wb12; +wb13:BLOCK(ram_adrb(13)) BEGIN ram_rb <= GUARDED ram_s_r13; END BLOCK wb13; +wb14:BLOCK(ram_adrb(14)) BEGIN ram_rb <= GUARDED ram_s_r14; END BLOCK wb14; +wb15:BLOCK(ram_adrb(15)) BEGIN ram_rb <= GUARDED ram_s_r15; END BLOCK wb15; + + + + -- ********************* Power supply check ********************** + + ASSERT(vss = '0') + REPORT "Power supply VSS badly connected." SEVERITY WARNING; + ASSERT(vdd = '1') + REPORT "Power supply VDD badly connected." SEVERITY WARNING; + + +END behavior_data_flow; diff --git a/alliance/src/documentation/alliance-examples/amd2901/pattern.c b/alliance/src/documentation/alliance-examples/amd2901/pattern.c new file mode 100644 index 00000000..410cc01a --- /dev/null +++ b/alliance/src/documentation/alliance-examples/amd2901/pattern.c @@ -0,0 +1,1109 @@ +/**********************************************************************************************/ +/******************************* Pierre Nguyen Tuong ******************************************/ +/******************************* 03/10/1999 ******************************************/ +/******************************* DEA ASIME - DESS ******************************************/ +/**********************************************************************************************/ +/******************************* Generation des vecteurs de tests de l'am2901 *****************/ +/**********************************************************************************************/ +/**********************************************************************************************/ + + +#include +#include +#include "mut.h" + + +#define RplusS 0 +#define SmoinsR 1 +#define RmoinsS 2 +#define RouS 3 +#define RetS 4 +#define nonRetS 5 +#define RouxS 6 +#define nonRouxS 7 + + + +/********************************* Variables globales *****************************************/ + +long vct = 0 ; /* Moment de l'evenement */ +long interval = 100L ; /* Interval */ + +int ck = 0 ; +int fonc = 0 ; +int test = 0 ; +int scin = 0 ; +int scout = 0 ; +int i = 0 ; +int a = 0 ; +int b = 0 ; +int d = 0 ; +int noe = 0 ; +int r0 = 0 ; +int r3 = 0 ; +int q0 = 0 ; +int q3 = 0 ; +int ovr = 0 ; +int zero = 0 ; +int signe = 0 ; +int np = 0 ; +int ng = 0 ; +int cin = 0 ; +int cout = 0 ; +int y = 0 ; + +int r = 0 ; /* Operande r */ +int s = 0 ; /* Operande s */ +int res = 0 ; /* Resultat de l'operation */ +int op ; /* Code operatoire */ +int sa ; /* Sortie a de la ram */ +int sb ; /* Sortie b de la ram */ +int sq ; /* Sortie q de l'accumulateur */ +int mcode ; /* Micro code */ + +short c[5] ; /* La retenue */ + +/********************************* Fonctions utiles *******************************************/ + +/*** Transforme un entier en chaine ***/ + +char *entierVersChaine(long entier) +{ + char *chaineEntier ; + chaineEntier = (char *) mbkalloc (32 * sizeof (char)); + sprintf (chaineEntier,"%i",entier); + + return(chaineEntier); +} + +/*** Transforme un octal en chaine ***/ + +char *octVersChaine(int entier) +{ + int temp ; + char *chaineEntier ; + char *chaineOctal ; + + chaineEntier = (char *)mbkalloc(32 * sizeof (char)); + chaineOctal = (char *)mbkalloc(32 * sizeof (char)); + + sprintf(chaineEntier,"%i",entier) ; /* Met le nombre octal dans la chaine */ + temp = (int)strtol(chaineEntier,(char **)NULL,8) ; /* Convertit le nombre octal en entier */ + sprintf(chaineOctal,"%i",temp) ; /* Met l'entier dans la chaine */ + free(chaineEntier) ; + + return(chaineOctal); +} + +/*** Fait avancer l'horloge de c coups ***/ + +void coupHorloge(long c) +{ + long i ; + + for(i = 1 ; i <= c ; i++) + { + AFFECT(entierVersChaine(vct),"ck","0") ; + vct = vct + interval ; + AFFECT(entierVersChaine(vct),"ck","1") ; + vct = vct + interval ; + } +} + + +/********************************* Fonctions de verifications *********************************/ + + +/*** zero ***/ + +int calculZero(void) +{ + if(res == 0) + zero = 1 ; + else + zero = 0 ; +} + +/*** Retenue de sortie ***/ + +void calculCout(void) +{ + int opx ; + int opy ; + int x ; + int y ; + int i ; + int z ; + +/* Initialisation */ + switch(op) + { + case RplusS : opx = r ; + opy = s ; + break ; + case SmoinsR : opx = s ; + opy = ~(r) ; + break ; + case RmoinsS : opx = r ; + opy = ~(s) ; + break ; + case RouS : + case RetS : opx = r ; + opy = s ; + break ; + case nonRetS : + case RouxS : + case nonRouxS: + + default : break ; + } + + c[0] = cin ; + + /* Le calcul de la retenue */ + + for (i = 1;i <= 4;i++) + { + x = (opx & 0x0001); + y = (opy & 0x0001); + if (((x == 1) && (y == 1)) + ||((x == 1) && (c[i-1] == 1)) + ||((y == 1) && (c[i-1] == 1))) + c[i] = 1 ; + else + c[i]=0; + opx = opx >> 1 ; + opy = opy >> 1 ; + } + + if (c[4]==0) + cout = 0 ; + else + cout = 1 ; +} + +/*** Signe ***/ + +void calculSigne(void) +{ + if((res & 0x8) == 0) + signe = 0 ; + else + signe = 1 ; +} + +/*** Depassement de capacite ***/ + +void calculOvr(void) +{ + if (c[4] ^ c[3]) + ovr = 1 ; + else + ovr = 0 ; +} + +/*** Resultat d'une operation ***/ + +void calculResultat(void) +{ + switch(op) + { + case RplusS : res = (r + s) % 16 ; + break ; + case SmoinsR : res = ((s - r) & 0xf) % 16 ; + break ; + case RmoinsS : res = ((r - s) & 0xf) % 16 ; + break ; + case RouS : res = r | s ; + break ; + case RetS : res = r & s ; + break ; + case nonRetS : res = (~(r) & s) & 0xf ; + break ; + case RouxS : res = r ^ s ; + break ; + case nonRouxS : res = (~(r ^ s)) & 0xf ; + break ; + default : break ; + } +} + +/*** Sorties ***/ + +void calculSortie(void) +{ + char *chaineEntier ; + int temp ; + + chaineEntier = (char *) mbkalloc (32 * sizeof (char)); + + sprintf(chaineEntier,"%i",mcode) ; + temp = (int)strtol(chaineEntier,(char **)NULL,8) ; + free(chaineEntier) ; + + temp = (temp & 0x1c0) >> 6 ; + + switch(temp) + { + case 2 : y = sa ; + break ; + default : y = res ; + break ; + } +} + +/*** Code operatoire ***/ + +void calculCodeOp(void) +{ + char *chaineEntier ; + int temp ; + + chaineEntier = (char *) mbkalloc (32 * sizeof (char)); + + sprintf(chaineEntier,"%i",mcode) ; + temp = (int)strtol(chaineEntier,(char **)NULL,8) ; + free(chaineEntier) ; + + temp = (temp & 0x38) >> 3 ; + + switch(temp) + { + case 0 : op = RplusS ; + break ; + case 1 : op = SmoinsR ; + break ; + case 2 : op = RmoinsS ; + break ; + case 3 : op = RouS ; + break ; + case 4 : op = RetS ; + break ; + case 5 : op = nonRetS ; + break ; + case 6 : op = RouxS ; + break ; + default : op = nonRouxS ; + break ; + } +} + +void operation(long vect) +{ + calculResultat() ; + calculSigne() ; + + calculCout() ; + calculOvr() ; + calculZero() ; + + if((op == RplusS) || (op == SmoinsR) || (op == RmoinsS)) + { + AFFECT(entierVersChaine(vect),"ovr",entierVersChaine(ovr)) ; + AFFECT(entierVersChaine(vect),"zero",entierVersChaine(zero)) ; + AFFECT(entierVersChaine(vect),"signe",entierVersChaine(signe)) ; + AFFECT(entierVersChaine(vect),"cout",entierVersChaine(cout)) ; + } + else + { + AFFECT(entierVersChaine(vect),"ovr",entierVersChaine(0)) ; + AFFECT(entierVersChaine(vect),"zero",entierVersChaine(zero)) ; + AFFECT(entierVersChaine(vect),"signe",entierVersChaine(signe)) ; + AFFECT(entierVersChaine(vect),"cout",entierVersChaine(0)) ; + } +} + +void sortie(long vect) +{ + calculSortie() ; + + AFFECT(entierVersChaine(vect),"y",entierVersChaine(y)) ; +} + +void codeOp(long vect) +{ + calculCodeOp() ; + + AFFECT(entierVersChaine(vect),"i",octVersChaine(mcode)) ; +} + +void entree(long vect) +{ + AFFECT(entierVersChaine(vect),"scin",entierVersChaine(scin)) ; + AFFECT(entierVersChaine(vect),"a",entierVersChaine(a)) ; + AFFECT(entierVersChaine(vect),"b",entierVersChaine(b)) ; + AFFECT(entierVersChaine(vect),"d",entierVersChaine(d)) ; + AFFECT(entierVersChaine(vect),"noe",entierVersChaine(noe)) ; + /* AFFECT(entierVersChaine(vect),"r0",entierVersChaine(r0)) ; */ + AFFECT(entierVersChaine(vect),"r3",entierVersChaine(r3)) ; + /* AFFECT(entierVersChaine(vect),"q0",entierVersChaine(q0)) ; */ + AFFECT(entierVersChaine(vect),"q3",entierVersChaine(q3)) ; + AFFECT(entierVersChaine(vect),"cin",entierVersChaine(cin)) ; + +} + + +/**********************************************************************************************/ +/********************************* Fonction principale ****************************************/ +/**********************************************************************************************/ + +int main() +{ + int i ; + int x ; + int z ; + + DEF_GENPAT ("pattern"); + + DECLAR ("a",":1","X",IN,"3 DOWNTO 0",""); + DECLAR ("b",":1","X",IN,"3 DOWNTO 0",""); + DECLAR ("d",":1","X",IN,"3 DOWNTO 0",""); + DECLAR ("i",":1","O",IN,"8 DOWNTO 0",""); + DECLAR ("fonc",":1","B",IN,"",""); + DECLAR ("test",":1","B",IN,"",""); + DECLAR ("scin",":1","B",IN,"",""); + DECLAR ("noe",":1","B",IN,"",""); + DECLAR ("ck",":1","B",IN,"",""); + DECLAR ("cin",":1","B",IN,"",""); + DECLAR ("r0",":1","B",INOUT,"",""); + DECLAR ("r3",":1","B",INOUT,"",""); + DECLAR ("q0",":1","B",INOUT,"",""); + DECLAR ("q3",":1","B",INOUT,"",""); + DECLAR ("y",":1","X",OUT,"3 DOWNTO 0",""); + DECLAR ("zero",":1","B",OUT,"",""); + DECLAR ("signe",":1","B",OUT,"",""); + DECLAR ("scout",":1","B",OUT,"",""); + DECLAR ("ovr",":1","B",OUT,"",""); + DECLAR ("np",":1","B",OUT,"",""); + DECLAR ("ng",":1","B",OUT,"",""); + DECLAR ("cout",":1","B",OUT,"",""); + DECLAR ("vdd",":1","B",IN,"",""); + DECLAR ("vss",":1","B",IN,"",""); + DECLAR ("vdde",":1","B",IN,"",""); + DECLAR ("vsse",":1","B",IN,"",""); + + + vct = 0 ; + + + + /****************** Initialiation ******************/ + AFFECT (entierVersChaine(vct),"a","0b0000"); + AFFECT (entierVersChaine(vct),"b","0b0000"); + AFFECT (entierVersChaine(vct),"fonc","0b1"); + AFFECT (entierVersChaine(vct),"test","0b0"); + AFFECT (entierVersChaine(vct),"scin","0b0"); + AFFECT (entierVersChaine(vct),"noe","0b0"); + AFFECT (entierVersChaine(vct),"cin","0b0"); + AFFECT (entierVersChaine(vct),"vdd","1") ; + AFFECT (entierVersChaine(vct),"vss","0") ; + AFFECT (entierVersChaine(vct),"vdde","1") ; + AFFECT (entierVersChaine(vct),"vsse","0") ; + AFFECT (entierVersChaine(vct),"i","0b0000") ; + AFFECT (entierVersChaine(vct),"d","0b0000") ; + AFFECT (entierVersChaine(vct),"ck","1") ; + AFFECT (entierVersChaine(vct),"scout","?0b*") ; + /***************************************************/ + + + + + /*****************************************/ + /***** Ecriture dans le registre Q *******/ + /*****************************************/ + + /* Ecriture de 1010 */ + + /* 1 **************/ + AFFECT (entierVersChaine(vct),"i",octVersChaine(007)); + AFFECT (entierVersChaine(vct),"d","0b1010"); + + AFFECT (entierVersChaine(vct),"y","0b1010"); + AFFECT (entierVersChaine(vct),"signe","0b1"); + + coupHorloge(1) ; + + /* Ecriture de 0101 */ + + /* 2 **************/ + + AFFECT (entierVersChaine(vct),"i","0o007"); + AFFECT (entierVersChaine(vct),"d","0b0101"); + AFFECT (entierVersChaine(vct),"y","0b0101"); + AFFECT (entierVersChaine(vct),"signe","0b0"); + + coupHorloge(1) ; + + AFFECT (entierVersChaine(vct),"y","0b0101"); + AFFECT (entierVersChaine(vct),"signe","0b0"); + + /* Lecture de l'accu */ + + /* 3 **************/ + + AFFECT (entierVersChaine(vct),"i","0o032"); + AFFECT (entierVersChaine(vct),"d","0b1010"); + AFFECT (entierVersChaine(vct),"y","0b0101"); + + coupHorloge(1) ; + + AFFECT (entierVersChaine(vct),"y","0b0101"); + AFFECT (entierVersChaine(vct),"signe","0b0"); + + + + /*****************************************************************/ + /***** Decalage droite du registre Q et ecriture dans la ram *****/ + /*****************************************************************/ + + /* 4 **************/ + + AFFECT (entierVersChaine(vct),"i","0o462"); + AFFECT (entierVersChaine(vct),"b","0b0000"); + AFFECT (entierVersChaine(vct),"r3","0b1"); + AFFECT (entierVersChaine(vct),"q3","0b1"); + + coupHorloge(1) ; + + AFFECT (entierVersChaine(vct-interval),"y","0b1010"); + AFFECT (entierVersChaine(vct-interval),"signe","0b1"); + + /* 5 **************/ + + AFFECT (entierVersChaine(vct),"i","0o462"); + AFFECT (entierVersChaine(vct),"b","0b0001"); + AFFECT (entierVersChaine(vct),"r3","0b0"); + AFFECT (entierVersChaine(vct),"q3","0b0"); + + coupHorloge(1) ; + + AFFECT (entierVersChaine(vct-interval),"y","0b0101"); + AFFECT (entierVersChaine(vct-interval),"signe","0b0"); + + + /* 6 **************/ + + AFFECT (entierVersChaine(vct),"i","0o462"); + AFFECT (entierVersChaine(vct),"b","0b0010"); + AFFECT (entierVersChaine(vct),"r3","0b1"); + AFFECT (entierVersChaine(vct),"q3","0b1"); + + coupHorloge(1) ; + + AFFECT (entierVersChaine(vct-interval),"y","0b1010"); + AFFECT (entierVersChaine(vct-interval),"signe","0b1"); + + + /* 7 **************/ + + AFFECT (entierVersChaine(vct),"i","0o462"); + AFFECT (entierVersChaine(vct),"b","0b0011"); + AFFECT (entierVersChaine(vct),"r3","0b0"); + AFFECT (entierVersChaine(vct),"q3","0b0"); + + coupHorloge(1) ; + + AFFECT (entierVersChaine(vct-interval),"y","0b0101"); + AFFECT (entierVersChaine(vct-interval),"signe","0b0"); + + + /* 8 **************/ + + AFFECT (entierVersChaine(vct),"i","0o462"); + AFFECT (entierVersChaine(vct),"b","0b0100"); + AFFECT (entierVersChaine(vct),"r3","0b1"); + AFFECT (entierVersChaine(vct),"q3","0b1"); + + coupHorloge(1) ; + + AFFECT (entierVersChaine(vct-interval),"y","0b1010"); + AFFECT (entierVersChaine(vct-interval),"signe","0b1"); + + + /* 9 **************/ + + AFFECT (entierVersChaine(vct),"i","0o462"); + AFFECT (entierVersChaine(vct),"b","0b0101"); + AFFECT (entierVersChaine(vct),"r3","0b0"); + AFFECT (entierVersChaine(vct),"q3","0b0"); + + coupHorloge(1) ; + + AFFECT (entierVersChaine(vct-interval),"y","0b0101"); + AFFECT (entierVersChaine(vct-interval),"signe","0b0"); + + + /* 10 **************/ + + AFFECT (entierVersChaine(vct),"i","0o462"); + AFFECT (entierVersChaine(vct),"b","0b0110"); + AFFECT (entierVersChaine(vct),"r3","0b1"); + AFFECT (entierVersChaine(vct),"q3","0b1"); + + coupHorloge(1) ; + + AFFECT (entierVersChaine(vct-interval),"y","0b1010"); + AFFECT (entierVersChaine(vct-interval),"signe","0b1"); + + + /* 11 **************/ + + AFFECT (entierVersChaine(vct),"i","0o462"); + AFFECT (entierVersChaine(vct),"b","0b0111"); + AFFECT (entierVersChaine(vct),"r3","0b0"); + AFFECT (entierVersChaine(vct),"q3","0b0"); + + coupHorloge(1) ; + + AFFECT (entierVersChaine(vct-interval),"y","0b0101"); + AFFECT (entierVersChaine(vct-interval),"signe","0b0"); + + /* 12 **************/ + + AFFECT (entierVersChaine(vct),"i","0o462"); + AFFECT (entierVersChaine(vct),"b","0b1000"); + AFFECT (entierVersChaine(vct),"r3","0b1"); + AFFECT (entierVersChaine(vct),"q3","0b1"); + + coupHorloge(1) ; + + AFFECT (entierVersChaine(vct-interval),"y","0b1010"); + AFFECT (entierVersChaine(vct-interval),"signe","0b1"); + + /*****************************************************/ + /***** Lecture de ce qui a ete ecrit dans la RAM *****/ + /*****************************************************/ + + /* 12 **************/ + + AFFECT (entierVersChaine(vct),"i","0o163"); + + for(i = 0 ; i < 7 ; i = i+2) + { + AFFECT (entierVersChaine(vct),"b",entierVersChaine(i)); + AFFECT (entierVersChaine(vct),"y","0b1010"); + AFFECT (entierVersChaine(vct),"signe","0b1"); + + coupHorloge(1) ; + + AFFECT (entierVersChaine(vct),"b",entierVersChaine(i+1)); + AFFECT (entierVersChaine(vct),"y","0b0101"); + AFFECT (entierVersChaine(vct),"signe","0b0"); + + coupHorloge(1) ; + } + + + + + + /*****************************************************************/ + /***** Decalage gauche du registre Q et ecriture dans la ram *****/ + /*****************************************************************/ + + + /* Ecriture de 0101 */ + + /* **************/ + + + AFFECT (entierVersChaine(vct),"r3","?0b*"); + AFFECT (entierVersChaine(vct),"q3","?0b*"); + AFFECT (entierVersChaine(vct),"r0","?0b*"); + AFFECT (entierVersChaine(vct),"q0","?0b*"); + + + /* Ecriture de 1010 */ + + /* 1 **************/ + AFFECT (entierVersChaine(vct),"i",octVersChaine(007)); + AFFECT (entierVersChaine(vct),"d","0b1010"); + + AFFECT (entierVersChaine(vct),"y","0b1010"); + AFFECT (entierVersChaine(vct),"signe","0b1"); + + coupHorloge(1) ; + + /* Ecriture de 0101 */ + + /* 2 **************/ + + AFFECT (entierVersChaine(vct),"i","0o007"); + AFFECT (entierVersChaine(vct),"d","0b0101"); + AFFECT (entierVersChaine(vct),"y","0b0101"); + AFFECT (entierVersChaine(vct),"signe","0b0"); + + coupHorloge(1) ; + + AFFECT (entierVersChaine(vct),"y","0b0101"); + AFFECT (entierVersChaine(vct),"signe","0b0"); + + /* Lecture de l'accu */ + + /* 3 **************/ + + AFFECT (entierVersChaine(vct),"i","0o032"); + AFFECT (entierVersChaine(vct),"d","0b1010"); + AFFECT (entierVersChaine(vct),"y","0b0101"); + + coupHorloge(1) ; + + AFFECT (entierVersChaine(vct),"y","0b0101"); + AFFECT (entierVersChaine(vct),"signe","0b0"); + + + + /* **************/ + /* **************/ + + + AFFECT (entierVersChaine(vct),"i","0o662"); + AFFECT (entierVersChaine(vct),"b","0b0000"); + AFFECT (entierVersChaine(vct),"r0","0b0"); + AFFECT (entierVersChaine(vct),"q0","0b0"); + + coupHorloge(1) ; + + AFFECT (entierVersChaine(vct-interval),"y","0b1010"); + AFFECT (entierVersChaine(vct-interval),"signe","0b1"); + + /* **************/ + + AFFECT (entierVersChaine(vct),"i","0o662"); + AFFECT (entierVersChaine(vct),"b","0b0001"); + AFFECT (entierVersChaine(vct),"r0","0b1"); + AFFECT (entierVersChaine(vct),"q0","0b1"); + + coupHorloge(1) ; + + AFFECT (entierVersChaine(vct-interval),"y","0b0101"); + AFFECT (entierVersChaine(vct-interval),"signe","0b0"); + + + /* **************/ + + + AFFECT (entierVersChaine(vct),"i","0o662"); + AFFECT (entierVersChaine(vct),"b","0b0010"); + AFFECT (entierVersChaine(vct),"r0","0b0"); + AFFECT (entierVersChaine(vct),"q0","0b0"); + + coupHorloge(1) ; + + AFFECT (entierVersChaine(vct-interval),"y","0b1010"); + AFFECT (entierVersChaine(vct-interval),"signe","0b1"); + + + /* **************/ + + AFFECT (entierVersChaine(vct),"i","0o662"); + AFFECT (entierVersChaine(vct),"b","0b0011"); + AFFECT (entierVersChaine(vct),"r0","0b1"); + AFFECT (entierVersChaine(vct),"q0","0b1"); + + coupHorloge(1) ; + + AFFECT (entierVersChaine(vct-interval),"y","0b0101"); + AFFECT (entierVersChaine(vct-interval),"signe","0b0"); + + + /* **************/ + + AFFECT (entierVersChaine(vct),"i","0o662"); + AFFECT (entierVersChaine(vct),"b","0b0100"); + AFFECT (entierVersChaine(vct),"r0","0b0"); + AFFECT (entierVersChaine(vct),"q0","0b0"); + + coupHorloge(1) ; + + AFFECT (entierVersChaine(vct-interval),"y","0b1010"); + AFFECT (entierVersChaine(vct-interval),"signe","0b1"); + + + /* **************/ + + AFFECT (entierVersChaine(vct),"i","0o662"); + AFFECT (entierVersChaine(vct),"b","0b0101"); + AFFECT (entierVersChaine(vct),"r0","0b1"); + AFFECT (entierVersChaine(vct),"q0","0b1"); + + coupHorloge(1) ; + + AFFECT (entierVersChaine(vct-interval),"y","0b0101"); + AFFECT (entierVersChaine(vct-interval),"signe","0b0"); + + + /* **************/ + + AFFECT (entierVersChaine(vct),"i","0o662"); + AFFECT (entierVersChaine(vct),"b","0b0110"); + AFFECT (entierVersChaine(vct),"r0","0b0"); + AFFECT (entierVersChaine(vct),"q0","0b0"); + + coupHorloge(1) ; + + AFFECT (entierVersChaine(vct-interval),"y","0b1010"); + AFFECT (entierVersChaine(vct-interval),"signe","0b1"); + + + /* **************/ + + AFFECT (entierVersChaine(vct),"i","0o662"); + AFFECT (entierVersChaine(vct),"b","0b0111"); + AFFECT (entierVersChaine(vct),"r0","0b1"); + AFFECT (entierVersChaine(vct),"q0","0b1"); + + coupHorloge(1) ; + + AFFECT (entierVersChaine(vct-interval),"y","0b0101"); + AFFECT (entierVersChaine(vct-interval),"signe","0b0"); + + /* **************/ + + AFFECT (entierVersChaine(vct),"i","0o662"); + AFFECT (entierVersChaine(vct),"b","0b1000"); + AFFECT (entierVersChaine(vct),"r0","0b0"); + AFFECT (entierVersChaine(vct),"q0","0b0"); + + coupHorloge(1) ; + + AFFECT (entierVersChaine(vct-interval),"y","0b1010"); + AFFECT (entierVersChaine(vct-interval),"signe","0b1"); + + /*****************************************************/ + /***** Lecture de ce qui a ete ecrit dans la RAM *****/ + /*****************************************************/ + + /* 12 **************/ + + AFFECT (entierVersChaine(vct),"i","0o163"); + + for(i = 0 ; i < 7 ; i = i+2) + { + AFFECT (entierVersChaine(vct),"b",entierVersChaine(i)); + AFFECT (entierVersChaine(vct),"y","0b1010"); + AFFECT (entierVersChaine(vct),"signe","0b1"); + + coupHorloge(1) ; + + AFFECT (entierVersChaine(vct),"b",entierVersChaine(i+1)); + AFFECT (entierVersChaine(vct),"y","0b0101"); + AFFECT (entierVersChaine(vct),"signe","0b0"); + + coupHorloge(1) ; + } + + + /*****************************************************************/ + /***** Lectures et ecritures de la ram ***************************/ + /*****************************************************************/ + + AFFECT (entierVersChaine(vct),"signe","?0b*"); + + for(i = 0 ; i < 16 ; i++) + { + /* Ecriture aux adresses a et b */ + AFFECT (entierVersChaine(vct),"i","0o337"); + AFFECT (entierVersChaine(vct),"d",entierVersChaine(i)); + AFFECT (entierVersChaine(vct),"a",entierVersChaine(i)); + AFFECT (entierVersChaine(vct),"b",entierVersChaine(i)); + AFFECT (entierVersChaine(vct),"y",entierVersChaine(i)); + coupHorloge(1) ; + } + + coupHorloge(1) ; + + AFFECT (entierVersChaine(vct),"i","0o137"); + AFFECT (entierVersChaine(vct),"d","0b0000"); + AFFECT (entierVersChaine(vct),"a","0b0000"); + AFFECT (entierVersChaine(vct),"b","0b0000"); + + AFFECT (entierVersChaine(vct),"y","?0b****"); + coupHorloge(1) ; + + /* Lecture a l'adresse a */ + for(i = 0 ; i < 16 ; i++) + { + AFFECT (entierVersChaine(vct),"i","0o134"); + AFFECT (entierVersChaine(vct),"a",entierVersChaine(i)); + AFFECT (entierVersChaine(vct),"y",entierVersChaine(i)); + coupHorloge(1) ; + } + + AFFECT (entierVersChaine(vct-interval),"y","?0b****"); + coupHorloge(1) ; + + AFFECT (entierVersChaine(vct),"i","0o137"); + AFFECT (entierVersChaine(vct),"d","0b0000"); + AFFECT (entierVersChaine(vct),"a","0b0000"); + AFFECT (entierVersChaine(vct),"b","0b0000"); + AFFECT (entierVersChaine(vct),"y","?0b****"); + coupHorloge(1) ; + + + + /* Lecture a l'adresse b */ + + for(i = 0 ; i < 16 ; i++) + { + AFFECT (entierVersChaine(vct),"i","0o133"); + AFFECT (entierVersChaine(vct),"b",entierVersChaine(i)); + + coupHorloge(1) ; + + + AFFECT (entierVersChaine(vct-interval),"y",entierVersChaine(i)); + + coupHorloge(1) ; + + AFFECT (entierVersChaine(vct-interval),"y","?0b****"); + } + + /*****************************************************************/ + /***** Operations arithmetiques et booleennes ********************/ + /*****************************************************************/ + + + scin = 0 ; + scout = 0 ; + a = 0 ; + b = 0 ; + d = 0 ; + noe = 0 ; + r0 = 0 ; + r3 = 0 ; + q0 = 0 ; + q3 = 0 ; + ovr = 0 ; + zero = 0 ; + signe = 0 ; + cin = 0 ; + y = 0 ; + + r = 0 ; + s = 0 ; + sa = 0 ; + sb = 0 ; + sq = 0 ; + mcode = 107 ; + + codeOp(vct) ; + for(i = 0 ; i < 16 ; i++) /* D,0 D+0 */ + { + r = d ; + s = 0 ; + entree(vct) ; + operation(vct) ; + sortie(vct) ; + d++ ; + + coupHorloge(1) ; + } + + + d = 0 ; + r = 0 ; + s = 0 ; + cin = 1 ; + mcode = 117 ; + + codeOp(vct) ; + for(i = 0 ; i < 16 ; i++) /* D,0 0-D */ + { + r = d ; + s = 0 ; + entree(vct) ; + operation(vct) ; + sortie(vct) ; + d++ ; + + coupHorloge(1) ; + } + + d = 0 ; + r = 0 ; + s = 0 ; + cin = 1 ; + mcode = 127 ; + + codeOp(vct) ; + for(i = 0 ; i < 16 ; i++) /* D,0 D-0 */ + { + r = d ; + s = 0 ; + entree(vct) ; + operation(vct) ; + sortie(vct) ; + d++ ; + + coupHorloge(1) ; + } + + d = 0 ; + r = 0 ; + s = 0 ; + cin = 1 ; + mcode = 127 ; + + codeOp(vct) ; + for(i = 0 ; i < 16 ; i++) /* D,0 D-0 */ + { + r = d ; + s = 0 ; + entree(vct) ; + operation(vct) ; + sortie(vct) ; + d++ ; + + coupHorloge(1) ; + } + + d = 0 ; + r = 0 ; + s = 0 ; + cin = 0 ; + mcode = 167 ; + + codeOp(vct) ; + for(i = 0 ; i < 16 ; i++) /* D,0 D ou exclusif 0 */ + { + r = d ; + s = 0 ; + entree(vct) ; + operation(vct) ; + sortie(vct) ; + d++ ; + + coupHorloge(1) ; + } + + d = 0 ; + r = 0 ; + s = 0 ; + cin = 0 ; + mcode = 167 ; + + codeOp(vct) ; + for(i = 0 ; i < 16 ; i++) /* D,0 D ou exclusif 0 */ + { + r = d ; + s = 0 ; + entree(vct) ; + operation(vct) ; + sortie(vct) ; + d++ ; + + coupHorloge(1) ; + } + + d = 0 ; + r = 0 ; + s = 0 ; + cin = 0 ; + mcode = 177 ; + + codeOp(vct) ; + + for(i = 0 ; i < 16 ; i++) /* D,0 non D ou exclusif 0 */ + { + r = d ; + s = 0 ; + entree(vct) ; + operation(vct) ; + sortie(vct) ; + d++ ; + + coupHorloge(1) ; + } + + /* Chargement de 5 dans l'accu */ + d = 5 ; + r = 5 ; + s = 0 ; + sa = 5 ; + cin = 0 ; + mcode = 7 ; + + codeOp(vct) ; + for(i = 0 ; i < 3 ; i++) /* D,0 D + 0 */ + { + r = d ; + s = 0 ; + entree(vct) ; + operation(vct) ; + sortie(vct) ; + + coupHorloge(1) ; + } + + d = 0 ; + r = 0 ; + s = 0 ; + sa = 5 ; + cin = 0 ; + mcode = 106 ; + + codeOp(vct) ; + for(i = 0 ; i < 16 ; i++) /* D,0 D + Q avec ovf et tout le tintoin */ + { + r = d ; + s = sa ; + entree(vct) ; + operation(vct) ; + sortie(vct) ; + d++ ; + + coupHorloge(1) ; + } + d = 4 ; + r = 0 ; + s = 0 ; + sa = 5 ; + cin = 1 ; + mcode = 116 ; + + codeOp(vct) ; + for(i = 0 ; i < 16 ; i++) /* D,0 Q - D avec ovf et tout le tintoin */ + { + r = d ; + s = 5 ; + entree(vct) ; + operation(vct) ; + sortie(vct) ; + if (d < 15) + d++ ; + else + d = 0; + + coupHorloge(1) ; + } + + d = 8 ; + r = 0 ; + s = 0 ; + sa = 5 ; + cin = 1 ; + mcode = 126 ; + + codeOp(vct) ; + for(i = 0 ; i < 16 ; i++) /* D,0 D - Q avec ovf et tout le tintoin */ + { + r = d ; + s = 5 ; + entree(vct) ; + operation(vct) ; + sortie(vct) ; + if (d < 15) + d++ ; + else + d = 0; + + coupHorloge(1) ; + } + + SAV_GENPAT (); + exit(0); +} + + + diff --git a/alliance/src/documentation/alliance-examples/amd2901/pattern.pat b/alliance/src/documentation/alliance-examples/amd2901/pattern.pat new file mode 100644 index 00000000..1b93841d --- /dev/null +++ b/alliance/src/documentation/alliance-examples/amd2901/pattern.pat @@ -0,0 +1,593 @@ + +-- description generated by Pat driver + +-- date : Tue Mar 4 09:45:36 2003 +-- revision : v109 + +-- sequence : pattern + +-- input / output list : +in a (3 downto 0) X;; +in b (3 downto 0) X;; +in d (3 downto 0) X;; +in i (8 downto 0) O;; +in fonc B;; +in test B;; +in scin B;; +in noe B;; +in ck B;; +in cin B;; +inout r0 B;; +inout r3 B;; +inout q0 B;; +inout q3 B;; +out y (3 downto 0) X;; +out zero B;; +out signe B;; +out scout B;; +out ovr B;; +out np B;; +out ng B;; +out cout B;; +in vdd B;; +in vss B;; +in vdde B;; +in vsse B;; + +begin + +-- Pattern description : + +-- a b d i f t s n c c r r q q y z s s o n n c v v v v +-- o e c o k i 0 3 0 3 e i c v p g o d s d s +-- n s i e n r g o r u d s d s +-- c t n o n u t e e +-- e t + + +-- Beware : unprocessed patterns + +< 0 ps> : 0 0 a 007 1 0 0 0 0 0 ?* ?* ?* ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 100 ps> : 0 0 a 007 1 0 0 0 1 0 ?* ?* ?* ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 200 ps> : 0 0 5 007 1 0 0 0 0 0 ?* ?* ?* ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 300 ps> : 0 0 5 007 1 0 0 0 1 0 ?* ?* ?* ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 400 ps> : 0 0 a 032 1 0 0 0 0 0 ?* ?* ?* ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 500 ps> : 0 0 a 032 1 0 0 0 1 0 ?* ?* ?* ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 600 ps> : 0 0 a 462 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 700 ps> : 0 0 a 462 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 800 ps> : 0 1 a 462 1 0 0 0 0 0 ?* 0 ?* 0 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 900 ps> : 0 1 a 462 1 0 0 0 1 0 ?* 0 ?* 0 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 1000 ps> : 0 2 a 462 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 1100 ps> : 0 2 a 462 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 1200 ps> : 0 3 a 462 1 0 0 0 0 0 ?* 0 ?* 0 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 1300 ps> : 0 3 a 462 1 0 0 0 1 0 ?* 0 ?* 0 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 1400 ps> : 0 4 a 462 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 1500 ps> : 0 4 a 462 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 1600 ps> : 0 5 a 462 1 0 0 0 0 0 ?* 0 ?* 0 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 1700 ps> : 0 5 a 462 1 0 0 0 1 0 ?* 0 ?* 0 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 1800 ps> : 0 6 a 462 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 1900 ps> : 0 6 a 462 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 2000 ps> : 0 7 a 462 1 0 0 0 0 0 ?* 0 ?* 0 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 2100 ps> : 0 7 a 462 1 0 0 0 1 0 ?* 0 ?* 0 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 2200 ps> : 0 8 a 462 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 2300 ps> : 0 8 a 462 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 2400 ps> : 0 0 a 163 1 0 0 0 0 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 2500 ps> : 0 0 a 163 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 2600 ps> : 0 1 a 163 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 2700 ps> : 0 1 a 163 1 0 0 0 1 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 2800 ps> : 0 2 a 163 1 0 0 0 0 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 2900 ps> : 0 2 a 163 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 3000 ps> : 0 3 a 163 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 3100 ps> : 0 3 a 163 1 0 0 0 1 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 3200 ps> : 0 4 a 163 1 0 0 0 0 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 3300 ps> : 0 4 a 163 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 3400 ps> : 0 5 a 163 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 3500 ps> : 0 5 a 163 1 0 0 0 1 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 3600 ps> : 0 6 a 163 1 0 0 0 0 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 3700 ps> : 0 6 a 163 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 3800 ps> : 0 7 a 163 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 3900 ps> : 0 7 a 163 1 0 0 0 1 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 4000 ps> : 0 7 a 007 1 0 0 0 0 0 ?* ?* ?* ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 4100 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?* 1 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 5400 ps> : 0 4 a 662 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 5500 ps> : 0 4 a 662 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 5600 ps> : 0 5 a 662 1 0 0 0 0 0 1 ?* 1 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 5700 ps> : 0 5 a 662 1 0 0 0 1 0 1 ?* 1 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 5800 ps> : 0 6 a 662 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 5900 ps> : 0 6 a 662 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 6000 ps> : 0 7 a 662 1 0 0 0 0 0 1 ?* 1 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 6100 ps> : 0 7 a 662 1 0 0 0 1 0 1 ?* 1 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 6200 ps> : 0 8 a 662 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 6300 ps> : 0 8 a 662 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 6400 ps> : 0 0 a 163 1 0 0 0 0 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 6500 ps> : 0 0 a 163 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 6600 ps> : 0 1 a 163 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 6700 ps> : 0 1 a 163 1 0 0 0 1 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 6800 ps> : 0 2 a 163 1 0 0 0 0 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 6900 ps> : 0 2 a 163 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 7000 ps> : 0 3 a 163 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 7100 ps> : 0 3 a 163 1 0 0 0 1 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 7200 ps> : 0 4 a 163 1 0 0 0 0 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 7300 ps> : 0 4 a 163 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 7400 ps> : 0 5 a 163 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 7500 ps> : 0 5 a 163 1 0 0 0 1 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 7600 ps> : 0 6 a 163 1 0 0 0 0 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 7700 ps> : 0 6 a 163 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 7800 ps> : 0 7 a 163 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 7900 ps> : 0 7 a 163 1 0 0 0 1 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ; +< 8000 ps> : 0 0 0 337 1 0 0 0 0 0 0 ?* 0 ?* ?0 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ; +< 8100 ps> : 0 0 0 337 1 0 0 0 1 0 0 ?* 0 ?* ?0 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ; +< 8200 ps> : 1 1 1 337 1 0 0 0 0 0 0 ?* 0 ?* ?1 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ; +< 8300 ps> : 1 1 1 337 1 0 0 0 1 0 0 ?* 0 ?* ?1 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ; +< 8400 ps> : 2 2 2 337 1 0 0 0 0 0 0 ?* 0 ?* ?2 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ; +< 8500 ps> : 2 2 2 337 1 0 0 0 1 0 0 ?* 0 ?* ?2 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ; +< 8600 ps> : 3 3 3 337 1 0 0 0 0 0 0 ?* 0 ?* ?3 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ; +< 8700 ps> : 3 3 3 337 1 0 0 0 1 0 0 ?* 0 ?* ?3 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ; +< 8800 ps> : 4 4 4 337 1 0 0 0 0 0 0 ?* 0 ?* ?4 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ; +< 8900 ps> : 4 4 4 337 1 0 0 0 1 0 0 ?* 0 ?* ?4 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ; +< 9000 ps> : 5 5 5 337 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 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0 0 ?* 0 ?* ?b ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ; +< 10400 ps> : c c c 337 1 0 0 0 0 0 0 ?* 0 ?* ?c ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ; +< 10500 ps> : c c c 337 1 0 0 0 1 0 0 ?* 0 ?* ?c ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ; +< 10600 ps> : d d d 337 1 0 0 0 0 0 0 ?* 0 ?* ?d ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ; +< 10700 ps> : d d d 337 1 0 0 0 1 0 0 ?* 0 ?* ?d ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ; +< 10800 ps> : e e e 337 1 0 0 0 0 0 0 ?* 0 ?* ?e ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ; +< 10900 ps> : e e e 337 1 0 0 0 1 0 0 ?* 0 ?* ?e ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ; +< 11000 ps> : f f f 337 1 0 0 0 0 0 0 ?* 0 ?* ?f ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ; +< 11100 ps> : f f f 337 1 0 0 0 1 0 0 ?* 0 ?* ?f ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ; +< 11200 ps> : f f f 337 1 0 0 0 0 0 0 ?* 0 ?* ?f ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ; +< 11300 ps> : f f f 337 1 0 0 0 1 0 0 ?* 0 ?* ?f ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ; +< 11400 ps> : 0 0 0 137 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ; +< 11500 ps> : 0 0 0 137 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* 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1 0 1 0 ; +< 46800 ps> : 0 0 b 106 1 0 0 0 0 0 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 46900 ps> : 0 0 b 106 1 0 0 0 1 0 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 47000 ps> : 0 0 c 106 1 0 0 0 0 0 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 47100 ps> : 0 0 c 106 1 0 0 0 1 0 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 47200 ps> : 0 0 d 106 1 0 0 0 0 0 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 47300 ps> : 0 0 d 106 1 0 0 0 1 0 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 47400 ps> : 0 0 e 106 1 0 0 0 0 0 0 0 0 0 ?3 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 47500 ps> : 0 0 e 106 1 0 0 0 1 0 0 0 0 0 ?3 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 47600 ps> : 0 0 f 106 1 0 0 0 0 0 0 0 0 0 ?4 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 47700 ps> : 0 0 f 106 1 0 0 0 1 0 0 0 0 0 ?4 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 47800 ps> : 0 0 4 116 1 0 0 0 0 1 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 47900 ps> : 0 0 4 116 1 0 0 0 1 1 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 48000 ps> : 0 0 5 116 1 0 0 0 0 1 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 48100 ps> : 0 0 5 116 1 0 0 0 1 1 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 48200 ps> : 0 0 6 116 1 0 0 0 0 1 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ; +< 48300 ps> : 0 0 6 116 1 0 0 0 1 1 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ; +< 48400 ps> : 0 0 7 116 1 0 0 0 0 1 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ; +< 48500 ps> : 0 0 7 116 1 0 0 0 1 1 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ; +< 48600 ps> : 0 0 8 116 1 0 0 0 0 1 0 0 0 0 ?d ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ; +< 48700 ps> : 0 0 8 116 1 0 0 0 1 1 0 0 0 0 ?d ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ; +< 48800 ps> : 0 0 9 116 1 0 0 0 0 1 0 0 0 0 ?c ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ; +< 48900 ps> : 0 0 9 116 1 0 0 0 1 1 0 0 0 0 ?c ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ; +< 49000 ps> : 0 0 a 116 1 0 0 0 0 1 0 0 0 0 ?b ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ; +< 49100 ps> : 0 0 a 116 1 0 0 0 1 1 0 0 0 0 ?b ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ; +< 49200 ps> : 0 0 b 116 1 0 0 0 0 1 0 0 0 0 ?a ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ; +< 49300 ps> : 0 0 b 116 1 0 0 0 1 1 0 0 0 0 ?a ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ; +< 49400 ps> : 0 0 c 116 1 0 0 0 0 1 0 0 0 0 ?9 ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ; +< 49500 ps> : 0 0 c 116 1 0 0 0 1 1 0 0 0 0 ?9 ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ; +< 49600 ps> : 0 0 d 116 1 0 0 0 0 1 0 0 0 0 ?8 ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ; +< 49700 ps> : 0 0 d 116 1 0 0 0 1 1 0 0 0 0 ?8 ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ; +< 49800 ps> : 0 0 e 116 1 0 0 0 0 1 0 0 0 0 ?7 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ; +< 49900 ps> : 0 0 e 116 1 0 0 0 1 1 0 0 0 0 ?7 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ; +< 50000 ps> : 0 0 f 116 1 0 0 0 0 1 0 0 0 0 ?6 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ; +< 50100 ps> : 0 0 f 116 1 0 0 0 1 1 0 0 0 0 ?6 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ; +< 50200 ps> : 0 0 0 116 1 0 0 0 0 1 0 0 0 0 ?5 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 50300 ps> : 0 0 0 116 1 0 0 0 1 1 0 0 0 0 ?5 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 50400 ps> : 0 0 1 116 1 0 0 0 0 1 0 0 0 0 ?4 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 50500 ps> : 0 0 1 116 1 0 0 0 1 1 0 0 0 0 ?4 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 50600 ps> : 0 0 2 116 1 0 0 0 0 1 0 0 0 0 ?3 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 50700 ps> : 0 0 2 116 1 0 0 0 1 1 0 0 0 0 ?3 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 50800 ps> : 0 0 3 116 1 0 0 0 0 1 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 50900 ps> : 0 0 3 116 1 0 0 0 1 1 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 51000 ps> : 0 0 8 126 1 0 0 0 0 1 0 0 0 0 ?3 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ; +< 51100 ps> : 0 0 8 126 1 0 0 0 1 1 0 0 0 0 ?3 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ; +< 51200 ps> : 0 0 9 126 1 0 0 0 0 1 0 0 0 0 ?4 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ; +< 51300 ps> : 0 0 9 126 1 0 0 0 1 1 0 0 0 0 ?4 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ; +< 51400 ps> : 0 0 a 126 1 0 0 0 0 1 0 0 0 0 ?5 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ; +< 51500 ps> : 0 0 a 126 1 0 0 0 1 1 0 0 0 0 ?5 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ; +< 51600 ps> : 0 0 b 126 1 0 0 0 0 1 0 0 0 0 ?6 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ; +< 51700 ps> : 0 0 b 126 1 0 0 0 1 1 0 0 0 0 ?6 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ; +< 51800 ps> : 0 0 c 126 1 0 0 0 0 1 0 0 0 0 ?7 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ; +< 51900 ps> : 0 0 c 126 1 0 0 0 1 1 0 0 0 0 ?7 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ; +< 52000 ps> : 0 0 d 126 1 0 0 0 0 1 0 0 0 0 ?8 ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 52100 ps> : 0 0 d 126 1 0 0 0 1 1 0 0 0 0 ?8 ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 52200 ps> : 0 0 e 126 1 0 0 0 0 1 0 0 0 0 ?9 ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 52300 ps> : 0 0 e 126 1 0 0 0 1 1 0 0 0 0 ?9 ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 52400 ps> : 0 0 f 126 1 0 0 0 0 1 0 0 0 0 ?a ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 52500 ps> : 0 0 f 126 1 0 0 0 1 1 0 0 0 0 ?a ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 52600 ps> : 0 0 0 126 1 0 0 0 0 1 0 0 0 0 ?b ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ; +< 52700 ps> : 0 0 0 126 1 0 0 0 1 1 0 0 0 0 ?b ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ; +< 52800 ps> : 0 0 1 126 1 0 0 0 0 1 0 0 0 0 ?c ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ; +< 52900 ps> : 0 0 1 126 1 0 0 0 1 1 0 0 0 0 ?c ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ; +< 53000 ps> : 0 0 2 126 1 0 0 0 0 1 0 0 0 0 ?d ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ; +< 53100 ps> : 0 0 2 126 1 0 0 0 1 1 0 0 0 0 ?d ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ; +< 53200 ps> : 0 0 3 126 1 0 0 0 0 1 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ; +< 53300 ps> : 0 0 3 126 1 0 0 0 1 1 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ; +< 53400 ps> : 0 0 4 126 1 0 0 0 0 1 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ; +< 53500 ps> : 0 0 4 126 1 0 0 0 1 1 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ; +< 53600 ps> : 0 0 5 126 1 0 0 0 0 1 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 53700 ps> : 0 0 5 126 1 0 0 0 1 1 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 53800 ps> : 0 0 6 126 1 0 0 0 0 1 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 53900 ps> : 0 0 6 126 1 0 0 0 1 1 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 54000 ps> : 0 0 7 126 1 0 0 0 0 1 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ; +< 54100 ps> : 0 0 7 126 1 0 0 0 1 1 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ; + +end; diff --git a/alliance/src/documentation/alliance-examples/amd2901/pattern_core.spi b/alliance/src/documentation/alliance-examples/amd2901/pattern_core.spi new file mode 100644 index 00000000..b76e4e8a --- /dev/null +++ b/alliance/src/documentation/alliance-examples/amd2901/pattern_core.spi @@ -0,0 +1,1281 @@ +vinput0 a[3] 0 PWL ( ++ 0PS LOW 1000PS LOW ++ 19300000PS LOW 19301000PS HIGH ++ 22900000PS HIGH 22901000PS LOW ++ 26500000PS LOW 26501000PS HIGH ++ 30100000PS HIGH 30101000PS LOW ++ ) + +vinput1 a[2] 0 PWL ( ++ 0PS LOW 1000PS LOW ++ 17700000PS LOW 17701000PS HIGH ++ 19300000PS HIGH 19301000PS LOW ++ 20900000PS LOW 20901000PS HIGH ++ 22900000PS HIGH 22901000PS LOW ++ 24900000PS LOW 24901000PS HIGH ++ 26500000PS HIGH 26501000PS LOW ++ 28100000PS LOW 28101000PS HIGH ++ 30100000PS HIGH 30101000PS LOW ++ ) + +vinput2 a[1] 0 PWL ( ++ 0PS LOW 1000PS LOW ++ 16900000PS LOW 16901000PS HIGH ++ 17700000PS HIGH 17701000PS LOW ++ 18500000PS LOW 18501000PS HIGH ++ 19300000PS HIGH 19301000PS LOW ++ 20100000PS LOW 20101000PS HIGH ++ 20900000PS HIGH 20901000PS LOW ++ 21700000PS LOW 21701000PS HIGH ++ 22900000PS HIGH 22901000PS LOW ++ 24100000PS LOW 24101000PS HIGH ++ 24900000PS HIGH 24901000PS LOW ++ 25700000PS LOW 25701000PS HIGH ++ 26500000PS HIGH 26501000PS LOW ++ 27300000PS LOW 27301000PS HIGH ++ 28100000PS HIGH 28101000PS LOW ++ 28900000PS LOW 28901000PS HIGH ++ 30100000PS HIGH 30101000PS LOW ++ ) + +vinput3 a[0] 0 PWL ( ++ 0PS LOW 1000PS LOW ++ 16500000PS LOW 16501000PS HIGH ++ 16900000PS HIGH 16901000PS LOW ++ 17300000PS LOW 17301000PS HIGH ++ 17700000PS HIGH 17701000PS LOW ++ 18100000PS LOW 18101000PS HIGH ++ 18500000PS HIGH 18501000PS LOW ++ 18900000PS LOW 18901000PS HIGH ++ 19300000PS HIGH 19301000PS LOW ++ 19700000PS LOW 19701000PS HIGH ++ 20100000PS HIGH 20101000PS LOW ++ 20500000PS LOW 20501000PS HIGH ++ 20900000PS HIGH 20901000PS LOW ++ 21300000PS LOW 21301000PS HIGH ++ 21700000PS HIGH 21701000PS LOW ++ 22100000PS LOW 22101000PS HIGH ++ 22900000PS HIGH 22901000PS LOW ++ 23700000PS LOW 23701000PS HIGH ++ 24100000PS HIGH 24101000PS LOW ++ 24500000PS LOW 24501000PS HIGH ++ 24900000PS HIGH 24901000PS LOW ++ 25300000PS LOW 25301000PS HIGH ++ 25700000PS HIGH 25701000PS LOW ++ 26100000PS LOW 26101000PS HIGH ++ 26500000PS HIGH 26501000PS LOW ++ 26900000PS LOW 26901000PS HIGH ++ 27300000PS HIGH 27301000PS LOW ++ 27700000PS LOW 27701000PS HIGH ++ 28100000PS HIGH 28101000PS LOW ++ 28500000PS LOW 28501000PS HIGH ++ 28900000PS HIGH 28901000PS LOW ++ 29300000PS LOW 29301000PS HIGH ++ 30100000PS HIGH 30101000PS LOW ++ ) + +vinput4 b[3] 0 PWL ( ++ 0PS LOW 1000PS LOW ++ 4500000PS LOW 4501000PS HIGH ++ 4900000PS HIGH 4901000PS LOW ++ 12500000PS LOW 12501000PS HIGH ++ 12900000PS HIGH 12901000PS LOW ++ 19300000PS LOW 19301000PS HIGH ++ 22900000PS HIGH 22901000PS LOW ++ 36900000PS LOW 36901000PS HIGH ++ 43300000PS HIGH 43301000PS LOW ++ ) + +vinput5 b[2] 0 PWL ( ++ 0PS LOW 1000PS LOW ++ 2900000PS LOW 2901000PS HIGH ++ 4500000PS HIGH 4501000PS LOW ++ 6500000PS LOW 6501000PS HIGH ++ 9300000PS HIGH 9301000PS LOW ++ 10900000PS LOW 10901000PS HIGH ++ 12500000PS HIGH 12501000PS LOW ++ 14500000PS LOW 14501000PS HIGH ++ 16100000PS HIGH 16101000PS LOW ++ 17700000PS LOW 17701000PS HIGH ++ 19300000PS HIGH 19301000PS LOW ++ 20900000PS LOW 20901000PS HIGH ++ 22900000PS HIGH 22901000PS LOW ++ 33700000PS LOW 33701000PS HIGH ++ 36900000PS HIGH 36901000PS LOW ++ 40100000PS LOW 40101000PS HIGH ++ 43300000PS HIGH 43301000PS LOW ++ ) + +vinput6 b[1] 0 PWL ( ++ 0PS LOW 1000PS LOW ++ 2100000PS LOW 2101000PS HIGH ++ 2900000PS HIGH 2901000PS LOW ++ 3700000PS LOW 3701000PS HIGH ++ 4500000PS HIGH 4501000PS LOW ++ 5700000PS LOW 5701000PS HIGH ++ 6500000PS HIGH 6501000PS LOW ++ 7300000PS LOW 7301000PS HIGH ++ 9300000PS HIGH 9301000PS LOW ++ 10100000PS LOW 10101000PS HIGH ++ 10900000PS HIGH 10901000PS LOW ++ 11700000PS LOW 11701000PS HIGH ++ 12500000PS HIGH 12501000PS LOW ++ 13700000PS LOW 13701000PS HIGH ++ 14500000PS HIGH 14501000PS LOW ++ 15300000PS LOW 15301000PS HIGH ++ 16100000PS HIGH 16101000PS LOW ++ 16900000PS LOW 16901000PS HIGH ++ 17700000PS HIGH 17701000PS LOW ++ 18500000PS LOW 18501000PS HIGH ++ 19300000PS HIGH 19301000PS LOW ++ 20100000PS LOW 20101000PS HIGH ++ 20900000PS HIGH 20901000PS LOW ++ 21700000PS LOW 21701000PS HIGH ++ 22900000PS HIGH 22901000PS LOW ++ 32100000PS LOW 32101000PS HIGH ++ 33700000PS HIGH 33701000PS LOW ++ 35300000PS LOW 35301000PS HIGH ++ 36900000PS HIGH 36901000PS LOW ++ 38500000PS LOW 38501000PS HIGH ++ 40100000PS HIGH 40101000PS LOW ++ 41700000PS LOW 41701000PS HIGH ++ 43300000PS HIGH 43301000PS LOW ++ ) + +vinput7 b[0] 0 PWL ( ++ 0PS LOW 1000PS LOW ++ 1700000PS LOW 1701000PS HIGH ++ 2100000PS HIGH 2101000PS LOW ++ 2500000PS LOW 2501000PS HIGH ++ 2900000PS HIGH 2901000PS LOW ++ 3300000PS LOW 3301000PS HIGH ++ 3700000PS HIGH 3701000PS LOW ++ 4100000PS LOW 4101000PS HIGH ++ 4500000PS HIGH 4501000PS LOW ++ 5300000PS LOW 5301000PS HIGH ++ 5700000PS HIGH 5701000PS LOW ++ 6100000PS LOW 6101000PS HIGH ++ 6500000PS HIGH 6501000PS LOW ++ 6900000PS LOW 6901000PS HIGH ++ 7300000PS HIGH 7301000PS LOW ++ 7700000PS LOW 7701000PS HIGH ++ 9300000PS HIGH 9301000PS LOW ++ 9700000PS LOW 9701000PS HIGH ++ 10100000PS HIGH 10101000PS LOW ++ 10500000PS LOW 10501000PS HIGH ++ 10900000PS HIGH 10901000PS LOW ++ 11300000PS LOW 11301000PS HIGH ++ 11700000PS HIGH 11701000PS LOW ++ 12100000PS LOW 12101000PS HIGH ++ 12500000PS HIGH 12501000PS LOW ++ 13300000PS LOW 13301000PS HIGH ++ 13700000PS HIGH 13701000PS LOW ++ 14100000PS LOW 14101000PS HIGH ++ 14500000PS HIGH 14501000PS LOW ++ 14900000PS LOW 14901000PS HIGH ++ 15300000PS HIGH 15301000PS LOW ++ 15700000PS LOW 15701000PS HIGH ++ 16100000PS HIGH 16101000PS LOW ++ 16500000PS LOW 16501000PS HIGH ++ 16900000PS HIGH 16901000PS LOW ++ 17300000PS LOW 17301000PS HIGH ++ 17700000PS HIGH 17701000PS LOW ++ 18100000PS LOW 18101000PS HIGH ++ 18500000PS HIGH 18501000PS LOW ++ 18900000PS LOW 18901000PS HIGH ++ 19300000PS HIGH 19301000PS LOW ++ 19700000PS LOW 19701000PS HIGH ++ 20100000PS HIGH 20101000PS LOW ++ 20500000PS LOW 20501000PS HIGH ++ 20900000PS HIGH 20901000PS LOW ++ 21300000PS LOW 21301000PS HIGH ++ 21700000PS HIGH 21701000PS LOW ++ 22100000PS LOW 22101000PS HIGH ++ 22900000PS HIGH 22901000PS LOW ++ 31300000PS LOW 31301000PS HIGH ++ 32100000PS HIGH 32101000PS LOW ++ 32900000PS LOW 32901000PS HIGH ++ 33700000PS HIGH 33701000PS LOW ++ 34500000PS LOW 34501000PS HIGH ++ 35300000PS HIGH 35301000PS LOW ++ 36100000PS LOW 36101000PS HIGH ++ 36900000PS HIGH 36901000PS LOW ++ 37700000PS LOW 37701000PS HIGH ++ 38500000PS HIGH 38501000PS LOW ++ 39300000PS LOW 39301000PS HIGH ++ 40100000PS HIGH 40101000PS LOW ++ 40900000PS LOW 40901000PS HIGH ++ 41700000PS HIGH 41701000PS LOW ++ 42500000PS LOW 42501000PS HIGH ++ 43300000PS HIGH 43301000PS LOW ++ ) + +vinput8 d[3] 0 PWL ( ++ 0PS HIGH 1000PS HIGH ++ 500000PS HIGH 501000PS LOW ++ 900000PS LOW 901000PS HIGH ++ 8500000PS HIGH 8501000PS LOW ++ 8900000PS LOW 8901000PS HIGH ++ 16100000PS HIGH 16101000PS LOW ++ 19300000PS LOW 19301000PS HIGH ++ 22900000PS HIGH 22901000PS LOW ++ 46500000PS LOW 46501000PS HIGH ++ 49700000PS HIGH 49701000PS LOW ++ 52900000PS LOW 52901000PS HIGH ++ 56100000PS HIGH 56101000PS LOW ++ 59300000PS LOW 59301000PS HIGH ++ 62500000PS HIGH 62501000PS LOW ++ 65700000PS LOW 65701000PS HIGH ++ 68900000PS HIGH 68901000PS LOW ++ 72100000PS LOW 72101000PS HIGH ++ 75300000PS HIGH 75301000PS LOW ++ 78500000PS LOW 78501000PS HIGH ++ 81700000PS HIGH 81701000PS LOW ++ 84900000PS LOW 84901000PS HIGH ++ 88100000PS HIGH 88101000PS LOW ++ 92500000PS LOW 92501000PS HIGH ++ 95700000PS HIGH 95701000PS LOW ++ 97300000PS LOW 97301000PS HIGH ++ 100500000PS HIGH 100501000PS LOW ++ 102100000PS LOW 102101000PS HIGH ++ 105300000PS HIGH 105301000PS LOW ++ ) + +vinput9 d[2] 0 PWL ( ++ 0PS LOW 1000PS LOW ++ 500000PS LOW 501000PS HIGH ++ 900000PS HIGH 901000PS LOW ++ 8500000PS LOW 8501000PS HIGH ++ 8900000PS HIGH 8901000PS LOW ++ 17700000PS LOW 17701000PS HIGH ++ 19300000PS HIGH 19301000PS LOW ++ 20900000PS LOW 20901000PS HIGH ++ 22900000PS HIGH 22901000PS LOW ++ 44900000PS LOW 44901000PS HIGH ++ 46500000PS HIGH 46501000PS LOW ++ 48100000PS LOW 48101000PS HIGH ++ 49700000PS HIGH 49701000PS LOW ++ 51300000PS LOW 51301000PS HIGH ++ 52900000PS HIGH 52901000PS LOW ++ 54500000PS LOW 54501000PS HIGH ++ 56100000PS HIGH 56101000PS LOW ++ 57700000PS LOW 57701000PS HIGH ++ 59300000PS HIGH 59301000PS LOW ++ 60900000PS LOW 60901000PS HIGH ++ 62500000PS HIGH 62501000PS LOW ++ 64100000PS LOW 64101000PS HIGH ++ 65700000PS HIGH 65701000PS LOW ++ 67300000PS LOW 67301000PS HIGH ++ 68900000PS HIGH 68901000PS LOW ++ 70500000PS LOW 70501000PS HIGH ++ 72100000PS HIGH 72101000PS LOW ++ 73700000PS LOW 73701000PS HIGH ++ 75300000PS HIGH 75301000PS LOW ++ 76900000PS LOW 76901000PS HIGH ++ 78500000PS HIGH 78501000PS LOW ++ 80100000PS LOW 80101000PS HIGH ++ 81700000PS HIGH 81701000PS LOW ++ 83300000PS LOW 83301000PS HIGH ++ 84900000PS HIGH 84901000PS LOW ++ 86500000PS LOW 86501000PS HIGH ++ 89300000PS HIGH 89301000PS LOW ++ 90900000PS LOW 90901000PS HIGH ++ 92500000PS HIGH 92501000PS LOW ++ 94100000PS LOW 94101000PS HIGH ++ 97300000PS HIGH 97301000PS LOW ++ 98900000PS LOW 98901000PS HIGH ++ 100500000PS HIGH 100501000PS LOW ++ 103700000PS LOW 103701000PS HIGH ++ 105300000PS HIGH 105301000PS LOW ++ 106900000PS LOW 106901000PS HIGH ++ ) + +vinput10 d[1] 0 PWL ( ++ 0PS HIGH 1000PS HIGH ++ 500000PS HIGH 501000PS LOW ++ 900000PS LOW 901000PS HIGH ++ 8500000PS HIGH 8501000PS LOW ++ 8900000PS LOW 8901000PS HIGH ++ 16100000PS HIGH 16101000PS LOW ++ 16900000PS LOW 16901000PS HIGH ++ 17700000PS HIGH 17701000PS LOW ++ 18500000PS LOW 18501000PS HIGH ++ 19300000PS HIGH 19301000PS LOW ++ 20100000PS LOW 20101000PS HIGH ++ 20900000PS HIGH 20901000PS LOW ++ 21700000PS LOW 21701000PS HIGH ++ 22900000PS HIGH 22901000PS LOW ++ 44100000PS LOW 44101000PS HIGH ++ 44900000PS HIGH 44901000PS LOW ++ 45700000PS LOW 45701000PS HIGH ++ 46500000PS HIGH 46501000PS LOW ++ 47300000PS LOW 47301000PS HIGH ++ 48100000PS HIGH 48101000PS LOW ++ 48900000PS LOW 48901000PS HIGH ++ 49700000PS HIGH 49701000PS LOW ++ 50500000PS LOW 50501000PS HIGH ++ 51300000PS HIGH 51301000PS LOW ++ 52100000PS LOW 52101000PS HIGH ++ 52900000PS HIGH 52901000PS LOW ++ 53700000PS LOW 53701000PS HIGH ++ 54500000PS HIGH 54501000PS LOW ++ 55300000PS LOW 55301000PS HIGH ++ 56100000PS HIGH 56101000PS LOW ++ 56900000PS LOW 56901000PS HIGH ++ 57700000PS HIGH 57701000PS LOW ++ 58500000PS LOW 58501000PS HIGH ++ 59300000PS HIGH 59301000PS LOW ++ 60100000PS LOW 60101000PS HIGH ++ 60900000PS HIGH 60901000PS LOW ++ 61700000PS LOW 61701000PS HIGH ++ 62500000PS HIGH 62501000PS LOW ++ 63300000PS LOW 63301000PS HIGH ++ 64100000PS HIGH 64101000PS LOW ++ 64900000PS LOW 64901000PS HIGH ++ 65700000PS HIGH 65701000PS LOW ++ 66500000PS LOW 66501000PS HIGH ++ 67300000PS HIGH 67301000PS LOW ++ 68100000PS LOW 68101000PS HIGH ++ 68900000PS HIGH 68901000PS LOW ++ 69700000PS LOW 69701000PS HIGH ++ 70500000PS HIGH 70501000PS LOW ++ 71300000PS LOW 71301000PS HIGH ++ 72100000PS HIGH 72101000PS LOW ++ 72900000PS LOW 72901000PS HIGH ++ 73700000PS HIGH 73701000PS LOW ++ 74500000PS LOW 74501000PS HIGH ++ 75300000PS HIGH 75301000PS LOW ++ 76100000PS LOW 76101000PS HIGH ++ 76900000PS HIGH 76901000PS LOW ++ 77700000PS LOW 77701000PS HIGH ++ 78500000PS HIGH 78501000PS LOW ++ 79300000PS LOW 79301000PS HIGH ++ 80100000PS HIGH 80101000PS LOW ++ 80900000PS LOW 80901000PS HIGH ++ 81700000PS HIGH 81701000PS LOW ++ 82500000PS LOW 82501000PS HIGH ++ 83300000PS HIGH 83301000PS LOW ++ 84100000PS LOW 84101000PS HIGH ++ 84900000PS HIGH 84901000PS LOW ++ 85700000PS LOW 85701000PS HIGH ++ 86500000PS HIGH 86501000PS LOW ++ 87300000PS LOW 87301000PS HIGH ++ 88100000PS HIGH 88101000PS LOW ++ 90100000PS LOW 90101000PS HIGH ++ 90900000PS HIGH 90901000PS LOW ++ 91700000PS LOW 91701000PS HIGH ++ 92500000PS HIGH 92501000PS LOW ++ 93300000PS LOW 93301000PS HIGH ++ 94100000PS HIGH 94101000PS LOW ++ 94900000PS LOW 94901000PS HIGH ++ 95700000PS HIGH 95701000PS LOW ++ 96500000PS LOW 96501000PS HIGH ++ 97300000PS HIGH 97301000PS LOW ++ 98100000PS LOW 98101000PS HIGH ++ 98900000PS HIGH 98901000PS LOW ++ 99700000PS LOW 99701000PS HIGH ++ 100500000PS HIGH 100501000PS LOW ++ 101300000PS LOW 101301000PS HIGH ++ 102100000PS HIGH 102101000PS LOW ++ 102900000PS LOW 102901000PS HIGH ++ 103700000PS HIGH 103701000PS LOW ++ 104500000PS LOW 104501000PS HIGH ++ 105300000PS HIGH 105301000PS LOW ++ 106100000PS LOW 106101000PS HIGH ++ 106900000PS HIGH 106901000PS LOW ++ 107700000PS LOW 107701000PS HIGH ++ ) + +vinput11 d[0] 0 PWL ( ++ 0PS LOW 1000PS LOW ++ 500000PS LOW 501000PS HIGH ++ 900000PS HIGH 901000PS LOW ++ 8500000PS LOW 8501000PS HIGH ++ 8900000PS HIGH 8901000PS LOW ++ 16500000PS LOW 16501000PS HIGH ++ 16900000PS HIGH 16901000PS LOW ++ 17300000PS LOW 17301000PS HIGH ++ 17700000PS HIGH 17701000PS LOW ++ 18100000PS LOW 18101000PS HIGH ++ 18500000PS HIGH 18501000PS LOW ++ 18900000PS LOW 18901000PS HIGH ++ 19300000PS HIGH 19301000PS LOW ++ 19700000PS LOW 19701000PS HIGH ++ 20100000PS HIGH 20101000PS LOW ++ 20500000PS LOW 20501000PS HIGH ++ 20900000PS HIGH 20901000PS LOW ++ 21300000PS LOW 21301000PS HIGH ++ 21700000PS HIGH 21701000PS LOW ++ 22100000PS LOW 22101000PS HIGH ++ 22900000PS HIGH 22901000PS LOW ++ 43700000PS LOW 43701000PS HIGH ++ 44100000PS HIGH 44101000PS LOW ++ 44500000PS LOW 44501000PS HIGH ++ 44900000PS HIGH 44901000PS LOW ++ 45300000PS LOW 45301000PS HIGH ++ 45700000PS HIGH 45701000PS LOW ++ 46100000PS LOW 46101000PS HIGH ++ 46500000PS HIGH 46501000PS LOW ++ 46900000PS LOW 46901000PS HIGH ++ 47300000PS HIGH 47301000PS LOW ++ 47700000PS LOW 47701000PS HIGH ++ 48100000PS HIGH 48101000PS LOW ++ 48500000PS LOW 48501000PS HIGH ++ 48900000PS HIGH 48901000PS LOW ++ 49300000PS LOW 49301000PS HIGH ++ 49700000PS HIGH 49701000PS LOW ++ 50100000PS LOW 50101000PS HIGH ++ 50500000PS HIGH 50501000PS LOW ++ 50900000PS LOW 50901000PS HIGH ++ 51300000PS HIGH 51301000PS LOW ++ 51700000PS LOW 51701000PS HIGH ++ 52100000PS HIGH 52101000PS LOW ++ 52500000PS LOW 52501000PS HIGH ++ 52900000PS HIGH 52901000PS LOW ++ 53300000PS LOW 53301000PS HIGH ++ 53700000PS HIGH 53701000PS LOW ++ 54100000PS LOW 54101000PS HIGH ++ 54500000PS HIGH 54501000PS LOW ++ 54900000PS LOW 54901000PS HIGH ++ 55300000PS HIGH 55301000PS LOW ++ 55700000PS LOW 55701000PS HIGH ++ 56100000PS HIGH 56101000PS LOW ++ 56500000PS LOW 56501000PS HIGH ++ 56900000PS HIGH 56901000PS LOW ++ 57300000PS LOW 57301000PS HIGH ++ 57700000PS HIGH 57701000PS LOW ++ 58100000PS LOW 58101000PS HIGH ++ 58500000PS HIGH 58501000PS LOW ++ 58900000PS LOW 58901000PS HIGH ++ 59300000PS HIGH 59301000PS LOW ++ 59700000PS LOW 59701000PS HIGH ++ 60100000PS HIGH 60101000PS LOW ++ 60500000PS LOW 60501000PS HIGH ++ 60900000PS HIGH 60901000PS LOW ++ 61300000PS LOW 61301000PS HIGH ++ 61700000PS HIGH 61701000PS LOW ++ 62100000PS LOW 62101000PS HIGH ++ 62500000PS HIGH 62501000PS LOW ++ 62900000PS LOW 62901000PS HIGH ++ 63300000PS HIGH 63301000PS LOW ++ 63700000PS LOW 63701000PS HIGH ++ 64100000PS HIGH 64101000PS LOW ++ 64500000PS LOW 64501000PS HIGH ++ 64900000PS HIGH 64901000PS LOW ++ 65300000PS LOW 65301000PS HIGH ++ 65700000PS HIGH 65701000PS LOW ++ 66100000PS LOW 66101000PS HIGH ++ 66500000PS HIGH 66501000PS LOW ++ 66900000PS LOW 66901000PS HIGH ++ 67300000PS HIGH 67301000PS LOW ++ 67700000PS LOW 67701000PS HIGH ++ 68100000PS HIGH 68101000PS LOW ++ 68500000PS LOW 68501000PS HIGH ++ 68900000PS HIGH 68901000PS LOW ++ 69300000PS LOW 69301000PS HIGH ++ 69700000PS HIGH 69701000PS LOW ++ 70100000PS LOW 70101000PS HIGH ++ 70500000PS HIGH 70501000PS LOW ++ 70900000PS LOW 70901000PS HIGH ++ 71300000PS HIGH 71301000PS LOW ++ 71700000PS LOW 71701000PS HIGH ++ 72100000PS HIGH 72101000PS LOW ++ 72500000PS LOW 72501000PS HIGH ++ 72900000PS HIGH 72901000PS LOW ++ 73300000PS LOW 73301000PS HIGH ++ 73700000PS HIGH 73701000PS LOW ++ 74100000PS LOW 74101000PS HIGH ++ 74500000PS HIGH 74501000PS LOW ++ 74900000PS LOW 74901000PS HIGH ++ 75300000PS HIGH 75301000PS LOW ++ 75700000PS LOW 75701000PS HIGH ++ 76100000PS HIGH 76101000PS LOW ++ 76500000PS LOW 76501000PS HIGH ++ 76900000PS HIGH 76901000PS LOW ++ 77300000PS LOW 77301000PS HIGH ++ 77700000PS HIGH 77701000PS LOW ++ 78100000PS LOW 78101000PS HIGH ++ 78500000PS HIGH 78501000PS LOW ++ 78900000PS LOW 78901000PS HIGH ++ 79300000PS HIGH 79301000PS LOW ++ 79700000PS LOW 79701000PS HIGH ++ 80100000PS HIGH 80101000PS LOW ++ 80500000PS LOW 80501000PS HIGH ++ 80900000PS HIGH 80901000PS LOW ++ 81300000PS LOW 81301000PS HIGH ++ 81700000PS HIGH 81701000PS LOW ++ 82100000PS LOW 82101000PS HIGH ++ 82500000PS HIGH 82501000PS LOW ++ 82900000PS LOW 82901000PS HIGH ++ 83300000PS HIGH 83301000PS LOW ++ 83700000PS LOW 83701000PS HIGH ++ 84100000PS HIGH 84101000PS LOW ++ 84500000PS LOW 84501000PS HIGH ++ 84900000PS HIGH 84901000PS LOW ++ 85300000PS LOW 85301000PS HIGH ++ 85700000PS HIGH 85701000PS LOW ++ 86100000PS LOW 86101000PS HIGH ++ 86500000PS HIGH 86501000PS LOW ++ 86900000PS LOW 86901000PS HIGH ++ 87300000PS HIGH 87301000PS LOW ++ 87700000PS LOW 87701000PS HIGH ++ 89300000PS HIGH 89301000PS LOW ++ 89700000PS LOW 89701000PS HIGH ++ 90100000PS HIGH 90101000PS LOW ++ 90500000PS LOW 90501000PS HIGH ++ 90900000PS HIGH 90901000PS LOW ++ 91300000PS LOW 91301000PS HIGH ++ 91700000PS HIGH 91701000PS LOW ++ 92100000PS LOW 92101000PS HIGH ++ 92500000PS HIGH 92501000PS LOW ++ 92900000PS LOW 92901000PS HIGH ++ 93300000PS HIGH 93301000PS LOW ++ 93700000PS LOW 93701000PS HIGH ++ 94100000PS HIGH 94101000PS LOW ++ 94500000PS LOW 94501000PS HIGH ++ 94900000PS HIGH 94901000PS LOW ++ 95300000PS LOW 95301000PS HIGH ++ 95700000PS HIGH 95701000PS LOW ++ 96100000PS LOW 96101000PS HIGH ++ 96500000PS HIGH 96501000PS LOW ++ 96900000PS LOW 96901000PS HIGH ++ 97300000PS HIGH 97301000PS LOW ++ 97700000PS LOW 97701000PS HIGH ++ 98100000PS HIGH 98101000PS LOW ++ 98500000PS LOW 98501000PS HIGH ++ 98900000PS HIGH 98901000PS LOW ++ 99300000PS LOW 99301000PS HIGH ++ 99700000PS HIGH 99701000PS LOW ++ 100100000PS LOW 100101000PS HIGH ++ 100500000PS HIGH 100501000PS LOW ++ 100900000PS LOW 100901000PS HIGH ++ 101300000PS HIGH 101301000PS LOW ++ 101700000PS LOW 101701000PS HIGH ++ 102100000PS HIGH 102101000PS LOW ++ 102500000PS LOW 102501000PS HIGH ++ 102900000PS HIGH 102901000PS LOW ++ 103300000PS LOW 103301000PS HIGH ++ 103700000PS HIGH 103701000PS LOW ++ 104100000PS LOW 104101000PS HIGH ++ 104500000PS HIGH 104501000PS LOW ++ 104900000PS LOW 104901000PS HIGH ++ 105300000PS HIGH 105301000PS LOW ++ 105700000PS LOW 105701000PS HIGH ++ 106100000PS HIGH 106101000PS LOW ++ 106500000PS LOW 106501000PS HIGH ++ 106900000PS HIGH 106901000PS LOW ++ 107300000PS LOW 107301000PS HIGH ++ 107700000PS HIGH 107701000PS LOW ++ 108100000PS LOW 108101000PS HIGH ++ ) + +vinput12 i[8] 0 PWL ( ++ 0PS LOW 1000PS LOW ++ 1300000PS LOW 1301000PS HIGH ++ 4900000PS HIGH 4901000PS LOW ++ 9300000PS LOW 9301000PS HIGH ++ 12900000PS HIGH 12901000PS LOW ++ ) + +vinput13 i[7] 0 PWL ( ++ 0PS LOW 1000PS LOW ++ 9300000PS LOW 9301000PS HIGH ++ 12900000PS HIGH 12901000PS LOW ++ 16100000PS LOW 16101000PS HIGH ++ 22900000PS HIGH 22901000PS LOW ++ ) + +vinput14 i[6] 0 PWL ( ++ 0PS LOW 1000PS LOW ++ 4900000PS LOW 4901000PS HIGH ++ 8100000PS HIGH 8101000PS LOW ++ 12900000PS LOW 12901000PS HIGH ++ 88100000PS HIGH 88101000PS LOW ++ 89300000PS LOW 89301000PS HIGH ++ ) + +vinput15 i[5] 0 PWL ( ++ 0PS LOW 1000PS LOW ++ 1300000PS LOW 1301000PS HIGH ++ 8100000PS HIGH 8101000PS LOW ++ 9300000PS LOW 9301000PS HIGH ++ 16100000PS HIGH 16101000PS LOW ++ 68900000PS LOW 68901000PS HIGH ++ 88100000PS HIGH 88101000PS LOW ++ ) + +vinput16 i[4] 0 PWL ( ++ 0PS LOW 1000PS LOW ++ 900000PS LOW 901000PS HIGH ++ 8100000PS HIGH 8101000PS LOW ++ 8900000PS LOW 8901000PS HIGH ++ 43300000PS HIGH 43301000PS LOW ++ 56100000PS LOW 56101000PS HIGH ++ 88100000PS HIGH 88101000PS LOW ++ 102100000PS LOW 102101000PS HIGH ++ ) + +vinput17 i[3] 0 PWL ( ++ 0PS LOW 1000PS LOW ++ 900000PS LOW 901000PS HIGH ++ 1300000PS HIGH 1301000PS LOW ++ 8900000PS LOW 8901000PS HIGH ++ 9300000PS HIGH 9301000PS LOW ++ 16100000PS LOW 16101000PS HIGH ++ 43300000PS HIGH 43301000PS LOW ++ 49700000PS LOW 49701000PS HIGH ++ 56100000PS HIGH 56101000PS LOW ++ 81700000PS LOW 81701000PS HIGH ++ 88100000PS HIGH 88101000PS LOW ++ 95700000PS LOW 95701000PS HIGH ++ 102100000PS HIGH 102101000PS LOW ++ ) + +vinput18 i[2] 0 PWL ( ++ 0PS HIGH 1000PS HIGH ++ 900000PS HIGH 901000PS LOW ++ 8100000PS LOW 8101000PS HIGH ++ 8900000PS HIGH 8901000PS LOW ++ 16100000PS LOW 16101000PS HIGH ++ 30500000PS HIGH 30501000PS LOW ++ 43300000PS LOW 43301000PS HIGH ++ ) + +vinput19 i[1] 0 PWL ( ++ 0PS HIGH 1000PS HIGH ++ 23300000PS HIGH 23301000PS LOW ++ 30100000PS LOW 30101000PS HIGH ++ ) + +vinput20 i[0] 0 PWL ( ++ 0PS HIGH 1000PS HIGH ++ 900000PS HIGH 901000PS LOW ++ 4900000PS LOW 4901000PS HIGH ++ 8900000PS HIGH 8901000PS LOW ++ 12900000PS LOW 12901000PS HIGH ++ 23300000PS HIGH 23301000PS LOW ++ 30100000PS LOW 30101000PS HIGH ++ 89300000PS HIGH 89301000PS LOW ++ ) + +vinput21 fonc 0 PWL ( ++ 0PS HIGH 1000PS HIGH ++ ) + +vinput22 test 0 PWL ( ++ 0PS LOW 1000PS LOW ++ ) + +vinput23 scin 0 PWL ( ++ 0PS LOW 1000PS LOW ++ ) + +vinput24 noe 0 PWL ( ++ 0PS LOW 1000PS LOW ++ ) + +vinput25 ck 0 PWL ( ++ 0PS LOW 1000PS LOW ++ 300000PS LOW 301000PS HIGH ++ 500000PS HIGH 501000PS LOW ++ 700000PS LOW 701000PS HIGH ++ 900000PS HIGH 901000PS LOW ++ 1100000PS LOW 1101000PS HIGH ++ 1300000PS HIGH 1301000PS LOW ++ 1500000PS LOW 1501000PS HIGH ++ 1700000PS HIGH 1701000PS LOW ++ 1900000PS LOW 1901000PS HIGH ++ 2100000PS HIGH 2101000PS LOW ++ 2300000PS LOW 2301000PS HIGH ++ 2500000PS HIGH 2501000PS LOW ++ 2700000PS LOW 2701000PS HIGH ++ 2900000PS HIGH 2901000PS LOW ++ 3100000PS LOW 3101000PS HIGH ++ 3300000PS HIGH 3301000PS LOW ++ 3500000PS LOW 3501000PS HIGH ++ 3700000PS HIGH 3701000PS LOW ++ 3900000PS LOW 3901000PS HIGH ++ 4100000PS HIGH 4101000PS LOW ++ 4300000PS LOW 4301000PS HIGH ++ 4500000PS HIGH 4501000PS LOW ++ 4700000PS LOW 4701000PS HIGH ++ 4900000PS HIGH 4901000PS LOW ++ 5100000PS LOW 5101000PS HIGH ++ 5300000PS HIGH 5301000PS LOW ++ 5500000PS LOW 5501000PS HIGH ++ 5700000PS HIGH 5701000PS LOW ++ 5900000PS LOW 5901000PS HIGH ++ 6100000PS HIGH 6101000PS LOW ++ 6300000PS LOW 6301000PS HIGH ++ 6500000PS HIGH 6501000PS LOW ++ 6700000PS LOW 6701000PS HIGH ++ 6900000PS HIGH 6901000PS LOW ++ 7100000PS LOW 7101000PS HIGH ++ 7300000PS HIGH 7301000PS LOW ++ 7500000PS LOW 7501000PS HIGH ++ 7700000PS HIGH 7701000PS LOW ++ 7900000PS LOW 7901000PS HIGH ++ 8100000PS HIGH 8101000PS LOW ++ 8300000PS LOW 8301000PS HIGH ++ 8500000PS HIGH 8501000PS LOW ++ 8700000PS LOW 8701000PS HIGH ++ 8900000PS HIGH 8901000PS LOW ++ 9100000PS LOW 9101000PS HIGH ++ 9300000PS HIGH 9301000PS LOW ++ 9500000PS LOW 9501000PS HIGH ++ 9700000PS HIGH 9701000PS LOW ++ 9900000PS LOW 9901000PS HIGH ++ 10100000PS HIGH 10101000PS LOW ++ 10300000PS LOW 10301000PS HIGH ++ 10500000PS HIGH 10501000PS LOW ++ 10700000PS LOW 10701000PS HIGH ++ 10900000PS HIGH 10901000PS LOW ++ 11100000PS LOW 11101000PS HIGH ++ 11300000PS HIGH 11301000PS LOW ++ 11500000PS LOW 11501000PS HIGH ++ 11700000PS HIGH 11701000PS LOW ++ 11900000PS LOW 11901000PS HIGH ++ 12100000PS HIGH 12101000PS LOW ++ 12300000PS LOW 12301000PS HIGH ++ 12500000PS HIGH 12501000PS LOW ++ 12700000PS LOW 12701000PS HIGH ++ 12900000PS HIGH 12901000PS LOW ++ 13100000PS LOW 13101000PS HIGH ++ 13300000PS HIGH 13301000PS LOW ++ 13500000PS LOW 13501000PS HIGH ++ 13700000PS HIGH 13701000PS LOW ++ 13900000PS LOW 13901000PS HIGH ++ 14100000PS HIGH 14101000PS LOW ++ 14300000PS LOW 14301000PS HIGH ++ 14500000PS HIGH 14501000PS LOW ++ 14700000PS LOW 14701000PS HIGH ++ 14900000PS HIGH 14901000PS LOW ++ 15100000PS LOW 15101000PS HIGH ++ 15300000PS HIGH 15301000PS LOW ++ 15500000PS LOW 15501000PS HIGH ++ 15700000PS HIGH 15701000PS LOW ++ 15900000PS LOW 15901000PS HIGH ++ 16100000PS HIGH 16101000PS LOW ++ 16300000PS LOW 16301000PS HIGH ++ 16500000PS HIGH 16501000PS LOW ++ 16700000PS LOW 16701000PS HIGH ++ 16900000PS HIGH 16901000PS LOW ++ 17100000PS LOW 17101000PS HIGH ++ 17300000PS HIGH 17301000PS LOW ++ 17500000PS LOW 17501000PS HIGH ++ 17700000PS HIGH 17701000PS LOW ++ 17900000PS LOW 17901000PS HIGH ++ 18100000PS HIGH 18101000PS LOW ++ 18300000PS LOW 18301000PS HIGH ++ 18500000PS HIGH 18501000PS LOW ++ 18700000PS LOW 18701000PS HIGH ++ 18900000PS HIGH 18901000PS LOW ++ 19100000PS LOW 19101000PS HIGH ++ 19300000PS HIGH 19301000PS LOW ++ 19500000PS LOW 19501000PS HIGH ++ 19700000PS HIGH 19701000PS LOW ++ 19900000PS LOW 19901000PS HIGH ++ 20100000PS HIGH 20101000PS LOW ++ 20300000PS LOW 20301000PS HIGH ++ 20500000PS HIGH 20501000PS LOW ++ 20700000PS LOW 20701000PS HIGH ++ 20900000PS HIGH 20901000PS LOW ++ 21100000PS LOW 21101000PS HIGH ++ 21300000PS HIGH 21301000PS LOW ++ 21500000PS LOW 21501000PS HIGH ++ 21700000PS HIGH 21701000PS LOW ++ 21900000PS LOW 21901000PS HIGH ++ 22100000PS HIGH 22101000PS LOW ++ 22300000PS LOW 22301000PS HIGH ++ 22500000PS HIGH 22501000PS LOW ++ 22700000PS LOW 22701000PS HIGH ++ 22900000PS HIGH 22901000PS LOW ++ 23100000PS LOW 23101000PS HIGH ++ 23300000PS HIGH 23301000PS LOW ++ 23500000PS LOW 23501000PS HIGH ++ 23700000PS HIGH 23701000PS LOW ++ 23900000PS LOW 23901000PS HIGH ++ 24100000PS HIGH 24101000PS LOW ++ 24300000PS LOW 24301000PS HIGH ++ 24500000PS HIGH 24501000PS LOW ++ 24700000PS LOW 24701000PS HIGH ++ 24900000PS HIGH 24901000PS LOW ++ 25100000PS LOW 25101000PS HIGH ++ 25300000PS HIGH 25301000PS LOW ++ 25500000PS LOW 25501000PS HIGH ++ 25700000PS HIGH 25701000PS LOW ++ 25900000PS LOW 25901000PS HIGH ++ 26100000PS HIGH 26101000PS LOW ++ 26300000PS LOW 26301000PS HIGH ++ 26500000PS HIGH 26501000PS LOW ++ 26700000PS LOW 26701000PS HIGH ++ 26900000PS HIGH 26901000PS LOW ++ 27100000PS LOW 27101000PS HIGH ++ 27300000PS HIGH 27301000PS LOW ++ 27500000PS LOW 27501000PS HIGH ++ 27700000PS HIGH 27701000PS LOW ++ 27900000PS LOW 27901000PS HIGH ++ 28100000PS HIGH 28101000PS LOW ++ 28300000PS LOW 28301000PS HIGH ++ 28500000PS HIGH 28501000PS LOW ++ 28700000PS LOW 28701000PS HIGH ++ 28900000PS HIGH 28901000PS LOW ++ 29100000PS LOW 29101000PS HIGH ++ 29300000PS HIGH 29301000PS LOW ++ 29500000PS LOW 29501000PS HIGH ++ 29700000PS HIGH 29701000PS LOW ++ 29900000PS LOW 29901000PS HIGH ++ 30100000PS HIGH 30101000PS LOW ++ 30300000PS LOW 30301000PS HIGH ++ 30500000PS HIGH 30501000PS LOW ++ 30700000PS LOW 30701000PS HIGH ++ 30900000PS HIGH 30901000PS LOW ++ 31100000PS LOW 31101000PS HIGH ++ 31300000PS HIGH 31301000PS LOW ++ 31500000PS LOW 31501000PS HIGH ++ 31700000PS HIGH 31701000PS LOW ++ 31900000PS LOW 31901000PS HIGH ++ 32100000PS HIGH 32101000PS LOW ++ 32300000PS LOW 32301000PS HIGH ++ 32500000PS HIGH 32501000PS LOW ++ 32700000PS LOW 32701000PS HIGH ++ 32900000PS HIGH 32901000PS LOW ++ 33100000PS LOW 33101000PS HIGH ++ 33300000PS HIGH 33301000PS LOW ++ 33500000PS LOW 33501000PS HIGH ++ 33700000PS HIGH 33701000PS LOW ++ 33900000PS LOW 33901000PS HIGH ++ 34100000PS HIGH 34101000PS LOW ++ 34300000PS LOW 34301000PS HIGH ++ 34500000PS HIGH 34501000PS LOW ++ 34700000PS LOW 34701000PS HIGH ++ 34900000PS HIGH 34901000PS LOW ++ 35100000PS LOW 35101000PS HIGH ++ 35300000PS HIGH 35301000PS LOW ++ 35500000PS LOW 35501000PS HIGH ++ 35700000PS HIGH 35701000PS LOW ++ 35900000PS LOW 35901000PS HIGH ++ 36100000PS HIGH 36101000PS LOW ++ 36300000PS LOW 36301000PS HIGH ++ 36500000PS HIGH 36501000PS LOW ++ 36700000PS LOW 36701000PS HIGH ++ 36900000PS HIGH 36901000PS LOW ++ 37100000PS LOW 37101000PS HIGH ++ 37300000PS HIGH 37301000PS LOW ++ 37500000PS LOW 37501000PS HIGH ++ 37700000PS HIGH 37701000PS LOW ++ 37900000PS LOW 37901000PS HIGH ++ 38100000PS HIGH 38101000PS LOW ++ 38300000PS LOW 38301000PS HIGH ++ 38500000PS HIGH 38501000PS LOW ++ 38700000PS LOW 38701000PS HIGH ++ 38900000PS HIGH 38901000PS LOW ++ 39100000PS LOW 39101000PS HIGH ++ 39300000PS HIGH 39301000PS LOW ++ 39500000PS LOW 39501000PS HIGH ++ 39700000PS HIGH 39701000PS LOW ++ 39900000PS LOW 39901000PS HIGH ++ 40100000PS HIGH 40101000PS LOW ++ 40300000PS LOW 40301000PS HIGH ++ 40500000PS HIGH 40501000PS LOW ++ 40700000PS LOW 40701000PS HIGH ++ 40900000PS HIGH 40901000PS LOW ++ 41100000PS LOW 41101000PS HIGH ++ 41300000PS HIGH 41301000PS LOW ++ 41500000PS LOW 41501000PS HIGH ++ 41700000PS HIGH 41701000PS LOW ++ 41900000PS LOW 41901000PS HIGH ++ 42100000PS HIGH 42101000PS LOW ++ 42300000PS LOW 42301000PS HIGH ++ 42500000PS HIGH 42501000PS LOW ++ 42700000PS LOW 42701000PS HIGH ++ 42900000PS HIGH 42901000PS LOW ++ 43100000PS LOW 43101000PS HIGH ++ 43300000PS HIGH 43301000PS LOW ++ 43500000PS LOW 43501000PS HIGH ++ 43700000PS HIGH 43701000PS LOW ++ 43900000PS LOW 43901000PS HIGH ++ 44100000PS HIGH 44101000PS LOW ++ 44300000PS LOW 44301000PS HIGH ++ 44500000PS HIGH 44501000PS LOW ++ 44700000PS LOW 44701000PS HIGH ++ 44900000PS HIGH 44901000PS LOW ++ 45100000PS LOW 45101000PS HIGH ++ 45300000PS HIGH 45301000PS LOW ++ 45500000PS LOW 45501000PS HIGH ++ 45700000PS HIGH 45701000PS LOW ++ 45900000PS LOW 45901000PS HIGH ++ 46100000PS HIGH 46101000PS LOW ++ 46300000PS LOW 46301000PS HIGH ++ 46500000PS HIGH 46501000PS LOW ++ 46700000PS LOW 46701000PS HIGH ++ 46900000PS HIGH 46901000PS LOW ++ 47100000PS LOW 47101000PS HIGH ++ 47300000PS HIGH 47301000PS LOW ++ 47500000PS LOW 47501000PS HIGH ++ 47700000PS HIGH 47701000PS LOW ++ 47900000PS LOW 47901000PS HIGH ++ 48100000PS HIGH 48101000PS LOW ++ 48300000PS LOW 48301000PS HIGH ++ 48500000PS HIGH 48501000PS LOW ++ 48700000PS LOW 48701000PS HIGH ++ 48900000PS HIGH 48901000PS LOW ++ 49100000PS LOW 49101000PS HIGH ++ 49300000PS HIGH 49301000PS LOW ++ 49500000PS LOW 49501000PS HIGH ++ 49700000PS HIGH 49701000PS LOW ++ 49900000PS LOW 49901000PS HIGH ++ 50100000PS HIGH 50101000PS LOW ++ 50300000PS LOW 50301000PS HIGH ++ 50500000PS HIGH 50501000PS LOW ++ 50700000PS LOW 50701000PS HIGH ++ 50900000PS HIGH 50901000PS LOW ++ 51100000PS LOW 51101000PS HIGH ++ 51300000PS HIGH 51301000PS LOW ++ 51500000PS LOW 51501000PS HIGH ++ 51700000PS HIGH 51701000PS LOW ++ 51900000PS LOW 51901000PS HIGH ++ 52100000PS HIGH 52101000PS LOW ++ 52300000PS LOW 52301000PS HIGH ++ 52500000PS HIGH 52501000PS LOW ++ 52700000PS LOW 52701000PS HIGH ++ 52900000PS HIGH 52901000PS LOW ++ 53100000PS LOW 53101000PS HIGH ++ 53300000PS HIGH 53301000PS LOW ++ 53500000PS LOW 53501000PS HIGH ++ 53700000PS HIGH 53701000PS LOW ++ 53900000PS LOW 53901000PS HIGH ++ 54100000PS HIGH 54101000PS LOW ++ 54300000PS LOW 54301000PS HIGH ++ 54500000PS HIGH 54501000PS LOW ++ 54700000PS LOW 54701000PS HIGH ++ 54900000PS HIGH 54901000PS LOW ++ 55100000PS LOW 55101000PS HIGH ++ 55300000PS HIGH 55301000PS LOW ++ 55500000PS LOW 55501000PS HIGH ++ 55700000PS HIGH 55701000PS LOW ++ 55900000PS LOW 55901000PS HIGH ++ 56100000PS HIGH 56101000PS LOW ++ 56300000PS LOW 56301000PS HIGH ++ 56500000PS HIGH 56501000PS LOW ++ 56700000PS LOW 56701000PS HIGH ++ 56900000PS HIGH 56901000PS LOW ++ 57100000PS LOW 57101000PS HIGH ++ 57300000PS HIGH 57301000PS LOW ++ 57500000PS LOW 57501000PS HIGH ++ 57700000PS HIGH 57701000PS LOW ++ 57900000PS LOW 57901000PS HIGH ++ 58100000PS HIGH 58101000PS LOW ++ 58300000PS LOW 58301000PS HIGH ++ 58500000PS HIGH 58501000PS LOW ++ 58700000PS LOW 58701000PS HIGH ++ 58900000PS HIGH 58901000PS LOW ++ 59100000PS LOW 59101000PS HIGH ++ 59300000PS HIGH 59301000PS LOW ++ 59500000PS LOW 59501000PS HIGH ++ 59700000PS HIGH 59701000PS LOW ++ 59900000PS LOW 59901000PS HIGH ++ 60100000PS HIGH 60101000PS LOW ++ 60300000PS LOW 60301000PS HIGH ++ 60500000PS HIGH 60501000PS LOW ++ 60700000PS LOW 60701000PS HIGH ++ 60900000PS HIGH 60901000PS LOW ++ 61100000PS LOW 61101000PS HIGH ++ 61300000PS HIGH 61301000PS LOW ++ 61500000PS LOW 61501000PS HIGH ++ 61700000PS HIGH 61701000PS LOW ++ 61900000PS LOW 61901000PS HIGH ++ 62100000PS HIGH 62101000PS LOW ++ 62300000PS LOW 62301000PS HIGH ++ 62500000PS HIGH 62501000PS LOW ++ 62700000PS LOW 62701000PS HIGH ++ 62900000PS HIGH 62901000PS LOW ++ 63100000PS LOW 63101000PS HIGH ++ 63300000PS HIGH 63301000PS LOW ++ 63500000PS LOW 63501000PS HIGH ++ 63700000PS HIGH 63701000PS LOW ++ 63900000PS LOW 63901000PS HIGH ++ 64100000PS HIGH 64101000PS LOW ++ 64300000PS LOW 64301000PS HIGH ++ 64500000PS HIGH 64501000PS LOW ++ 64700000PS LOW 64701000PS HIGH ++ 64900000PS HIGH 64901000PS LOW ++ 65100000PS LOW 65101000PS HIGH ++ 65300000PS HIGH 65301000PS LOW ++ 65500000PS LOW 65501000PS HIGH ++ 65700000PS HIGH 65701000PS LOW ++ 65900000PS LOW 65901000PS HIGH ++ 66100000PS HIGH 66101000PS LOW ++ 66300000PS LOW 66301000PS HIGH ++ 66500000PS HIGH 66501000PS LOW ++ 66700000PS LOW 66701000PS HIGH ++ 66900000PS HIGH 66901000PS LOW ++ 67100000PS LOW 67101000PS HIGH ++ 67300000PS HIGH 67301000PS LOW ++ 67500000PS LOW 67501000PS HIGH ++ 67700000PS HIGH 67701000PS LOW ++ 67900000PS LOW 67901000PS HIGH ++ 68100000PS HIGH 68101000PS LOW ++ 68300000PS LOW 68301000PS HIGH ++ 68500000PS HIGH 68501000PS LOW ++ 68700000PS LOW 68701000PS HIGH ++ 68900000PS HIGH 68901000PS LOW ++ 69100000PS LOW 69101000PS HIGH ++ 69300000PS HIGH 69301000PS LOW ++ 69500000PS LOW 69501000PS HIGH ++ 69700000PS HIGH 69701000PS LOW ++ 69900000PS LOW 69901000PS HIGH ++ 70100000PS HIGH 70101000PS LOW ++ 70300000PS LOW 70301000PS HIGH ++ 70500000PS HIGH 70501000PS LOW ++ 70700000PS LOW 70701000PS HIGH ++ 70900000PS HIGH 70901000PS LOW ++ 71100000PS LOW 71101000PS HIGH ++ 71300000PS HIGH 71301000PS LOW ++ 71500000PS LOW 71501000PS HIGH ++ 71700000PS HIGH 71701000PS LOW ++ 71900000PS LOW 71901000PS HIGH ++ 72100000PS HIGH 72101000PS LOW ++ 72300000PS LOW 72301000PS HIGH ++ 72500000PS HIGH 72501000PS LOW ++ 72700000PS LOW 72701000PS HIGH ++ 72900000PS HIGH 72901000PS LOW ++ 73100000PS LOW 73101000PS HIGH ++ 73300000PS HIGH 73301000PS LOW ++ 73500000PS LOW 73501000PS HIGH ++ 73700000PS HIGH 73701000PS LOW ++ 73900000PS LOW 73901000PS HIGH ++ 74100000PS HIGH 74101000PS LOW ++ 74300000PS LOW 74301000PS HIGH ++ 74500000PS HIGH 74501000PS LOW ++ 74700000PS LOW 74701000PS HIGH ++ 74900000PS HIGH 74901000PS LOW ++ 75100000PS LOW 75101000PS HIGH ++ 75300000PS HIGH 75301000PS LOW ++ 75500000PS LOW 75501000PS HIGH ++ 75700000PS HIGH 75701000PS LOW ++ 75900000PS LOW 75901000PS HIGH ++ 76100000PS HIGH 76101000PS LOW ++ 76300000PS LOW 76301000PS HIGH ++ 76500000PS HIGH 76501000PS LOW ++ 76700000PS LOW 76701000PS HIGH ++ 76900000PS HIGH 76901000PS LOW ++ 77100000PS LOW 77101000PS HIGH ++ 77300000PS HIGH 77301000PS LOW ++ 77500000PS LOW 77501000PS HIGH ++ 77700000PS HIGH 77701000PS LOW ++ 77900000PS LOW 77901000PS HIGH ++ 78100000PS HIGH 78101000PS LOW ++ 78300000PS LOW 78301000PS HIGH ++ 78500000PS HIGH 78501000PS LOW ++ 78700000PS LOW 78701000PS HIGH ++ 78900000PS HIGH 78901000PS LOW ++ 79100000PS LOW 79101000PS HIGH ++ 79300000PS HIGH 79301000PS LOW ++ 79500000PS LOW 79501000PS HIGH ++ 79700000PS HIGH 79701000PS LOW ++ 79900000PS LOW 79901000PS HIGH ++ 80100000PS HIGH 80101000PS LOW ++ 80300000PS LOW 80301000PS HIGH ++ 80500000PS HIGH 80501000PS LOW ++ 80700000PS LOW 80701000PS HIGH ++ 80900000PS HIGH 80901000PS LOW ++ 81100000PS LOW 81101000PS HIGH ++ 81300000PS HIGH 81301000PS LOW ++ 81500000PS LOW 81501000PS HIGH ++ 81700000PS HIGH 81701000PS LOW ++ 81900000PS LOW 81901000PS HIGH ++ 82100000PS HIGH 82101000PS LOW ++ 82300000PS LOW 82301000PS HIGH ++ 82500000PS HIGH 82501000PS LOW ++ 82700000PS LOW 82701000PS HIGH ++ 82900000PS HIGH 82901000PS LOW ++ 83100000PS LOW 83101000PS HIGH ++ 83300000PS HIGH 83301000PS LOW ++ 83500000PS LOW 83501000PS HIGH ++ 83700000PS HIGH 83701000PS LOW ++ 83900000PS LOW 83901000PS HIGH ++ 84100000PS HIGH 84101000PS LOW ++ 84300000PS LOW 84301000PS HIGH ++ 84500000PS HIGH 84501000PS LOW ++ 84700000PS LOW 84701000PS HIGH ++ 84900000PS HIGH 84901000PS LOW ++ 85100000PS LOW 85101000PS HIGH ++ 85300000PS HIGH 85301000PS LOW ++ 85500000PS LOW 85501000PS HIGH ++ 85700000PS HIGH 85701000PS LOW ++ 85900000PS LOW 85901000PS HIGH ++ 86100000PS HIGH 86101000PS LOW ++ 86300000PS LOW 86301000PS HIGH ++ 86500000PS HIGH 86501000PS LOW ++ 86700000PS LOW 86701000PS HIGH ++ 86900000PS HIGH 86901000PS LOW ++ 87100000PS LOW 87101000PS HIGH ++ 87300000PS HIGH 87301000PS LOW ++ 87500000PS LOW 87501000PS HIGH ++ 87700000PS HIGH 87701000PS LOW ++ 87900000PS LOW 87901000PS HIGH ++ 88100000PS HIGH 88101000PS LOW ++ 88300000PS LOW 88301000PS HIGH ++ 88500000PS HIGH 88501000PS LOW ++ 88700000PS LOW 88701000PS HIGH ++ 88900000PS HIGH 88901000PS LOW ++ 89100000PS LOW 89101000PS HIGH ++ 89300000PS HIGH 89301000PS LOW ++ 89500000PS LOW 89501000PS HIGH ++ 89700000PS HIGH 89701000PS LOW ++ 89900000PS LOW 89901000PS HIGH ++ 90100000PS HIGH 90101000PS LOW ++ 90300000PS LOW 90301000PS HIGH ++ 90500000PS HIGH 90501000PS LOW ++ 90700000PS LOW 90701000PS HIGH ++ 90900000PS HIGH 90901000PS LOW ++ 91100000PS LOW 91101000PS HIGH ++ 91300000PS HIGH 91301000PS LOW ++ 91500000PS LOW 91501000PS HIGH ++ 91700000PS HIGH 91701000PS LOW ++ 91900000PS LOW 91901000PS HIGH ++ 92100000PS HIGH 92101000PS LOW ++ 92300000PS LOW 92301000PS HIGH ++ 92500000PS HIGH 92501000PS LOW ++ 92700000PS LOW 92701000PS HIGH ++ 92900000PS HIGH 92901000PS LOW ++ 93100000PS LOW 93101000PS HIGH ++ 93300000PS HIGH 93301000PS LOW ++ 93500000PS LOW 93501000PS HIGH ++ 93700000PS HIGH 93701000PS LOW ++ 93900000PS LOW 93901000PS HIGH ++ 94100000PS HIGH 94101000PS LOW ++ 94300000PS LOW 94301000PS HIGH ++ 94500000PS HIGH 94501000PS LOW ++ 94700000PS LOW 94701000PS HIGH ++ 94900000PS HIGH 94901000PS LOW ++ 95100000PS LOW 95101000PS HIGH ++ 95300000PS HIGH 95301000PS LOW ++ 95500000PS LOW 95501000PS HIGH ++ 95700000PS HIGH 95701000PS LOW ++ 95900000PS LOW 95901000PS HIGH ++ 96100000PS HIGH 96101000PS LOW ++ 96300000PS LOW 96301000PS HIGH ++ 96500000PS HIGH 96501000PS LOW ++ 96700000PS LOW 96701000PS HIGH ++ 96900000PS HIGH 96901000PS LOW ++ 97100000PS LOW 97101000PS HIGH ++ 97300000PS HIGH 97301000PS LOW ++ 97500000PS LOW 97501000PS HIGH ++ 97700000PS HIGH 97701000PS LOW ++ 97900000PS LOW 97901000PS HIGH ++ 98100000PS HIGH 98101000PS LOW ++ 98300000PS LOW 98301000PS HIGH ++ 98500000PS HIGH 98501000PS LOW ++ 98700000PS LOW 98701000PS HIGH ++ 98900000PS HIGH 98901000PS LOW ++ 99100000PS LOW 99101000PS HIGH ++ 99300000PS HIGH 99301000PS LOW ++ 99500000PS LOW 99501000PS HIGH ++ 99700000PS HIGH 99701000PS LOW ++ 99900000PS LOW 99901000PS HIGH ++ 100100000PS HIGH 100101000PS LOW ++ 100300000PS LOW 100301000PS HIGH ++ 100500000PS HIGH 100501000PS LOW ++ 100700000PS LOW 100701000PS HIGH ++ 100900000PS HIGH 100901000PS LOW ++ 101100000PS LOW 101101000PS HIGH ++ 101300000PS HIGH 101301000PS LOW ++ 101500000PS LOW 101501000PS HIGH ++ 101700000PS HIGH 101701000PS LOW ++ 101900000PS LOW 101901000PS HIGH ++ 102100000PS HIGH 102101000PS LOW ++ 102300000PS LOW 102301000PS HIGH ++ 102500000PS HIGH 102501000PS LOW ++ 102700000PS LOW 102701000PS HIGH ++ 102900000PS HIGH 102901000PS LOW ++ 103100000PS LOW 103101000PS HIGH ++ 103300000PS HIGH 103301000PS LOW ++ 103500000PS LOW 103501000PS HIGH ++ 103700000PS HIGH 103701000PS LOW ++ 103900000PS LOW 103901000PS HIGH ++ 104100000PS HIGH 104101000PS LOW ++ 104300000PS LOW 104301000PS HIGH ++ 104500000PS HIGH 104501000PS LOW ++ 104700000PS LOW 104701000PS HIGH ++ 104900000PS HIGH 104901000PS LOW ++ 105100000PS LOW 105101000PS HIGH ++ 105300000PS HIGH 105301000PS LOW ++ 105500000PS LOW 105501000PS HIGH ++ 105700000PS HIGH 105701000PS LOW ++ 105900000PS LOW 105901000PS HIGH ++ 106100000PS HIGH 106101000PS LOW ++ 106300000PS LOW 106301000PS HIGH ++ 106500000PS HIGH 106501000PS LOW ++ 106700000PS LOW 106701000PS HIGH ++ 106900000PS HIGH 106901000PS LOW ++ 107100000PS LOW 107101000PS HIGH ++ 107300000PS HIGH 107301000PS LOW ++ 107500000PS LOW 107501000PS HIGH ++ 107700000PS HIGH 107701000PS LOW ++ 107900000PS LOW 107901000PS HIGH ++ 108100000PS HIGH 108101000PS LOW ++ 108300000PS LOW 108301000PS HIGH ++ ) + +vinput26 cin 0 PWL ( ++ 0PS LOW 1000PS LOW ++ 49700000PS LOW 49701000PS HIGH ++ 68900000PS HIGH 68901000PS LOW ++ 95700000PS LOW 95701000PS HIGH ++ ) + +vinput27 ram_i_down 0 PWL ( ++ 0PS LOW 1000PS LOW ++ 9700000PS LOW 9701000PS HIGH ++ 10100000PS HIGH 10101000PS LOW ++ 10500000PS LOW 10501000PS HIGH ++ 10900000PS HIGH 10901000PS LOW ++ 11300000PS LOW 11301000PS HIGH ++ 11700000PS HIGH 11701000PS LOW ++ 12100000PS LOW 12101000PS HIGH ++ 12500000PS HIGH 12501000PS LOW ++ ) + +vinput29 ram_i_up 0 PWL ( ++ 0PS LOW 1000PS LOW ++ 1300000PS LOW 1301000PS HIGH ++ 1700000PS HIGH 1701000PS LOW ++ 2100000PS LOW 2101000PS HIGH ++ 2500000PS HIGH 2501000PS LOW ++ 2900000PS LOW 2901000PS HIGH ++ 3300000PS HIGH 3301000PS LOW ++ 3700000PS LOW 3701000PS HIGH ++ 4100000PS HIGH 4101000PS LOW ++ 4500000PS LOW 4501000PS HIGH ++ 8100000PS HIGH 8101000PS LOW ++ ) + +vinput31 acc_i_down 0 PWL ( ++ 0PS LOW 1000PS LOW ++ 9700000PS LOW 9701000PS HIGH ++ 10100000PS HIGH 10101000PS LOW ++ 10500000PS LOW 10501000PS HIGH ++ 10900000PS HIGH 10901000PS LOW ++ 11300000PS LOW 11301000PS HIGH ++ 11700000PS HIGH 11701000PS LOW ++ 12100000PS LOW 12101000PS HIGH ++ 12500000PS HIGH 12501000PS LOW ++ ) + +vinput33 acc_i_up 0 PWL ( ++ 0PS LOW 1000PS LOW ++ 1300000PS LOW 1301000PS HIGH ++ 1700000PS HIGH 1701000PS LOW ++ 2100000PS LOW 2101000PS HIGH ++ 2500000PS HIGH 2501000PS LOW ++ 2900000PS LOW 2901000PS HIGH ++ 3300000PS HIGH 3301000PS LOW ++ 3700000PS LOW 3701000PS HIGH ++ 4100000PS HIGH 4101000PS LOW ++ 4500000PS LOW 4501000PS HIGH ++ 8100000PS HIGH 8101000PS LOW ++ ) + +