Ganesh Gore 7db7c240e3 [FPGA1212_V1] Updated design + Added buffer on IO_EN net + Tie Off floating module inputs + Complete DRC/Timing closed		2020-11-29 10:24:03 -07:00
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FPGA1212_FLAT_HD_SKY_Verilog	[FPGA1212_V1] Updated design + Added buffer on IO_EN net + Tie Off floating module inputs + Complete DRC/Timing closed	2020-11-29 10:24:03 -07:00
FPGA1212_FLAT_HD_SKY_task	[FPGA1212_V1] Updated design + Added buffer on IO_EN net + Tie Off floating module inputs + Complete DRC/Timing closed	2020-11-29 10:24:03 -07:00
Verification	Added FPGA12x12 with CocoTB tests	2020-11-21 16:07:09 -07:00
fpga_top	[FPGA1212_V1] Updated design + Added buffer on IO_EN net + Tie Off floating module inputs + Complete DRC/Timing closed	2020-11-29 10:24:03 -07:00
config.sh	Added FPGA12x12 with CocoTB tests	2020-11-21 16:07:09 -07:00