Tarachand Pagarani dec0a0e160 further changes to add 4 clock buffer tiles		2021-02-01 04:32:22 -08:00
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openfpga_shell_script	further changes to add 4 clock buffer tiles	2021-02-01 04:32:22 -08:00
openfpga_simulation_setting	further changes to add 4 clock buffer tiles	2021-02-01 04:32:22 -08:00
skywater_openfpga_task	Enabling custom yosys script only for and gate design, will enable later for other designs when yosys submodule is updated	2021-01-07 01:15:41 -08:00
magic_drc_to_rdb.py	[Action] Updated action script for local run	2020-12-14 12:08:16 -07:00
merge_caravel_klayout.py	[Action] More cleanup while precheck	2020-12-20 17:04:56 -07:00
merge_fpga_top.tcl	[BugFix] After Integration with mpw-one-b	2020-12-17 09:29:54 -07:00
repo_setup.py	[Script] Now batch task run will error out in the first failed task	2020-11-26 18:30:01 -07:00