riscv
/
SOFA
mirror of https://github.com/lnis-uofu/SOFA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
SOFA/FPGA1212_SOFA_HD_PNR
History
Ganesh Gore f8c34abb2f [DRCFix] Fixed filler cell boundary 2021-02-10 15:29:34 -07:00
..
FPGA1212_SOFA_HD_Verilog [SOFA_HD] Updated netlist and task 2020-12-14 01:14:14 -07:00
FPGA1212_SOFA_HD_task Replacing deprecated tile_port syntax 2021-01-12 21:33:53 -08:00
Verification [SOFA_HD] Updated verification script 2020-12-14 01:16:30 -07:00
fpga_top [DRCFix] Fixed filler cell boundary 2021-02-10 15:29:34 -07:00
modules Updated all the results 2020-12-20 03:44:00 -07:00
README.md Updated all the results 2020-12-20 03:44:00 -07:00
config.sh Updated all the results 2020-12-20 03:44:00 -07:00

README.md

FPGA1212_SOFA_HD_PNR

12x12 FPGA designed using hierarchical flow and SKY130_FD_SC_HD. Flat Module design style