Ganesh Gore 7db7c240e3 [FPGA1212_V1] Updated design + Added buffer on IO_EN net + Tie Off floating module inputs + Complete DRC/Timing closed		2020-11-29 10:24:03 -07:00
..
fpga_top_icv_in_design.fm.v	[FPGA1212_V1] Updated design + Added buffer on IO_EN net + Tie Off floating module inputs + Complete DRC/Timing closed	2020-11-29 10:24:03 -07:00
fpga_top_icv_in_design.gds.gz	[FPGA1212_V1] Updated design + Added buffer on IO_EN net + Tie Off floating module inputs + Complete DRC/Timing closed	2020-11-29 10:24:03 -07:00
fpga_top_icv_in_design.lef	Added FPGA12x12 with CocoTB tests	2020-11-21 16:07:09 -07:00
fpga_top_icv_in_design.lvs.v	[FPGA1212_V1] Updated design + Added buffer on IO_EN net + Tie Off floating module inputs + Complete DRC/Timing closed	2020-11-29 10:24:03 -07:00
fpga_top_icv_in_design.nominal_25.spef	[FPGA1212_V1] Updated design + Added buffer on IO_EN net + Tie Off floating module inputs + Complete DRC/Timing closed	2020-11-29 10:24:03 -07:00
fpga_top_icv_in_design.pt.v	[FPGA1212_V1] Updated design + Added buffer on IO_EN net + Tie Off floating module inputs + Complete DRC/Timing closed	2020-11-29 10:24:03 -07:00
fpga_top_icv_in_design.top_only.pt.v	[FPGA1212_V1] Updated design + Added buffer on IO_EN net + Tie Off floating module inputs + Complete DRC/Timing closed	2020-11-29 10:24:03 -07:00