mirror of https://github.com/lnis-uofu/SOFA.git
64 lines
3.4 KiB
Verilog
64 lines
3.4 KiB
Verilog
//////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE SD Card Controller IP Core ////
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//// ////
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//// edge_detect.v ////
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//// ////
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//// This file is part of the WISHBONE SD Card ////
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//// Controller IP Core project ////
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//// http://opencores.org/project,sd_card_controller ////
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//// ////
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//// Description ////
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//// Signal edge detection. If input signal transitions between ////
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//// two states, output signal is generated for one clock cycle. ////
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//// ////
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//// Author(s): ////
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//// - Marek Czerski, ma.czerski@gmail.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2013 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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module edge_detect (
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input rst,
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input clk,
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input sig,
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output rise,
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output fall
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);
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reg [1:0] sig_reg;
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always @(posedge clk or posedge rst)
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if (rst == 1'b1)
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sig_reg <= 2'b00;
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else
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sig_reg <= {sig_reg[0], sig};
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assign rise = sig_reg[0] == 1'b1 && sig_reg[1] == 1'b0 ? 1'b1 : 1'b0;
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assign fall = sig_reg[0] == 1'b0 && sig_reg[1] == 1'b1 ? 1'b1 : 1'b0;
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endmodule |