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SOFA/FPGA1212_QLSOFA_HD_PNR
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WRansohoff b4e3440972
Fix parsing error in FPGA1212_QLSOFA arch file. 
I was pointed to this task as a starting point for generating an FPGA on the skywater PDK, and I think this small change is necessary to get the task to run with:

`python3 openfpga_flow/scripts/run_fpga_task.py FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/`
 		2021-02-05 11:36:29 -06:00
..
FPGA1212_QLSOFA_HD_Verilog [QLSOFA] Bugfix to fix floating cin net 2020-12-22 00:23:37 -07:00
FPGA1212_QLSOFA_HD_task Fix parsing error in FPGA1212_QLSOFA arch file. 2021-02-05 11:36:29 -06:00
Verification [QLSOFA_HD] Updated QLSOFA_HD Verification results 2020-12-14 13:38:08 -07:00
fpga_top [QLSOFA] Bugfix to fix floating cin net 2020-12-22 00:23:37 -07:00
modules [QLSOFA] Bugfix to fix floating cin net 2020-12-22 00:23:37 -07:00
README.md Updated all the results 2020-12-20 03:44:00 -07:00
config.sh [QLSOFA] Bugfix to fix floating cin net 2020-12-22 00:23:37 -07:00

README.md

FPGA1212_FLAT_HD_SKY_PNR

12x12 FPGA designed using hierarchical flow and SKY130_FD_SC_HD. Flat Module design style