mirror of https://github.com/lnis-uofu/SOFA.git
5 lines
342 B
Plaintext
5 lines
342 B
Plaintext
SrcLoc, DestLoc
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FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/,OpenFPGA_task
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FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
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FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
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SOFA-Chips/HDL/common/user_project_wrapper_integration.v,verilog/gl/user_project_wrapper.v |