History

tangxifan 7b2632a872 [Testbench] Add power pin support to scff testbench		2020-12-18 15:55:05 -07:00
..
README.md	[Doc] Update README for python script	2020-11-27 10:29:32 -07:00
caravel_fpga_io_test_gl_include_netlists.v	[Testbench] Add testbenches for RTL and Gate-level netlists of Caravel	2020-12-15 16:13:34 -07:00
ccff_test_post_pnr_v1.0.v	[Testbench] Now ccff and scff testbench template have multiple versions corresponding to the FPGA variants	2020-12-02 15:22:19 -07:00
ccff_test_post_pnr_v1.1.v	[Testbench] Patch ccff test	2020-12-02 20:07:36 -07:00
generate_post_pnr_testbenches.py	[Testbench] Bug fix in calling sub python script	2020-12-01 08:14:43 -07:00
post_pnr_fpga_cells.v	[Testbench] Restore post-Pnr testbenches for CHD version	2020-12-14 13:17:37 -07:00
post_pnr_testbench_converter.py	[Testbench] Update scripts to rename top-level module for post-PnR testbenches	2020-11-28 14:29:56 -07:00
post_pnr_wrapper_testbench_converter.py	[Testbench] Add a tempo fix on the analog pins	2020-11-29 22:32:36 -07:00
pre_pnr_ccff_test.v	[Testbench] Add configuration chain test benches for pre- and post- pnr simulation	2020-11-18 15:58:00 -07:00
scff_test_post_pnr_v1.0.v	[Testbench] Now ccff and scff testbench template have multiple versions corresponding to the FPGA variants	2020-12-02 15:22:19 -07:00
scff_test_post_pnr_v1.1.v	[Testbench] Add power pin support to scff testbench	2020-12-18 15:55:05 -07:00

Skywater PDK

This directory contains the commonly used testbench templates for FPGA verification

**post_pnr_testbench_converter.py: The python script to convert an auto-generated pre-PnR testbench to the post-PnR testbench tuned for final layout
post_pnr_fpga_cells.v: The netlist that includes all the standard cells used by the post-PnRed FPGA fabric
Pre-PnR testbenches
- pre_pnr_ccff_test.v: The template testbench for post-PnR verification on the configuration chain
Post-PnR testbenches
- post_pnr_ccff_test.v: The template testbench for post-PnR verification on the configuration chain
- post_pnr_scff_test.v: The template testbench for post-PnR verification on the scan chain