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tangxifan 66b3710d53 [Script] Improve setup script to auto setup the openfpga task-run 2020-10-14 11:06:37 -06:00
ARCH [Architecture] Add a set of openfpga architectures using different Skywater Foundry standard cells 2020-10-14 09:11:05 -06:00
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SCRIPT [Script] Improve setup script to auto setup the openfpga task-run 2020-10-14 11:06:37 -06:00
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README.md [Documentation] Update frontpage README for guidelines 2020-10-14 09:50:37 -06:00

README.md

skywater-openfpga

FPGA tape-outs using the open-source Skywater 130nm PDK and OpenFPGA

Quick Start

#Clone the repository and go inside it
git clone https://github.com/LNIS-Projects/skywater-openfpga.git
python3 SCRIPT/repo_setup.py

  • Keep this folder clean and organized as follows

    • DOC: documentation of the project
    • ARCH: Architecture XML and other input files which OpenFPGA requires to generate Verilog netlists
    • BENCHMARK: Benchmarks to be tested on the FPGA fabric
    • HDL: Hardware description netlists for the FPGA fabrics
    • SDC: design constraints
    • SCRIPT: Scripts to setup, run OpenFPGA etc.
    • TESTBENCH: Verilog testbenches generated by OpenFPGA
    • PDK: Technology files linked from skywater opensource pdk
    • SNPS_ICC2: workspace of Synopsys IC Compiler 2 Keep a README inside the folder about the ICC2 version and how-to-use.
    • MSIM: workspace of verification using Mentor ModelSim

  • Note:

    • Please ONLY place folders under this directory. README should be the ONLY file under this directory
    • Each EDA tool should have independent workspace in separated directories