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SOFA/FPGA1212_SOFA_HD_PNR
History
Ganesh Gore 3a472b0db0 [Flow] Adding Makefile for running task 2021-04-03 17:54:59 -06:00
..
FPGA1212_SOFA_HD_Verilog [SOFA_HD] Updated netlist and task 2020-12-14 01:14:14 -07:00
FPGA1212_SOFA_HD_task [Flow] Adding Makefile for running task 2021-04-03 17:54:59 -06:00
Verification [SOFA_HD] Updated verification script 2020-12-14 01:16:30 -07:00
fpga_top [DRCFix] Fixed filler cell boundary 2021-02-10 15:29:34 -07:00
modules Updated all the results 2020-12-20 03:44:00 -07:00
Makefile [Flow] Adding Makefile for running task 2021-04-03 17:54:59 -06:00
README.md Updated all the results 2020-12-20 03:44:00 -07:00
config.sh Updated all the results 2020-12-20 03:44:00 -07:00

README.md

FPGA1212_SOFA_HD_PNR

12x12 FPGA designed using hierarchical flow and SKY130_FD_SC_HD. Flat Module design style