mirror of https://github.com/lnis-uofu/SOFA.git
160 lines
5.3 KiB
Verilog
160 lines
5.3 KiB
Verilog
/*
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*-------------------------------------------------------------
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*
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* A wrapper for the FPGA IP to fit the I/O interface of Caravel SoC
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*
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* The wrapper is a technology mapped netlist where the mode-switch
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* multiplexers are mapped to the Skywater 130nm
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* High-Density (HD) standard cells
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*
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*-------------------------------------------------------------
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*/
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module fpga_top (
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// Fixed I/O interface from Caravel SoC definition
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// DO NOT CHANGE!!!
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inout vdda1, // User area 1 3.3V supply
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inout vdda2, // User area 2 3.3V supply
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inout vssa1, // User area 1 analog ground
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inout vssa2, // User area 2 analog ground
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inout vccd1, // User area 1 1.8V supply
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inout vccd2, // User area 2 1.8v supply
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inout vssd1, // User area 1 digital ground
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inout vssd2, // User area 2 digital ground
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// Wishbone Slave ports (WB MI A)
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input wb_clk_i,
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input wb_rst_i,
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input wbs_stb_i,
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input wbs_cyc_i,
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input wbs_we_i,
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input [3:0] wbs_sel_i,
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input [31:0] wbs_dat_i,
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input [31:0] wbs_adr_i,
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output wbs_ack_o,
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output [31:0] wbs_dat_o,
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// Logic Analyzer Signals
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input [127:0] la_data_in,
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output [127:0] la_data_out,
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input [127:0] la_oen,
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// IOs
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input [37:0] io_in,
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output [37:0] io_out,
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output [37:0] io_oeb
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);
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// Modelsim does NOT like redefining wires that already in the
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// input/output ports. The follow lines may be needed when
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// `default_nettype none
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// is enabled
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//wire [`MPRJ_IO_PADS-1:0] io_in;
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//wire [`MPRJ_IO_PADS-1:0] io_out;
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//wire [`MPRJ_IO_PADS-1:0] io_oeb;
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// FPGA wires
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wire prog_clk;
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wire Test_en;
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wire io_isol_n;
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wire clk;
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wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
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wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
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wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
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wire ccff_head;
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wire ccff_tail;
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wire sc_head;
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wire sc_tail;
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// Switch between wishbone and logic analyzer
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wire wb_la_switch;
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wire wb_la_switch_b;
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// Inverted switch signal to drive tri-state buffers
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// Use drive strength 8 as we will have 33 output pins which is driven by
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// the buffers
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sky130_fd_sc_hd__inv_8 WB_LA_SWITCH_INV (.A(la_wb_switch), .Y(la_wb_switch_b));
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// Wire-bond TOP side I/O of FPGA to LEFT-side of Caravel interface
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assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] = io_in[24];
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assign io_out[24] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0];
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assign io_oeb[24] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0];
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// Wire-bond TOP side I/O of FPGA to TOP-side of Caravel interface
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assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1:9] = io_in[23:15];
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assign io_out[23:15] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1:9];
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assign io_oeb[23:15] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1:9];
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// Wire-bond TOP side I/O of FPGA to RIGHT-side of Caravel interface
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assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[10:11] = io_in[14:13];
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assign io_out[14:13] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10:11];
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assign io_oeb[14:13] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[10:11];
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// Wire-bond RIGHT side I/O of FPGA to RIGHT-side of Caravel interface
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assign ccff_head = io_in[12];
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assign io_out[12] = 1'b0;
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assign io_oeb[12] = 1'b1;
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assign io_out[11] = sc_tail;
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assign io_oeb[11] = 1'b0;
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assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12:20] = io_in[10:2];
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assign io_out[10:2] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12:20];
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assign io_oeb[10:2] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12:20];
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assign io_isol_n = io_in[1];
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assign io_out[1] = 1'b0;
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assign io_oeb[1] = 1'b1;
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assign Test_en = io_in[0];
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assign io_out[0] = 1'b0;
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assign io_oeb[0] = 1'b1;
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// Wire-bond RIGHT, BOTTOM, LEFT side I/O of FPGA to BOTTOM-side of Caravel interface
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// Autogenerate code start
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// Autogenerate code end
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// Wire-bond LEFT side I/O of FPGA to LEFT-side of Caravel interface
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assign prog_clk = io_in[37];
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assign io_out[37] = 1'b0;
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assign io_oeb[37] = 1'b1;
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// FPGA clock port can be driven by either wishbone clock or an GPIO
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assign clk = io_in[36];
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assign io_out[36] = 1'b0;
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assign io_oeb[36] = 1'b1;
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assign io_out[35] = ccff_tail;
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assign io_oeb[35] = 1'b0;
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assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[136:143] = io_in[34:27];
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assign io_out[34:27] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[136:143];
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assign io_oeb[34:27] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[136:143];
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assign sc_head = io_in[26];
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assign io_out[26] = 1'b0;
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assign io_oeb[26] = 1'b1;
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// I/O[25] is reserved for a switch between wishbone interface
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// and logic analyzer
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assign wb_la_switch = io_in[25];
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assign io_out[25] = 1'b0;
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assign io_oeb[25] = 1'b1;
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// TODO: Connect spypad from FPGA to logic analyzer ports
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fpga_core fpga_core_uut(.prog_clk(prog_clk),
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.Test_en(Test_en),
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.clk(clk),
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.IO_ISOL_N(io_isol_n),
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.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
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.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
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.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
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.ccff_head(ccff_head),
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.ccff_tail(ccff_tail),
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.sc_head(sc_head),
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.sc_tail(sc_tail)
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);
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endmodule
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