History

tangxifan 51a00d4612 Merge branch 'master' into xt_dev		2021-06-09 19:42:36 -06:00
..
FPGA1212_SOFA_HD_Verilog	[SOFA_HD] Updated netlist and task	2020-12-14 01:14:14 -07:00
FPGA1212_SOFA_HD_task	Merge branch 'master' into xt_dev	2021-06-09 19:42:36 -06:00
Verification	[SOFA_HD] Updated verification script	2020-12-14 01:16:30 -07:00
fpga_top	[DRCFix] Fixed filler cell boundary	2021-02-10 15:29:34 -07:00
modules	Updated all the results	2020-12-20 03:44:00 -07:00
Makefile	[SOFA1212] Updated SOFA Project	2021-04-05 23:29:01 -06:00
README.md	Updated all the results	2020-12-20 03:44:00 -07:00
config.sh	[SOFA1212] Updated SOFA Project	2021-04-05 23:29:01 -06:00

FPGA1212_SOFA_HD_PNR

12x12 FPGA designed using hierarchical flow and SKY130_FD_SC_HD. Flat Module design style