Tarachand Pagarani 053afc7c45 correct the VPR binding for netlist generation		2020-12-08 07:12:13 -08:00
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k4_N8_caravel_cc_fdhd_2x2	[Script] Update openfpga task-run script to use the adhoc simulation settings tuned for Caravel SoC	2020-11-17 15:03:10 -07:00
k4_N8_caravel_cc_fdhd_12x12	[Script] Add and2_or2 benchmark to the testbench generation script for 12x12 HD FPGA	2020-11-22 13:34:53 -07:00
k4_N8_reset_caravel_cc_fdhd_12x12	[Script] Bug fix in task configuration files	2020-11-27 15:05:35 -07:00
k4_N8_reset_softadder_caravel_cc_fdhd_12x12	[Script] Add task run for the architecture with both reset and soft adders	2020-11-27 18:15:05 -07:00
k4_N8_softadder_caravel_cc_fdhd_12x12	[Script] Add task run for softadder architecture	2020-11-27 16:14:14 -07:00
ql_ap3_vpr_routing_caravel_cc_fdhd_8x8	correct the VPR binding for netlist generation	2020-12-08 07:12:13 -08:00