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tangxifan a900cba5a5 [HDL] Bug fix in the pin assignment due to the conflicts on sc_tail and ccff_tail 2020-11-30 10:29:05 -07:00
..
README.md [Doc] Add README to HDL common files 2020-11-28 17:37:36 -07:00
caravel_fpga_wrapper_hd.v [HDL] Update wrapper using the new generator 2020-11-29 12:47:52 -07:00
caravel_fpga_wrapper_hd_template.v [HDL] Name fix to be compatible with testbench generation 2020-11-29 21:01:44 -07:00
caravel_wrapper_pin_assignment_v1.0.json [HDL] Bug fix in the pin assignment due to the conflicts on sc_tail and ccff_tail 2020-11-30 10:29:05 -07:00
caravel_wrapper_pin_assignment_v1.1.json [HDL] Bug fix in the pin assignment due to the conflicts on sc_tail and ccff_tail 2020-11-30 10:29:05 -07:00
digital_io_hd.v [HDL] Patch tech mapped netlists of digital I/O and remove the out-of-date behavoiral codes 2020-11-19 16:31:06 -07:00
sky130_fd_sc_hd_wrapper.v [HDL] Add a wrapper for HD MUX2 cell required by carry logic 2020-11-27 16:01:27 -07:00
skywater_function_verification.v [HDL] Add preprocessing flags for running functional verification 2020-11-05 11:29:23 -07:00
wrapper_lines_generator.py [HDL] bug fix in wrapper line generator 2020-11-29 12:47:22 -07:00

README.md

Skywater PDK

This directory contains the HDL netlists and code generator for FPGA fabrics.

  • caravel_fpga_wrapper_hd.v: The wrapper for FPGA fabric to interface the Caravel SoC, which is technology mapped to the Skywater 130nm Foundry High-Density Standard Cell Library. This file is automatically generated by a Python script
  • caravel_defines.v: The parameters required for Caravel wrapper HDL codes
  • caravel_fpga_wrapper_hd_template.v: The template HDL codes for the wrapper
  • digital_io_hd.v: the I/O cell used by High-density FPGA, which is technology mapped to the Skywater 130nm Foundry High-Density Standard Cell Library.
  • sky130_fd_sc_hd_wrapper.v: Wrapper codes for the standard cells from the Skywater 130nm Foundry High-Density Standard Cell Library
  • skywater_function_verification.v: Include pre-processing flags to enable functional verification for FPGAs
  • wrapper_lines_generator.py: Python script to generate the wrapper caravel_fpga_wrapper_hd.v