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FPGA88_SOFA_A_CCFF_Chain.svg
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Updated port names
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2023-03-01 15:59:04 -07:00 |
FPGA88_SOFA_A_clock0_combined_tree.svg
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Added clock tree
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2023-03-01 15:40:06 -07:00 |
FPGA88_SOFA_A_clock0_leve0_tree.svg
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Added clock tree
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2023-03-01 15:40:06 -07:00 |
FPGA88_SOFA_A_clock0_leve1_tree.svg
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Added clock tree
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2023-03-01 15:40:06 -07:00 |
FPGA88_SOFA_A_clock0_leve2_clear_tree.svg
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Added clock tree
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2023-03-01 15:40:06 -07:00 |
FPGA88_SOFA_A_clock0_leve2_tree.svg
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Added clock tree
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2023-03-01 15:40:06 -07:00 |
FPGA88_SOFA_A_floorplan.svg
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Updated CPP and SC_HEIGHT values
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2023-03-01 09:57:54 -07:00 |
FPGA88_SOFA_A_pre_tile_floorplan.svg
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Updated CPP and SC_HEIGHT values
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2023-03-01 09:57:54 -07:00 |
FPGA88_SOFA_A_raw_floorplan.svg
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Updated CPP and SC_HEIGHT values
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2023-03-01 09:57:54 -07:00 |
FPGA88_SOFA_A_render.svg
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Added SOFA-A project
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2023-03-01 09:31:42 -07:00 |
FPGA88_SOFA_A_restruct_render.svg
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Added global signal connectivity patterns
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2023-03-01 10:09:45 -07:00 |
config_enable_pattern.svg
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Added global signal connectivity patterns
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2023-03-01 10:09:45 -07:00 |
prog_reset_pattern.svg
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Added global signal connectivity patterns
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2023-03-01 10:09:45 -07:00 |
reset_pattern.svg
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Added global signal connectivity patterns
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2023-03-01 10:09:45 -07:00 |
test_enable_pattern.svg
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Added global signal connectivity patterns
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2023-03-01 10:09:45 -07:00 |