Ganesh Gore 9f9897c5e2 [SOFA-CHD] Updated design with mux-primitive bug fixed - Calibre DRC pending		2020-12-14 00:34:42 -07:00
..
lb	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
routing	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
sub_module	[SOFA-CHD] Updated design with mux-primitive bug fixed - Calibre DRC pending	2020-12-14 00:34:42 -07:00
InstancesMap.txt	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
define_simulation.v	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
fabric_netlists.v	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
fpga_core.v	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
fpga_defines.v	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
fpga_top.v	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
top_include_netlists.v	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00