riscv
/
SOFA
mirror of https://github.com/lnis-uofu/SOFA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
SOFA/FPGA1212_QLSOFA_HD_PNR
History
Ganesh Gore 7309d3822c [DRCFix] Fixed filler cell boundary 2021-02-10 22:43:08 -07:00
..
FPGA1212_QLSOFA_HD_Verilog [QLSOFA] Bugfix to fix floating cin net 2020-12-22 00:23:37 -07:00
FPGA1212_QLSOFA_HD_task Fix parsing error in FPGA1212_QLSOFA arch file. 2021-02-05 11:36:29 -06:00
Verification [QLSOFA_HD] Updated QLSOFA_HD Verification results 2020-12-14 13:38:08 -07:00
fpga_top [DRCFix] Fixed filler cell boundary 2021-02-10 22:43:08 -07:00
modules [QLSOFA] Bugfix to fix floating cin net 2020-12-22 00:23:37 -07:00
README.md Updated all the results 2020-12-20 03:44:00 -07:00
config.sh [QLSOFA] Bugfix to fix floating cin net 2020-12-22 00:23:37 -07:00

README.md

FPGA1212_FLAT_HD_SKY_PNR

12x12 FPGA designed using hierarchical flow and SKY130_FD_SC_HD. Flat Module design style