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SOFA/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC
History
Ganesh Gore 8b22960ddc [Design] Added FPGA22 design with SKY130_FD_SC_HD 2020-10-26 23:59:20 -06:00
..
lb [Design] Added FPGA22 design with SKY130_FD_SC_HD 2020-10-26 23:59:20 -06:00
routing [Design] Added FPGA22 design with SKY130_FD_SC_HD 2020-10-26 23:59:20 -06:00
sub_module [Design] Added FPGA22 design with SKY130_FD_SC_HD 2020-10-26 23:59:20 -06:00
define_simulation.v [Design] Added FPGA22 design with SKY130_FD_SC_HD 2020-10-26 23:59:20 -06:00
fabric_netlists.v [Design] Added FPGA22 design with SKY130_FD_SC_HD 2020-10-26 23:59:20 -06:00
fpga_core.v [Design] Added FPGA22 design with SKY130_FD_SC_HD 2020-10-26 23:59:20 -06:00
fpga_defines.v [Design] Added FPGA22 design with SKY130_FD_SC_HD 2020-10-26 23:59:20 -06:00
fpga_top.v [Design] Added FPGA22 design with SKY130_FD_SC_HD 2020-10-26 23:59:20 -06:00
top_autocheck_top_tb.v [Design] Added FPGA22 design with SKY130_FD_SC_HD 2020-10-26 23:59:20 -06:00
top_formal_random_top_tb.v [Design] Added FPGA22 design with SKY130_FD_SC_HD 2020-10-26 23:59:20 -06:00
top_include_netlists.v [Design] Added FPGA22 design with SKY130_FD_SC_HD 2020-10-26 23:59:20 -06:00
top_top_formal_verification.v [Design] Added FPGA22 design with SKY130_FD_SC_HD 2020-10-26 23:59:20 -06:00