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SOFA/FPGA22_HIER_SKY_PNR
History
Ganesh Gore 030679a518 dropped symbolic link 2020-10-27 11:21:20 -06:00
..
FPGA22_HIER_SKY_Verilog [Design] Added FPGA22 design with SKY130_FD_SC_HD 2020-10-26 23:59:20 -06:00
FPGA22_HIER_SKY_task dropped symbolic link 2020-10-27 11:21:20 -06:00
fpga_core [Design] Added FPGA22 design with SKY130_FD_SC_HD 2020-10-26 23:59:20 -06:00
modules [Design] Added FPGA22 design with SKY130_FD_SC_HD 2020-10-26 23:59:20 -06:00
README.md [Design] Added FPGA22 design with SKY130_FD_SC_HD 2020-10-26 23:59:20 -06:00

README.md

FPGA22_HIER_SKY_PNR

2x2 FPGA designed using hierarchical flow and SKY130_FD_SC_HD

Directory Structure

FPGA22_HIER_SKY_task :- OpenFPGA task directory and all related files FPGA22_HIER_SKY_Verilog :- Verilog-netlist used for this design modules :- Final files of each module (lef,def,spef,v,gds) fpga_core :- Final files of fpga_core (eFPGA design) fpga_top :- Reserved for design with GPIOs or caravel

Checks

  • .tech file DRC - Clean
  • Timing SignOff - Clean

Pending

  • Tap cell addition
  • DRC SignOff
  • PostPnR function simulation